source: rtems/bsps/powerpc/gen83xx/irq/irq.c @ e560ee85

Last change on this file since e560ee85 was e560ee85, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:55

bsps/powerpc/: Scripted embedded brains header file clean up

Updates #4625.
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File size: 19.4 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    embedded brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.org/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file integrates the IPIC irq controller                    |
18\*===============================================================*/
19
20#include <mpc83xx/mpc83xx.h>
21
22#include <rtems.h>
23
24#include <libcpu/powerpc-utility.h>
25#include <bsp/vectors.h>
26
27#include <bsp.h>
28#include <bsp/irq.h>
29#include <bsp/irq-generic.h>
30
31#define MPC83XX_IPIC_VECTOR_NUMBER 92
32
33#define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER)
34
35#define MPC83XX_IPIC_INVALID_MASK_POSITION 255
36
37typedef struct {
38  volatile uint32_t *pend_reg;
39  volatile uint32_t *mask_reg;
40  const uint32_t bit_num;
41} BSP_isrc_rsc_t;
42
43/*
44 * data structure to handle all mask registers in the IPIC
45 *
46 * Mask positions:
47 *   simsr [0] :  0 .. 31
48 *   simsr [1] : 32 .. 63
49 *   semsr     : 64 .. 95
50 *   sermr     : 96 .. 127
51 */
52typedef struct {
53  uint32_t simsr_mask [2];
54  uint32_t semsr_mask;
55  uint32_t sermr_mask;
56} mpc83xx_ipic_mask_t;
57
58static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = {
59  /* vector 0 */
60  {&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31},
61  {NULL, NULL, 0},
62  {NULL, NULL, 0},
63  {NULL, NULL, 0},
64  {NULL, NULL, 0},
65  {NULL, NULL, 0},
66  {NULL, NULL, 0},
67  {NULL, NULL, 0},
68  /* vector  8 */
69  {NULL, NULL, 0},  /* reserved vector  8 */
70  /* vector  9: UART1 SIxxR_H, Bit 24 */
71  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24},
72  /* vector 10: UART2 SIxxR_H, Bit 25 */
73  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25},
74  /* vector 11: SEC   SIxxR_H, Bit 26 */
75  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26},
76  {NULL, NULL, 0},  /* reserved vector 12 */
77  {NULL, NULL, 0},  /* reserved vector 13 */
78  /* vector 14: I2C1 SIxxR_H, Bit 29 */
79  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29},
80  /* vector 15: I2C2 SIxxR_H, Bit 30 */
81  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30},
82  /* vector 16: SPI  SIxxR_H, Bit 31 */
83  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31},
84  /* vector 17: IRQ1 SExxR  , Bit  1 */
85  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1},
86  /* vector 18: IRQ2 SExxR  , Bit  2 */
87  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2},
88  /* vector 19: IRQ3 SExxR  , Bit  3 */
89  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3},
90  /* vector 20: IRQ4 SExxR  , Bit  4 */
91  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4},
92  /* vector 21: IRQ5 SExxR  , Bit  5 */
93  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5},
94  /* vector 22: IRQ6 SExxR  , Bit  6 */
95  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6},
96  /* vector 23: IRQ7 SExxR  , Bit  7 */
97  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7},
98  {NULL, NULL, 0},  /* reserved vector 24 */
99  {NULL, NULL, 0},  /* reserved vector 25 */
100  {NULL, NULL, 0},  /* reserved vector 26 */
101  {NULL, NULL, 0},  /* reserved vector 27 */
102  {NULL, NULL, 0},  /* reserved vector 28 */
103  {NULL, NULL, 0},  /* reserved vector 29 */
104  {NULL, NULL, 0},  /* reserved vector 30 */
105  {NULL, NULL, 0},  /* reserved vector 31 */
106  /* vector 32: TSEC1 Tx  SIxxR_H  , Bit  0 */
107  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0},
108  /* vector 33: TSEC1 Rx  SIxxR_H  , Bit  1 */
109  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1},
110  /* vector 34: TSEC1 Err SIxxR_H  , Bit  2 */
111  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2},
112  /* vector 35: TSEC2 Tx  SIxxR_H  , Bit  3 */
113  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3},
114  /* vector 36: TSEC2 Rx  SIxxR_H  , Bit  4 */
115  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4},
116  /* vector 37: TSEC2 Err SIxxR_H  , Bit  5 */
117  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5},
118  /* vector 38: USB DR    SIxxR_H  , Bit  6 */
119  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6},
120  /* vector 39: USB MPH   SIxxR_H  , Bit  7 */
121  {&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7},
122  {NULL, NULL, 0},  /* reserved vector 40 */
123  {NULL, NULL, 0},  /* reserved vector 41 */
124  {NULL, NULL, 0},  /* reserved vector 42 */
125  {NULL, NULL, 0},  /* reserved vector 43 */
126  {NULL, NULL, 0},  /* reserved vector 44 */
127  {NULL, NULL, 0},  /* reserved vector 45 */
128  {NULL, NULL, 0},  /* reserved vector 46 */
129  {NULL, NULL, 0},  /* reserved vector 47 */
130  /* vector 48: IRQ0 SExxR  , Bit  0 */
131  {&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0},
132  {NULL, NULL, 0},  /* reserved vector 49 */
133  {NULL, NULL, 0},  /* reserved vector 50 */
134  {NULL, NULL, 0},  /* reserved vector 51 */
135  {NULL, NULL, 0},  /* reserved vector 52 */
136  {NULL, NULL, 0},  /* reserved vector 53 */
137  {NULL, NULL, 0},  /* reserved vector 54 */
138  {NULL, NULL, 0},  /* reserved vector 55 */
139  {NULL, NULL, 0},  /* reserved vector 56 */
140  {NULL, NULL, 0},  /* reserved vector 57 */
141  {NULL, NULL, 0},  /* reserved vector 58 */
142  {NULL, NULL, 0},  /* reserved vector 59 */
143  {NULL, NULL, 0},  /* reserved vector 60 */
144  {NULL, NULL, 0},  /* reserved vector 61 */
145  {NULL, NULL, 0},  /* reserved vector 62 */
146  {NULL, NULL, 0},  /* reserved vector 63 */
147  /* vector 64: RTC SEC   SIxxR_L  , Bit  0 */
148  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0},
149  /* vector 65: PIT       SIxxR_L  , Bit  1 */
150  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1},
151  /* vector 66: PCI1      SIxxR_L  , Bit  2 */
152  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2},
153  /* vector 67: PCI2      SIxxR_L  , Bit  3 */
154  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3},
155  /* vector 68: RTC ALR   SIxxR_L  , Bit  4 */
156  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4},
157  /* vector 69: MU        SIxxR_L  , Bit  5 */
158  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5},
159  /* vector 70: SBA       SIxxR_L  , Bit  6 */
160  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6},
161  /* vector 71: DMA       SIxxR_L  , Bit  7 */
162  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7},
163  /* vector 72: GTM4      SIxxR_L  , Bit  8 */
164  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8},
165  /* vector 73: GTM8      SIxxR_L  , Bit  9 */
166  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9},
167  /* vector 74: GPIO1     SIxxR_L  , Bit 10 */
168  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10},
169  /* vector 75: GPIO2     SIxxR_L  , Bit 11 */
170  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11},
171  /* vector 76: DDR       SIxxR_L  , Bit 12 */
172  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12},
173  /* vector 77: LBC       SIxxR_L  , Bit 13 */
174  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13},
175  /* vector 78: GTM2      SIxxR_L  , Bit 14 */
176  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14},
177  /* vector 79: GTM6      SIxxR_L  , Bit 15 */
178  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15},
179  /* vector 80: PMC       SIxxR_L  , Bit 16 */
180  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16},
181  {NULL, NULL, 0},  /* reserved vector 81 */
182  {NULL, NULL, 0},  /* reserved vector 82 */
183  {NULL, NULL, 0},  /* reserved vector 63 */
184  /* vector 84: GTM3      SIxxR_L  , Bit 20 */
185  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20},
186  /* vector 85: GTM7      SIxxR_L  , Bit 21 */
187  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21},
188  {NULL, NULL, 0},  /* reserved vector 81 */
189  {NULL, NULL, 0},  /* reserved vector 82 */
190  {NULL, NULL, 0},  /* reserved vector 63 */
191  {NULL, NULL, 0},  /* reserved vector 63 */
192  /* vector 90: GTM1      SIxxR_L  , Bit 26 */
193  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26},
194  /* vector 91: GTM5      SIxxR_L  , Bit 27 */
195  {&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27}
196};
197
198static const uint8_t
199    mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = {
200  MPC83XX_IPIC_INVALID_MASK_POSITION,
201  MPC83XX_IPIC_INVALID_MASK_POSITION,
202  MPC83XX_IPIC_INVALID_MASK_POSITION,
203  MPC83XX_IPIC_INVALID_MASK_POSITION,
204  MPC83XX_IPIC_INVALID_MASK_POSITION,
205  MPC83XX_IPIC_INVALID_MASK_POSITION,
206  MPC83XX_IPIC_INVALID_MASK_POSITION,
207  MPC83XX_IPIC_INVALID_MASK_POSITION,
208  MPC83XX_IPIC_INVALID_MASK_POSITION,
209  7,
210  6,
211  5,
212  MPC83XX_IPIC_INVALID_MASK_POSITION,
213  MPC83XX_IPIC_INVALID_MASK_POSITION,
214  2,
215  1,
216  0,
217  94,
218  93,
219  92,
220  91,
221  90,
222  89,
223  88,
224  MPC83XX_IPIC_INVALID_MASK_POSITION,
225  MPC83XX_IPIC_INVALID_MASK_POSITION,
226  MPC83XX_IPIC_INVALID_MASK_POSITION,
227  MPC83XX_IPIC_INVALID_MASK_POSITION,
228  MPC83XX_IPIC_INVALID_MASK_POSITION,
229  MPC83XX_IPIC_INVALID_MASK_POSITION,
230  MPC83XX_IPIC_INVALID_MASK_POSITION,
231  MPC83XX_IPIC_INVALID_MASK_POSITION,
232  31,
233  30,
234  29,
235  28,
236  27,
237  26,
238  25,
239  24,
240  MPC83XX_IPIC_INVALID_MASK_POSITION,
241  MPC83XX_IPIC_INVALID_MASK_POSITION,
242  MPC83XX_IPIC_INVALID_MASK_POSITION,
243  MPC83XX_IPIC_INVALID_MASK_POSITION,
244  MPC83XX_IPIC_INVALID_MASK_POSITION,
245  MPC83XX_IPIC_INVALID_MASK_POSITION,
246  MPC83XX_IPIC_INVALID_MASK_POSITION,
247  MPC83XX_IPIC_INVALID_MASK_POSITION,
248  95,
249  MPC83XX_IPIC_INVALID_MASK_POSITION,
250  MPC83XX_IPIC_INVALID_MASK_POSITION,
251  MPC83XX_IPIC_INVALID_MASK_POSITION,
252  MPC83XX_IPIC_INVALID_MASK_POSITION,
253  MPC83XX_IPIC_INVALID_MASK_POSITION,
254  MPC83XX_IPIC_INVALID_MASK_POSITION,
255  MPC83XX_IPIC_INVALID_MASK_POSITION,
256  MPC83XX_IPIC_INVALID_MASK_POSITION,
257  MPC83XX_IPIC_INVALID_MASK_POSITION,
258  MPC83XX_IPIC_INVALID_MASK_POSITION,
259  MPC83XX_IPIC_INVALID_MASK_POSITION,
260  MPC83XX_IPIC_INVALID_MASK_POSITION,
261  MPC83XX_IPIC_INVALID_MASK_POSITION,
262  MPC83XX_IPIC_INVALID_MASK_POSITION,
263  MPC83XX_IPIC_INVALID_MASK_POSITION,
264  63,
265  62,
266  61,
267  60,
268  59,
269  58,
270  57,
271  56,
272  55,
273  54,
274  53,
275  52,
276  51,
277  50,
278  49,
279  48,
280  47,
281  MPC83XX_IPIC_INVALID_MASK_POSITION,
282  MPC83XX_IPIC_INVALID_MASK_POSITION,
283  MPC83XX_IPIC_INVALID_MASK_POSITION,
284  43,
285  42,
286  MPC83XX_IPIC_INVALID_MASK_POSITION,
287  MPC83XX_IPIC_INVALID_MASK_POSITION,
288  MPC83XX_IPIC_INVALID_MASK_POSITION,
289  MPC83XX_IPIC_INVALID_MASK_POSITION,
290  37,
291  36
292};
293
294/*
295 * this array will be filled with mask values needed
296 * to temporarily disable all IRQ soures with lower or same
297 * priority of the current source (whose vector is the array index)
298 */
299static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER];
300
301rtems_status_code mpc83xx_ipic_set_mask(
302  rtems_vector_number vector,
303  rtems_vector_number mask_vector,
304  bool mask
305)
306{
307  uint8_t pos = 0;
308  mpc83xx_ipic_mask_t *mask_entry;
309  uint32_t *mask_reg;
310  rtems_interrupt_level level;
311
312  /* Parameter check */
313  if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) ||
314      !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
315    return RTEMS_INVALID_NUMBER;
316  } else if (vector == mask_vector) {
317    return RTEMS_RESOURCE_IN_USE;
318  }
319
320  /* Position and mask entry */
321  pos = mpc83xx_ipic_mask_position_table [mask_vector];
322  mask_entry = &mpc83xx_ipic_prio2mask [vector];
323
324  /* Mask register and position */
325  if (pos < 32) {
326    mask_reg = &mask_entry->simsr_mask [0];
327  } else if (pos < 64) {
328    pos -= 32;
329    mask_reg = &mask_entry->simsr_mask [1];
330  } else if (pos < 96) {
331    pos -= 64;
332    mask_reg = &mask_entry->semsr_mask;
333  } else if (pos < 128) {
334    pos -= 96;
335    mask_reg = &mask_entry->sermr_mask;
336  } else {
337    return RTEMS_NOT_IMPLEMENTED;
338  }
339
340  /* Mask or unmask */
341  if (mask) {
342    rtems_interrupt_disable( level);
343    *mask_reg &= ~(1 << pos);
344    rtems_interrupt_enable( level);
345  } else {
346    rtems_interrupt_disable( level);
347    *mask_reg |= 1 << pos;
348    rtems_interrupt_enable( level);
349  }
350
351  return RTEMS_SUCCESSFUL;
352}
353
354rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt(
355  rtems_vector_number vector,
356  int type
357)
358{
359  rtems_interrupt_level level;
360  uint32_t reg = 0;
361
362  if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) {
363    return RTEMS_INVALID_NUMBER;
364  } else if (type < 0 || type > MPC83XX_IPIC_INTERRUPT_CRITICAL) {
365    return RTEMS_INVALID_NUMBER;
366  }
367
368  rtems_interrupt_disable( level);
369  reg = mpc83xx.ipic.sicfr;
370  mpc83xx.ipic.sicfr = (reg & ~0x7f000300) | (vector << 24) | (type << 8);
371  rtems_interrupt_enable( level);
372
373  return RTEMS_SUCCESSFUL;
374}
375
376/*
377 * functions to enable/disable a source at the ipic
378 */
379rtems_status_code bsp_interrupt_get_attributes(
380  rtems_vector_number         vector,
381  rtems_interrupt_attributes *attributes
382)
383{
384  return RTEMS_SUCCESSFUL;
385}
386
387rtems_status_code bsp_interrupt_is_pending(
388  rtems_vector_number vector,
389  bool               *pending
390)
391{
392  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
393  bsp_interrupt_assert(pending != NULL);
394  *pending = false;
395  return RTEMS_UNSATISFIED;
396}
397
398rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
399{
400  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
401  return RTEMS_UNSATISFIED;
402}
403
404rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
405{
406  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
407  return RTEMS_UNSATISFIED;
408}
409
410rtems_status_code bsp_interrupt_vector_is_enabled(
411  rtems_vector_number vector,
412  bool               *enabled
413)
414{
415  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
416  bsp_interrupt_assert(enabled != NULL);
417  *enabled = false;
418  return RTEMS_UNSATISFIED;
419}
420
421rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector)
422{
423  rtems_vector_number vecnum = vector - BSP_IPIC_IRQ_LOWEST_OFFSET;
424  const BSP_isrc_rsc_t *rsc_ptr;
425
426  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
427
428  if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
429    rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
430    if (rsc_ptr->mask_reg != NULL) {
431      uint32_t bit = 1U << (31 - rsc_ptr->bit_num);
432      rtems_interrupt_level level;
433
434      rtems_interrupt_disable(level);
435      *(rsc_ptr->mask_reg) |= bit;
436      rtems_interrupt_enable(level);
437    }
438  }
439
440  return RTEMS_SUCCESSFUL;
441}
442
443rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector)
444{
445  rtems_vector_number vecnum = vector - BSP_IPIC_IRQ_LOWEST_OFFSET;
446  const BSP_isrc_rsc_t *rsc_ptr;
447
448  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
449
450  if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
451    rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
452    if (rsc_ptr->mask_reg != NULL) {
453      uint32_t bit = 1U << (31 - rsc_ptr->bit_num);
454      rtems_interrupt_level level;
455
456      rtems_interrupt_disable(level);
457      *(rsc_ptr->mask_reg) &= ~bit;
458      rtems_interrupt_enable(level);
459    }
460  }
461
462  return RTEMS_SUCCESSFUL;
463}
464
465/*
466 *  IRQ Handler: this is called from the primary exception dispatcher
467 */
468static int BSP_irq_handle_at_ipic( unsigned excNum)
469{
470  int32_t vecnum;
471#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
472  mpc83xx_ipic_mask_t mask_save;
473  const mpc83xx_ipic_mask_t *mask_ptr;
474  uint32_t msr = 0;
475  rtems_interrupt_level level;
476#endif
477
478  /* Get vector number */
479  switch (excNum) {
480    case ASM_EXT_VECTOR:
481      vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr);
482      break;
483    case ASM_E300_SYSMGMT_VECTOR:
484      vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr);
485      break;
486    case ASM_E300_CRIT_VECTOR:
487      vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr);
488      break;
489    default:
490      return 1;
491  }
492
493  /*
494   * Check the vector number, mask lower priority interrupts, enable
495   * exceptions and dispatch the handler.
496   */
497  if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
498#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
499    mask_ptr = &mpc83xx_ipic_prio2mask [vecnum];
500
501    rtems_interrupt_disable( level);
502
503    /* Save current mask registers */
504    mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0];
505    mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1];
506    mask_save.semsr_mask = mpc83xx.ipic.semsr;
507    mask_save.sermr_mask = mpc83xx.ipic.sermr;
508
509    /* Mask all lower priority interrupts */
510    mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0];
511    mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1];
512    mpc83xx.ipic.semsr &= mask_ptr->semsr_mask;
513    mpc83xx.ipic.sermr &= mask_ptr->sermr_mask;
514
515    rtems_interrupt_enable( level);
516
517    /* Enable all interrupts */
518    if (excNum != ASM_E300_CRIT_VECTOR) {
519      msr = ppc_external_exceptions_enable();
520    }
521#endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */
522
523    /* Dispatch interrupt handlers */
524    bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET);
525
526#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
527    /* Restore machine state */
528    if (excNum != ASM_E300_CRIT_VECTOR) {
529      ppc_external_exceptions_disable( msr);
530    }
531
532    /* Restore initial masks */
533    rtems_interrupt_disable( level);
534    mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0];
535    mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1];
536    mpc83xx.ipic.semsr = mask_save.semsr_mask;
537    mpc83xx.ipic.sermr = mask_save.sermr_mask;
538    rtems_interrupt_enable( level);
539#endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */
540  } else {
541    bsp_interrupt_handler_default( vecnum);
542  }
543
544  return 0;
545}
546
547/*
548 * Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources
549 * to implement nested interrupts.
550 */
551static void mpc83xx_ipic_calc_prio2mask(void)
552{
553  /*
554   * FIXME: fill the array
555   */
556}
557
558/*
559 * Activate the interrupt controller
560 */
561static void mpc83xx_ipic_initialize(void)
562{
563  /*
564   * mask off all interrupts
565   */
566  mpc83xx.ipic.simsr [0] = 0;
567  mpc83xx.ipic.simsr [1] = 0;
568  mpc83xx.ipic.semsr = 0;
569  mpc83xx.ipic.sermr = 0;
570  /*
571   * set desired configuration as defined in bspopts.h
572   * normally, the default values should be fine
573   */
574#if defined( BSP_SICFR_VAL)  /* defined in bspopts.h ? */
575  mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
576#endif
577
578  /*
579   * set desired priorities as defined in bspopts.h
580   * normally, the default values should be fine
581   */
582#if defined( BSP_SIPRR0_VAL)  /* defined in bspopts.h ? */
583  mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL;
584#endif
585
586#if defined( BSP_SIPRR1_VAL)  /* defined in bspopts.h ? */
587  mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL;
588#endif
589
590#if defined( BSP_SIPRR2_VAL)  /* defined in bspopts.h ? */
591  mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL;
592#endif
593
594#if defined( BSP_SIPRR3_VAL)  /* defined in bspopts.h ? */
595  mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL;
596#endif
597
598#if defined( BSP_SMPRR0_VAL)  /* defined in bspopts.h ? */
599  mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL;
600#endif
601
602#if defined( BSP_SMPRR1_VAL)  /* defined in bspopts.h ? */
603  mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL;
604#endif
605
606#if defined( BSP_SECNR_VAL)  /* defined in bspopts.h ? */
607  mpc83xx.ipic.secnr = BSP_SECNR_VAL;
608#endif
609
610  /*
611   * calculate priority masks
612   */
613  mpc83xx_ipic_calc_prio2mask();
614}
615
616static int mpc83xx_exception_handler(
617  BSP_Exception_frame *frame,
618  unsigned exception_number
619)
620{
621  return BSP_irq_handle_at_ipic( exception_number);
622}
623
624void bsp_interrupt_facility_initialize()
625{
626  rtems_status_code sc;
627
628  /* Install exception handler */
629  sc = ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler);
630  _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL);
631  sc = ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler);
632  _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL);
633  sc = ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler);
634  _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL);
635
636  /* Initialize the interrupt controller */
637  mpc83xx_ipic_initialize();
638}
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