source: rtems/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*===============================================================*\
2| Project: RTEMS generic MPC83xx BSP                              |
3+-----------------------------------------------------------------+
4|                    Copyright (c) 2007                           |
5|                    Embedded Brains GmbH                         |
6|                    Obere Lagerstr. 30                           |
7|                    D-82178 Puchheim                             |
8|                    Germany                                      |
9|                    rtems@embedded-brains.de                     |
10+-----------------------------------------------------------------+
11| The license and distribution terms for this file may be         |
12| found in the file LICENSE in this distribution or at            |
13|                                                                 |
14| http://www.rtems.org/license/LICENSE.                           |
15|                                                                 |
16+-----------------------------------------------------------------+
17| this file contains board specific definitions                   |
18\*===============================================================*/
19
20
21#ifndef __GEN83xx_HWREG_VALS_h
22#define __GEN83xx_HWREG_VALS_h
23
24#include <mpc83xx/mpc83xx.h>
25#include <bsp.h>
26
27#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0
28  #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND)
29#else
30  #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY)
31#endif
32
33/*
34 * distinguish board characteristics
35 */
36#if defined(MPC83XX_BOARD_MPC8349EAMDS)
37/*
38 * for Freescale MPC8349 EAMDS
39 */
40/*
41 * two DUART channels supported
42 */
43#define GEN83xx_DUART_AVAIL_MASK 0x03
44
45/* we need the low level initialization in start.S*/
46#define NEED_LOW_LEVEL_INIT
47/*
48 * clocking infos
49 */
50#define BSP_CLKIN_FRQ 66000000L
51#define RCFG_SYSPLL_MF 4
52#define RCFG_COREPLL_MF 4
53
54/*
55 * Reset configuration words
56 */
57#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
58                          RCWLR_DDRCM_1_1  |    \
59                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
60                          RCWLR_COREPLL(RCFG_COREPLL_MF))
61
62#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
63                          RCWHR_PCI_32       |  \
64                          RCWHR_PCI1ARB_EN   |  \
65                          RCWHR_PCI2ARB_EN   |  \
66                          RCWHR_CORE_EN      |  \
67                          RCWHR_BMS_LOW      |  \
68                          RCWHR_BOOTSEQ_NONE |  \
69                          RCWHR_SW_DIS       |  \
70                          MPC83XX_RCWHR_BOOT_DEVICE | \
71                          RCWHR_TSEC1M_GMII  |  \
72                          RCWHR_TSEC2M_GMII  |  \
73                          RCWHR_ENDIAN_BIG   |  \
74                          RCWHR_LALE_NORM    |  \
75                          RCWHR_LDP_PAR)
76#elif defined(MPC83XX_BOARD_HSC_CM01)
77/*
78 * for JPK HSC_CM01
79 */
80/*
81 * one DUART channel (UART1) supported
82 */
83#define GEN83xx_DUART_AVAIL_MASK 0x01
84
85/* we need the low level initialization in start.S*/
86#define NEED_LOW_LEVEL_INIT
87/*
88 * clocking infos
89 */
90#define BSP_CLKIN_FRQ 30000000L
91#define RCFG_SYSPLL_MF 11
92#define RCFG_COREPLL_MF 4
93/*
94 * Reset configuration words
95 */
96#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
97                          RCWLR_DDRCM_1_1  |    \
98                          RCWLR_SPMF(RCFG_SYSPLL_MF)    |       \
99                          RCWLR_COREPLL(RCFG_COREPLL_MF))
100
101#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
102                          RCWHR_PCI_32       |  \
103                          RCWHR_PCI1ARB_DIS  |  \
104                          RCWHR_PCI2ARB_DIS  |  \
105                          RCWHR_CORE_EN      |  \
106                          RCWHR_BMS_LOW      |  \
107                          RCWHR_BOOTSEQ_NONE |  \
108                          RCWHR_SW_DIS       |  \
109                          MPC83XX_RCWHR_BOOT_DEVICE | \
110                          RCWHR_TSEC1M_RGMII |  \
111                          RCWHR_TSEC2M_GMII  |  \
112                          RCWHR_ENDIAN_BIG   |  \
113                          RCWHR_LALE_EARLY   |  \
114                          RCWHR_LDP_SPC)
115
116#elif defined(MPC83XX_BOARD_BR_UID)
117/*
118 * for BR UID
119 */
120/*
121 * one DUART channel (UART1) supported
122 */
123#define GEN83xx_DUART_AVAIL_MASK 0x01
124
125/* we need the low level initialization in start.S*/
126#define NEED_LOW_LEVEL_INIT
127/*
128 * clocking infos
129 */
130#define BSP_CLKIN_FRQ 25000000L
131#define RCFG_SYSPLL_MF  5
132#define RCFG_COREPLL_MF 5
133/*
134 * Reset configuration words
135 */
136#define RESET_CONF_WRD_L \
137  (RCWLR_LBIUCM_1_1                                                     \
138   | RCWLR_DDRCM_2_1                                                    \
139   | RCWLR_SPMF(RCFG_SYSPLL_MF)                                         \
140   | RCWLR_COREPLL(RCFG_COREPLL_MF)                                     \
141   | RCWLR_CEVCOD_1_2                                                   \
142   | RCWLR_CEPMF(8)                                                     \
143   )
144
145#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
146                          RCWHR_PCI_32       |  \
147                          RCWHR_PCI1ARB_DIS  |  \
148                          RCWHR_CORE_EN      |  \
149                          RCWHR_BMS_LOW      |  \
150                          RCWHR_BOOTSEQ_NONE |  \
151                          RCWHR_SW_DIS       |  \
152                          MPC83XX_RCWHR_BOOT_DEVICE |   \
153                          RCWHR_ENDIAN_BIG)
154
155#elif defined( HAS_UBOOT)
156
157/* TODO */
158
159#else
160
161#error "board type not defined"
162
163#endif
164
165#if defined(MPC83XX_BOARD_MPC8349EAMDS)
166/**************************
167 * for Freescale MPC83XX_BOARD_MPC8349EAMDS
168 */
169
170/*
171 * working values for various registers, used in start/start.S
172 */
173
174/*
175 * Local Access Windows
176 * FIXME: decode bit settings
177 */
178#define LBLAWBAR0_VAL  0xFE000000
179#define LBLAWAR0_VAL   0x80000016
180#define LBLAWBAR1_VAL  0xF8000000
181#define LBLAWAR1_VAL   0x8000000E
182#define LBLAWBAR2_VAL  0xF0000000
183#define LBLAWAR2_VAL   0x80000019
184#define DDRLAWBAR0_VAL 0x00000000
185#define DDRLAWAR0_VAL  0x8000001B
186/*
187 * Local Bus (Memory) Controller
188 * FIXME: decode bit settings
189 */
190#define BR0_VAL 0xFE001001
191#define OR0_VAL 0xFF806FF7
192#define BR1_VAL 0xF8000801
193#define OR1_VAL 0xFFFFE8F0
194#define BR2_VAL 0xF0001861
195#define OR2_VAL 0xFC006901
196/*
197 * SDRAM registers
198 * FIXME: decode bit settings
199 */
200#define MRPTR_VAL 0x20000000
201#define LSRT_VAL  0x32000000
202#define LSDMR_VAL 0x4062D733
203#define LCRR_VAL  0x80000004
204
205/*
206 * DDR-SDRAM registers
207 * FIXME: decode bit settings
208 */
209#define CS2_BNDS_VAL                 0x00000007
210#define CS3_BNDS_VAL                 0x0008000F
211#define CS2_CONFIG_VAL               0x80000101
212#define CS3_CONFIG_VAL               0x80000101
213#define TIMING_CFG_1_VAL             0x36333321
214#define TIMING_CFG_2_VAL             0x00000800
215#define DDR_SDRAM_CFG_VAL            0xC2000000
216#define DDR_SDRAM_MODE_VAL           0x00000022
217#define DDR_SDRAM_INTTVL_VAL         0x045B0100
218#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
219
220#elif defined(MPC83XX_BOARD_HSC_CM01)
221/**************************
222 * for JPK HSC_CM01
223 */
224
225/* fpga BCSR register */
226#define FPGA_START 0xF8000000
227#define FPGA_SIZE  0x8000
228#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
229
230/*
231 * working values for various registers, used in start/start.S
232 */
233
234/* fpga config 16 MB size */
235#define FPGA_CONFIG_START       0xF8000000
236#define FPGA_CONFIG_SIZE        0x01000000
237/* fpga register 8 MB size */
238#define FPGA_REGISTER_START     0xF9000000
239#define FPGA_REGISTER_SIZE      0x00800000
240/* fpga fifo 8 MB size */
241#define FPGA_FIFO_START         0xF9800000
242#define FPGA_FIFO_SIZE          0x00800000
243
244#define FPGA_START (FPGA_CONFIG_START)
245// fpga window size 32 MByte
246#define FPGA_SIZE  (0x02000000)
247#define FPGA_END   (FPGA_START+FPGA_SIZE-1)
248
249/*
250 * Local Access Windows
251 * FIXME: decode bit settings
252 */
253
254#define LBLAWBAR0_VAL  bsp_rom_start
255#define LBLAWAR0_VAL   0x80000018
256#define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
257#define LBLAWAR1_VAL   0x80000018
258#define DDRLAWBAR0_VAL bsp_ram_start
259#define DDRLAWAR0_VAL  0x8000001B
260/*
261 * Local Bus (Memory) Controller
262 * FIXME: decode bit settings
263 */
264#define BR0_VAL (0xFE000000 | 0x01001)
265#define OR0_VAL 0xFE000E54
266// fpga config access range (UPM_A) (32 kByte)
267#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
268#define OR2_VAL 0xFFFF9100
269
270// fpga register access range (UPM_B) (8 MByte)
271#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
272#define OR3_VAL 0xFF801100
273
274// fpga fifo access range (UPM_C) (8 MByte)
275#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
276#define OR4_VAL 0xFF801100
277
278/*
279 * SDRAM registers
280 */
281#define MRPTR_VAL 0x20000000
282#define LSRT_VAL  0x32000000
283#define LSDMR_VAL 0x4062D733
284#define LCRR_VAL  0x80010004
285
286/*
287 * DDR-SDRAM registers
288 * FIXME: decode bit settings
289 */
290#define DDRCDR_VAL                   0x00000001
291#define CS0_BNDS_VAL                 0x0000000F
292#define CS0_CONFIG_VAL               0x80810102
293#define TIMING_CFG_0_VAL             0x00420802
294#define TIMING_CFG_1_VAL             0x3735A322
295#define TIMING_CFG_2_VAL             0x2F9044C7
296#define DDR_SDRAM_CFG_2_VAL          0x00401000
297#define DDR_SDRAM_MODE_VAL           0x44521632
298#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
299#define DDR_SDRAM_CFG_VAL            0x63000008
300
301#define DDR_ERR_DISABLE_VAL          0x0000008D
302#define DDR_ERR_DISABLE_VAL2         0x00000089
303#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
304#define DDR_SDRAM_INIT_ADDR_VAL      0
305#define DDR_SDRAM_INTERVAL_VAL       0x05080000
306
307#elif defined(MPC83XX_BOARD_BR_UID)
308/**************************
309 * for BR UID
310 */
311
312/*
313 * working values for various registers, used in start/start.S
314 */
315
316/*
317 * Local Access Windows
318 * FIXME: decode bit settings
319 */
320
321#define LBLAWBAR0_VAL  bsp_rom_start
322#define LBLAWAR0_VAL   0x80000018
323#define DDRLAWBAR0_VAL bsp_ram_start
324#define DDRLAWAR0_VAL  0x8000001B
325
326
327/*
328 * clocking for local bus:
329 * ALE active for 1 clock
330 * local bus clock = 1/2 csb clock
331 */
332#define LCRR_VAL  0x80010002
333
334/*
335 * DDR-SDRAM registers
336 * FIXME: decode bit settings
337 */
338#define DDRCDR_VAL                   0x00000001
339#define CS0_BNDS_VAL                 0x0000000F
340#define CS0_CONFIG_VAL               0x80014202
341#define TIMING_CFG_0_VAL             0x00220802
342#define TIMING_CFG_1_VAL             0x26259222
343#define TIMING_CFG_2_VAL             0x111048C7
344#define DDR_SDRAM_CFG_2_VAL          0x00401000
345#define DDR_SDRAM_MODE_VAL           0x200F1632
346#define DDR_SDRAM_MODE_2_VAL         0x40006000
347#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
348#define DDR_SDRAM_CFG_VAL            0x43100008
349
350#define DDR_ERR_DISABLE_VAL          0x0000008D
351#define DDR_ERR_DISABLE_VAL2         0x00000089
352#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
353#define DDR_SDRAM_INIT_ADDR_VAL      0
354#define DDR_SDRAM_INTERVAL_VAL       0x01E8222E
355
356#elif defined( HAS_UBOOT)
357
358/* TODO */
359
360#else
361
362#error "board type not defined"
363
364#endif
365
366/**************************
367 * derived values for all boards
368 */
369/* value of input clock divider (derived from pll mode reg) */
370#if MPC83XX_CHIP_TYPE != 8309
371  #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
372#else
373  /* On the MPC8309 this bit is reserved */
374  #define BSP_SYSPLL_CKID 1
375#endif
376/* value of system pll (derived from pll mode reg) */
377#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
378/* value of system pll (derived from pll mode reg) */
379#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f)
380
381#endif /* __GEN83xx_HWREG_VALS_h */
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