[42bf1b9] | 1 | /*===============================================================*\ |
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| 2 | | Project: RTEMS generic MPC83xx BSP | |
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| 3 | +-----------------------------------------------------------------+ |
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| 4 | | Copyright (c) 2007 | |
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| 5 | | Embedded Brains GmbH | |
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| 6 | | Obere Lagerstr. 30 | |
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| 7 | | D-82178 Puchheim | |
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| 8 | | Germany | |
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| 9 | | rtems@embedded-brains.de | |
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| 10 | +-----------------------------------------------------------------+ |
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| 11 | | The license and distribution terms for this file may be | |
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| 12 | | found in the file LICENSE in this distribution or at | |
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| 13 | | | |
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[c499856] | 14 | | http://www.rtems.org/license/LICENSE. | |
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[42bf1b9] | 15 | | | |
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| 16 | +-----------------------------------------------------------------+ |
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| 17 | | this file contains board specific definitions | |
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| 18 | \*===============================================================*/ |
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| 19 | |
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[e570c313] | 20 | |
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[42bf1b9] | 21 | #ifndef __GEN83xx_HWREG_VALS_h |
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| 22 | #define __GEN83xx_HWREG_VALS_h |
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| 23 | |
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| 24 | #include <mpc83xx/mpc83xx.h> |
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[4b23c94] | 25 | #include <bsp.h> |
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[907b07d9] | 26 | |
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| 27 | #ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0 |
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| 28 | #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND) |
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| 29 | #else |
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| 30 | #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY) |
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| 31 | #endif |
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| 32 | |
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[42bf1b9] | 33 | /* |
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| 34 | * distinguish board characteristics |
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| 35 | */ |
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[7a752161] | 36 | #if defined(MPC83XX_BOARD_MPC8349EAMDS) |
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[42bf1b9] | 37 | /* |
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| 38 | * for Freescale MPC8349 EAMDS |
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| 39 | */ |
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| 40 | /* |
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| 41 | * two DUART channels supported |
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| 42 | */ |
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| 43 | #define GEN83xx_DUART_AVAIL_MASK 0x03 |
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| 44 | |
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| 45 | /* we need the low level initialization in start.S*/ |
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| 46 | #define NEED_LOW_LEVEL_INIT |
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| 47 | /* |
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| 48 | * clocking infos |
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| 49 | */ |
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| 50 | #define BSP_CLKIN_FRQ 66000000L |
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[ac7af4a] | 51 | #define RCFG_SYSPLL_MF 4 |
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[42bf1b9] | 52 | #define RCFG_COREPLL_MF 4 |
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| 53 | |
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| 54 | /* |
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| 55 | * Reset configuration words |
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| 56 | */ |
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| 57 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 58 | RCWLR_DDRCM_1_1 | \ |
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| 59 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 60 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 61 | |
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| 62 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 63 | RCWHR_PCI_32 | \ |
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| 64 | RCWHR_PCI1ARB_EN | \ |
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| 65 | RCWHR_PCI2ARB_EN | \ |
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| 66 | RCWHR_CORE_EN | \ |
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| 67 | RCWHR_BMS_LOW | \ |
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| 68 | RCWHR_BOOTSEQ_NONE | \ |
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| 69 | RCWHR_SW_DIS | \ |
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[907b07d9] | 70 | MPC83XX_RCWHR_BOOT_DEVICE | \ |
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[42bf1b9] | 71 | RCWHR_TSEC1M_GMII | \ |
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| 72 | RCWHR_TSEC2M_GMII | \ |
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| 73 | RCWHR_ENDIAN_BIG | \ |
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| 74 | RCWHR_LALE_NORM | \ |
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| 75 | RCWHR_LDP_PAR) |
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[7a752161] | 76 | #elif defined(MPC83XX_BOARD_HSC_CM01) |
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[42bf1b9] | 77 | /* |
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| 78 | * for JPK HSC_CM01 |
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| 79 | */ |
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| 80 | /* |
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| 81 | * one DUART channel (UART1) supported |
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| 82 | */ |
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| 83 | #define GEN83xx_DUART_AVAIL_MASK 0x01 |
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| 84 | |
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| 85 | /* we need the low level initialization in start.S*/ |
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| 86 | #define NEED_LOW_LEVEL_INIT |
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| 87 | /* |
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| 88 | * clocking infos |
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| 89 | */ |
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| 90 | #define BSP_CLKIN_FRQ 30000000L |
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[ac7af4a] | 91 | #define RCFG_SYSPLL_MF 11 |
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[42bf1b9] | 92 | #define RCFG_COREPLL_MF 4 |
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| 93 | /* |
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| 94 | * Reset configuration words |
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| 95 | */ |
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| 96 | #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ |
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| 97 | RCWLR_DDRCM_1_1 | \ |
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| 98 | RCWLR_SPMF(RCFG_SYSPLL_MF) | \ |
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| 99 | RCWLR_COREPLL(RCFG_COREPLL_MF)) |
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| 100 | |
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| 101 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 102 | RCWHR_PCI_32 | \ |
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[4b23c94] | 103 | RCWHR_PCI1ARB_DIS | \ |
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| 104 | RCWHR_PCI2ARB_DIS | \ |
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[42bf1b9] | 105 | RCWHR_CORE_EN | \ |
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| 106 | RCWHR_BMS_LOW | \ |
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| 107 | RCWHR_BOOTSEQ_NONE | \ |
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| 108 | RCWHR_SW_DIS | \ |
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[907b07d9] | 109 | MPC83XX_RCWHR_BOOT_DEVICE | \ |
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[42bf1b9] | 110 | RCWHR_TSEC1M_RGMII | \ |
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| 111 | RCWHR_TSEC2M_GMII | \ |
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| 112 | RCWHR_ENDIAN_BIG | \ |
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[4b23c94] | 113 | RCWHR_LALE_EARLY | \ |
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| 114 | RCWHR_LDP_SPC) |
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[574fb67] | 115 | |
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[d9af2ed4] | 116 | #elif defined(MPC83XX_BOARD_BR_UID) |
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| 117 | /* |
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| 118 | * for BR UID |
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| 119 | */ |
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| 120 | /* |
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| 121 | * one DUART channel (UART1) supported |
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| 122 | */ |
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| 123 | #define GEN83xx_DUART_AVAIL_MASK 0x01 |
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| 124 | |
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| 125 | /* we need the low level initialization in start.S*/ |
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| 126 | #define NEED_LOW_LEVEL_INIT |
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| 127 | /* |
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| 128 | * clocking infos |
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| 129 | */ |
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| 130 | #define BSP_CLKIN_FRQ 25000000L |
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| 131 | #define RCFG_SYSPLL_MF 5 |
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| 132 | #define RCFG_COREPLL_MF 5 |
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| 133 | /* |
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| 134 | * Reset configuration words |
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| 135 | */ |
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| 136 | #define RESET_CONF_WRD_L \ |
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| 137 | (RCWLR_LBIUCM_1_1 \ |
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| 138 | | RCWLR_DDRCM_2_1 \ |
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| 139 | | RCWLR_SPMF(RCFG_SYSPLL_MF) \ |
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| 140 | | RCWLR_COREPLL(RCFG_COREPLL_MF) \ |
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| 141 | | RCWLR_CEVCOD_1_2 \ |
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| 142 | | RCWLR_CEPMF(8) \ |
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| 143 | ) |
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| 144 | |
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| 145 | #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ |
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| 146 | RCWHR_PCI_32 | \ |
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| 147 | RCWHR_PCI1ARB_DIS | \ |
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| 148 | RCWHR_CORE_EN | \ |
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| 149 | RCWHR_BMS_LOW | \ |
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| 150 | RCWHR_BOOTSEQ_NONE | \ |
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| 151 | RCWHR_SW_DIS | \ |
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[907b07d9] | 152 | MPC83XX_RCWHR_BOOT_DEVICE | \ |
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[d9af2ed4] | 153 | RCWHR_ENDIAN_BIG) |
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| 154 | |
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[574fb67] | 155 | #elif defined( HAS_UBOOT) |
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| 156 | |
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| 157 | /* TODO */ |
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| 158 | |
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[42bf1b9] | 159 | #else |
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[574fb67] | 160 | |
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[42bf1b9] | 161 | #error "board type not defined" |
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[574fb67] | 162 | |
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[42bf1b9] | 163 | #endif |
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| 164 | |
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[7a752161] | 165 | #if defined(MPC83XX_BOARD_MPC8349EAMDS) |
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[42bf1b9] | 166 | /************************** |
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[7a752161] | 167 | * for Freescale MPC83XX_BOARD_MPC8349EAMDS |
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[42bf1b9] | 168 | */ |
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| 169 | |
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| 170 | /* |
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| 171 | * working values for various registers, used in start/start.S |
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| 172 | */ |
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[574fb67] | 173 | |
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[42bf1b9] | 174 | /* |
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| 175 | * Local Access Windows |
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[ac7af4a] | 176 | * FIXME: decode bit settings |
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[42bf1b9] | 177 | */ |
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| 178 | #define LBLAWBAR0_VAL 0xFE000000 |
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| 179 | #define LBLAWAR0_VAL 0x80000016 |
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| 180 | #define LBLAWBAR1_VAL 0xF8000000 |
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| 181 | #define LBLAWAR1_VAL 0x8000000E |
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| 182 | #define LBLAWBAR2_VAL 0xF0000000 |
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| 183 | #define LBLAWAR2_VAL 0x80000019 |
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| 184 | #define DDRLAWBAR0_VAL 0x00000000 |
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| 185 | #define DDRLAWAR0_VAL 0x8000001B |
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| 186 | /* |
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| 187 | * Local Bus (Memory) Controller |
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[ac7af4a] | 188 | * FIXME: decode bit settings |
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[42bf1b9] | 189 | */ |
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| 190 | #define BR0_VAL 0xFE001001 |
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| 191 | #define OR0_VAL 0xFF806FF7 |
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| 192 | #define BR1_VAL 0xF8000801 |
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| 193 | #define OR1_VAL 0xFFFFE8F0 |
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| 194 | #define BR2_VAL 0xF0001861 |
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| 195 | #define OR2_VAL 0xFC006901 |
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| 196 | /* |
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| 197 | * SDRAM registers |
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[ac7af4a] | 198 | * FIXME: decode bit settings |
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[42bf1b9] | 199 | */ |
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| 200 | #define MRPTR_VAL 0x20000000 |
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| 201 | #define LSRT_VAL 0x32000000 |
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| 202 | #define LSDMR_VAL 0x4062D733 |
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| 203 | #define LCRR_VAL 0x80000004 |
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| 204 | |
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| 205 | /* |
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| 206 | * DDR-SDRAM registers |
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[ac7af4a] | 207 | * FIXME: decode bit settings |
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[42bf1b9] | 208 | */ |
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| 209 | #define CS2_BNDS_VAL 0x00000007 |
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| 210 | #define CS3_BNDS_VAL 0x0008000F |
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| 211 | #define CS2_CONFIG_VAL 0x80000101 |
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| 212 | #define CS3_CONFIG_VAL 0x80000101 |
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| 213 | #define TIMING_CFG_1_VAL 0x36333321 |
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| 214 | #define TIMING_CFG_2_VAL 0x00000800 |
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| 215 | #define DDR_SDRAM_CFG_VAL 0xC2000000 |
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| 216 | #define DDR_SDRAM_MODE_VAL 0x00000022 |
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| 217 | #define DDR_SDRAM_INTTVL_VAL 0x045B0100 |
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| 218 | #define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 |
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| 219 | |
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[7a752161] | 220 | #elif defined(MPC83XX_BOARD_HSC_CM01) |
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[42bf1b9] | 221 | /************************** |
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| 222 | * for JPK HSC_CM01 |
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| 223 | */ |
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| 224 | |
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[4b23c94] | 225 | /* fpga BCSR register */ |
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| 226 | #define FPGA_START 0xF8000000 |
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| 227 | #define FPGA_SIZE 0x8000 |
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| 228 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 229 | |
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[42bf1b9] | 230 | /* |
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| 231 | * working values for various registers, used in start/start.S |
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| 232 | */ |
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[574fb67] | 233 | |
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[4b23c94] | 234 | /* fpga config 16 MB size */ |
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| 235 | #define FPGA_CONFIG_START 0xF8000000 |
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| 236 | #define FPGA_CONFIG_SIZE 0x01000000 |
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| 237 | /* fpga register 8 MB size */ |
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| 238 | #define FPGA_REGISTER_START 0xF9000000 |
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| 239 | #define FPGA_REGISTER_SIZE 0x00800000 |
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| 240 | /* fpga fifo 8 MB size */ |
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| 241 | #define FPGA_FIFO_START 0xF9800000 |
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| 242 | #define FPGA_FIFO_SIZE 0x00800000 |
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| 243 | |
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| 244 | #define FPGA_START (FPGA_CONFIG_START) |
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| 245 | // fpga window size 32 MByte |
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| 246 | #define FPGA_SIZE (0x02000000) |
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| 247 | #define FPGA_END (FPGA_START+FPGA_SIZE-1) |
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| 248 | |
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[42bf1b9] | 249 | /* |
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| 250 | * Local Access Windows |
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[ac7af4a] | 251 | * FIXME: decode bit settings |
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[42bf1b9] | 252 | */ |
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| 253 | |
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[574fb67] | 254 | #define LBLAWBAR0_VAL bsp_rom_start |
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[42bf1b9] | 255 | #define LBLAWAR0_VAL 0x80000018 |
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[4b23c94] | 256 | #define LBLAWBAR1_VAL (FPGA_CONFIG_START) |
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[ce7d6e62] | 257 | #define LBLAWAR1_VAL 0x80000018 |
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[574fb67] | 258 | #define DDRLAWBAR0_VAL bsp_ram_start |
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[42bf1b9] | 259 | #define DDRLAWAR0_VAL 0x8000001B |
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| 260 | /* |
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| 261 | * Local Bus (Memory) Controller |
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[ac7af4a] | 262 | * FIXME: decode bit settings |
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[42bf1b9] | 263 | */ |
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[ce7d6e62] | 264 | #define BR0_VAL (0xFE000000 | 0x01001) |
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[42bf1b9] | 265 | #define OR0_VAL 0xFE000E54 |
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[4b23c94] | 266 | // fpga config access range (UPM_A) (32 kByte) |
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| 267 | #define BR2_VAL (FPGA_CONFIG_START | 0x01881) |
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[ce7d6e62] | 268 | #define OR2_VAL 0xFFFF9100 |
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[4b23c94] | 269 | |
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| 270 | // fpga register access range (UPM_B) (8 MByte) |
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| 271 | #define BR3_VAL (FPGA_REGISTER_START | 0x018A1) |
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[ce7d6e62] | 272 | #define OR3_VAL 0xFF801100 |
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[4b23c94] | 273 | |
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[ce7d6e62] | 274 | // fpga fifo access range (UPM_C) (8 MByte) |
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| 275 | #define BR4_VAL (FPGA_FIFO_START | 0x018C1) |
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| 276 | #define OR4_VAL 0xFF801100 |
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[4b23c94] | 277 | |
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[42bf1b9] | 278 | /* |
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[4b23c94] | 279 | * SDRAM registers |
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[42bf1b9] | 280 | */ |
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[4b23c94] | 281 | #define MRPTR_VAL 0x20000000 |
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| 282 | #define LSRT_VAL 0x32000000 |
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| 283 | #define LSDMR_VAL 0x4062D733 |
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| 284 | #define LCRR_VAL 0x80010004 |
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[42bf1b9] | 285 | |
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| 286 | /* |
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| 287 | * DDR-SDRAM registers |
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[ac7af4a] | 288 | * FIXME: decode bit settings |
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[42bf1b9] | 289 | */ |
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| 290 | #define DDRCDR_VAL 0x00000001 |
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| 291 | #define CS0_BNDS_VAL 0x0000000F |
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| 292 | #define CS0_CONFIG_VAL 0x80810102 |
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| 293 | #define TIMING_CFG_0_VAL 0x00420802 |
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| 294 | #define TIMING_CFG_1_VAL 0x3735A322 |
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| 295 | #define TIMING_CFG_2_VAL 0x2F9044C7 |
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| 296 | #define DDR_SDRAM_CFG_2_VAL 0x00401000 |
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| 297 | #define DDR_SDRAM_MODE_VAL 0x44521632 |
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| 298 | #define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 |
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[d11ea4eb] | 299 | #define DDR_SDRAM_CFG_VAL 0x63000008 |
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[42bf1b9] | 300 | |
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| 301 | #define DDR_ERR_DISABLE_VAL 0x0000008D |
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| 302 | #define DDR_ERR_DISABLE_VAL2 0x00000089 |
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| 303 | #define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE |
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| 304 | #define DDR_SDRAM_INIT_ADDR_VAL 0 |
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| 305 | #define DDR_SDRAM_INTERVAL_VAL 0x05080000 |
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[574fb67] | 306 | |
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[d9af2ed4] | 307 | #elif defined(MPC83XX_BOARD_BR_UID) |
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| 308 | /************************** |
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| 309 | * for BR UID |
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| 310 | */ |
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| 311 | |
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| 312 | /* |
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| 313 | * working values for various registers, used in start/start.S |
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| 314 | */ |
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| 315 | |
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| 316 | /* |
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| 317 | * Local Access Windows |
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| 318 | * FIXME: decode bit settings |
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| 319 | */ |
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| 320 | |
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| 321 | #define LBLAWBAR0_VAL bsp_rom_start |
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| 322 | #define LBLAWAR0_VAL 0x80000018 |
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| 323 | #define DDRLAWBAR0_VAL bsp_ram_start |
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| 324 | #define DDRLAWAR0_VAL 0x8000001B |
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| 325 | |
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| 326 | |
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| 327 | /* |
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| 328 | * clocking for local bus: |
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| 329 | * ALE active for 1 clock |
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| 330 | * local bus clock = 1/2 csb clock |
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| 331 | */ |
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| 332 | #define LCRR_VAL 0x80010002 |
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| 333 | |
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| 334 | /* |
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| 335 | * DDR-SDRAM registers |
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| 336 | * FIXME: decode bit settings |
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| 337 | */ |
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| 338 | #define DDRCDR_VAL 0x00000001 |
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| 339 | #define CS0_BNDS_VAL 0x0000000F |
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| 340 | #define CS0_CONFIG_VAL 0x80014202 |
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| 341 | #define TIMING_CFG_0_VAL 0x00220802 |
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| 342 | #define TIMING_CFG_1_VAL 0x26259222 |
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| 343 | #define TIMING_CFG_2_VAL 0x111048C7 |
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| 344 | #define DDR_SDRAM_CFG_2_VAL 0x00401000 |
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| 345 | #define DDR_SDRAM_MODE_VAL 0x200F1632 |
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| 346 | #define DDR_SDRAM_MODE_2_VAL 0x40006000 |
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| 347 | #define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 |
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| 348 | #define DDR_SDRAM_CFG_VAL 0x43100008 |
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| 349 | |
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| 350 | #define DDR_ERR_DISABLE_VAL 0x0000008D |
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| 351 | #define DDR_ERR_DISABLE_VAL2 0x00000089 |
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| 352 | #define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE |
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| 353 | #define DDR_SDRAM_INIT_ADDR_VAL 0 |
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| 354 | #define DDR_SDRAM_INTERVAL_VAL 0x01E8222E |
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| 355 | |
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[574fb67] | 356 | #elif defined( HAS_UBOOT) |
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| 357 | |
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| 358 | /* TODO */ |
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| 359 | |
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[42bf1b9] | 360 | #else |
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[574fb67] | 361 | |
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[42bf1b9] | 362 | #error "board type not defined" |
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| 363 | |
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[574fb67] | 364 | #endif |
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[42bf1b9] | 365 | |
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| 366 | /************************** |
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| 367 | * derived values for all boards |
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| 368 | */ |
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| 369 | /* value of input clock divider (derived from pll mode reg) */ |
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[566c05c] | 370 | #if MPC83XX_CHIP_TYPE != 8309 |
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| 371 | #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) |
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| 372 | #else |
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| 373 | /* On the MPC8309 this bit is reserved */ |
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| 374 | #define BSP_SYSPLL_CKID 1 |
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| 375 | #endif |
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[42bf1b9] | 376 | /* value of system pll (derived from pll mode reg) */ |
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[ac7af4a] | 377 | #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) |
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[42bf1b9] | 378 | /* value of system pll (derived from pll mode reg) */ |
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[ac7af4a] | 379 | #define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) |
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[42bf1b9] | 380 | |
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| 381 | #endif /* __GEN83xx_HWREG_VALS_h */ |
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