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start.S @ cc61d5c

Last change on this file since cc61d5c was fbcd7c8f, checked in by Sebastian Huber <sebastian.huber@…>, on 04/20/18 at 08:19:28

bsps: Move start files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

Property mode set to 100644

File size: 25.5 KB

Line
1	/===============================================================\
2	\| Project: RTEMS generic MPC5200 BSP \|
3	+-----------------------------------------------------------------+
4	\| Partially based on the code references which are named below. \|
5	\| Adaptions, modifications, enhancements and any recent parts of \|
6	\| the code are: \|
7	\| Copyright (c) 2005 \|
8	\| Embedded Brains GmbH \|
9	\| Obere Lagerstr. 30 \|
10	\| D-82178 Puchheim \|
11	\| Germany \|
12	\| rtems@embedded-brains.de \|
13	+-----------------------------------------------------------------+
14	\| The license and distribution terms for this file may be \|
15	\| found in the file LICENSE in this distribution or at \|
16	\| \|
17	\| http://www.rtems.org/license/LICENSE. \|
18	\| \|
19	+-----------------------------------------------------------------+
20	\| this file contains the startup assembly code \|
21	\===============================================================/
22	/***********************************************************************/
23	/* */
24	/* Module: start.S */
25	/* Date: 07/17/2003 */
26	/* Purpose: RTEMS MPC5x00 CPU assembly startup */
27	/* */
28	/---------------------------------------------------------------------/
29	/* */
30	/* Description: This file contains the assembler portion of MPC5x00 */
31	/* startup code */
32	/* */
33	/---------------------------------------------------------------------/
34	/* */
35	/* Code */
36	/* References: startup code for Motorola PQII ADS board */
37	/* Module: start.S */
38	/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
39	/* Version 1.2 */
40	/* Date: 04/18/2002 */
41	/* */
42	/* Author(s) / Copyright(s): */
43	/* */
44	/* Modified for the Motorola PQII ADS board by */
45	/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
46	/* Surrey Satellite Technology Limited */
47	/* */
48	/* I have a proprietary bootloader programmed into the flash */
49	/* on the board which initialises the SDRAM prior to calling */
50	/* this function. */
51	/* */
52	/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
53	/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
54	/* written by: */
55	/* */
56	/* Author: Andrew Bray <andy@i-cubed.co.uk> */
57	/* */
58	/* COPYRIGHT (c) 1995 by i-cubed ltd. */
59	/* */
60	/* To anyone who acknowledges that this file is provided "AS IS" */
61	/* without any express or implied warranty: */
62	/* permission to use, copy, modify, and distribute this file */
63	/* for any purpose is hereby granted without fee, provided that */
64	/* the above copyright notice and this notice appears in all */
65	/* copies, and that the name of i-cubed limited not be used in */
66	/* advertising or publicity pertaining to distribution of the */
67	/* software without specific, written prior permission. */
68	/* i-cubed limited makes no representations about the suitability */
69	/* of this software for any purpose. */
70	/* */
71	/---------------------------------------------------------------------/
72	/* */
73	/* Partially based on the code references which are named above. */
74	/* Adaptions, modifications, enhancements and any recent parts of */
75	/* the code are under the right of */
76	/* */
77	/* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */
78	/* Copyright(C) 2003 */
79	/* */
80	/---------------------------------------------------------------------/
81	/* */
82	/* IPR Engineering makes no representation or warranties with */
83	/* respect to the performance of this computer program, and */
84	/* specifically disclaims any responsibility for any damages, */
85	/* special or consequential, connected with the use of this program. */
86	/* */
87	/---------------------------------------------------------------------/
88	/* */
89	/* Version history: 1.0 */
90	/* */
91	/***********************************************************************/
92
93	#include <rtems/powerpc/cache.h>
94
95	#include <bsp.h>
96	#include <bsp/mpc5200.h>
97
98	/* Some register offsets of MPC5x00 memory map registers */
99	.set CS0STR, 0x04
100	.set CS0STP, 0x08
101	.set CS1STR, 0x0C
102	.set CS1STP, 0x10
103	.set SDRAMCS0, 0x34
104	.set SDRAMCS1, 0x38
105	.set BOOTSTR, 0x4C
106	.set BOOTSTP, 0x50
107	.set ADREN, 0x54
108	.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
109	.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
110	.set CFG, 0x20C
111	.set CSBOOTROM, 0x300
112	.set CSCONTROL, 0x318
113	.set CS1CONF, 0x304
114
115
116	/* Register offsets of MPC5x00 SDRAM memory controller registers */
117	.set MOD, 0x100
118	.set CTRL, 0x104
119	.set CFG1, 0x108
120	.set CFG2, 0x10C
121	.set ADRSEL, 0x110
122	.set SDELAY, 0x190
123
124	/* Register offsets of MPC5x00 GPIO registers needed */
125	.set GPIOPCR, 0xb00
126	.set GPIOWE, 0xc00
127	.set GPIOWOD, 0xc04
128	.set GPIOWDD, 0xc08
129	.set GPIOWDO, 0xc0c
130
131	.set GPIOSEN, 0xb04
132	.set GPIOSDD, 0xb0c
133	.set GPIOSDO, 0xb10
134
135	/* Register offsets of MPC5x00 Arbiter registers */
136	.set ARBCFG, 0x1f40
137	.set ARBADRTO, 0x1f58
138	.set ARBDATTO, 0x1f5c
139	.set ARBMPREN, 0x1f64
140	.set ARBMPRIO, 0x1f68
141	.set ARBSNOOP, 0x1f70
142
143	/* Some bit encodings for MGT5100 registers */
144	.set ADREN_BOOT_EN, (1 << (31 - 6))
145	.set ADREN_CS0_EN, (1 << (31 - 15))
146	.set ADREN_CS1_EN, (1 << (31 - 14))
147	.set ADREN_WSE, (1 << (31 - 31))
148
149	.set CTRL_PRECHARGE_ALL, (1 << (31 - 30))
150	.set CTRL_REFRESH, (1 << (31 - 29))
151	.set CTRL_MODE_EN, (1 << (31 - 0))
152
153	.set CSCONF_CE, (1<<12)
154
155	/* Some fixed values for MPC5x00 registers */
156	.set CSCONTROL_VAL, 0x91000000
157
158	/*
159	* The DDR_MODE bit is a read-only status and should be written as 0.
160	*
161	* XLB_CLK = FVCO / 4
162	* IPB_CLK = XLB_CLK / 2
163	* PCI_CLK = IPB_CLK
164	*/
165	.set CFG_VAL, 0x00000100
166
167	.extern boot_card
168
169	.section ".vectors", "ax"
170	bl start
171	.rep 63
172	.long 0x04000400
173	.endr
174	__vec2: b __vec2
175	.rep 63
176	.long 0x04000400
177	.endr
178	__vec3: b __vec3
179	.rep 63
180	.long 0x04000400
181	.endr
182	__vec4: b __vec4
183	.rep 63
184	.long 0x04000400
185	.endr
186	__vec5: b __vec5
187	.rep 63
188	.long 0x04000400
189	.endr
190	__vec6: b __vec6
191	.rep 63
192	.long 0x04000400
193	.endr
194	__vec7: b __vec7
195	.rep 63
196	.long 0x04000400
197	.endr
198	__vec8: b __vec8
199	.rep 63
200	.long 0x04000400
201	.endr
202	__vec9: b __vec9
203	.rep 63
204	.long 0x04000400
205	.endr
206	__veca: b __veca
207	.rep 63
208	.long 0x04000400
209	.endr
210	__vecb: b __vecb
211	.rep 63
212	.long 0x04000400
213	.endr
214	__vecc: b __vecc
215	.rep 63
216	.long 0x04000400
217	.endr
218	__vecd: b __vecd
219	.rep 63
220	.long 0x04000400
221	.endr
222	__vece: b __vece
223	.rep 63
224	.long 0x04000400
225	.endr
226	__vecf: b __vecf
227	.rep 63+1024
228	.long 0x04000400
229	.endr
230
231	.section ".entry"
232	PUBLIC_VAR (start)
233	start:
234	/* 1st: initialization work (common for RAM/ROM startup) */
235	mfmsr r30
236	SETBITS r30, r29, MSR_ME\|MSR_RI
237	CLRBITS r30, r29, MSR_EE
238	mtmsr r30 /* Set RI/ME, Clr EE in MSR */
239
240	#ifdef HAS_UBOOT
241	mr r14, r3
242	#endif /* HAS_UBOOT */
243
244	#if defined(NEED_LOW_LEVEL_INIT)
245	/* initialize the MBAR (common RAM/ROM startup) */
246	LWI r31, MBAR_RESET
247	LWI r29, MBAR
248	rlwinm r30, r29,16,16,31
249	stw r30, 0(r31) /* Set the MBAR */
250	#endif
251
252	LWI r31, MBAR /* set r31 to current MBAR */
253	/* init GPIOPCR */
254	lwz r29,GPIOPCR(r31)
255	LWI r30, BSP_GPIOPCR_INITMASK
256	not r30,r30
257	and r29,r29,r30
258	LWI r30, BSP_GPIOPCR_INITVAL
259	or r29,r29,r30
260	stw r29, GPIOPCR(r31)
261
262	/* further initialization work (common RAM/ROM startup) */
263	bl TLB_init /* Initialize TLBs */
264
265
266	bl FID_DCache /* Flush, inhibit and disable data cache */
267
268
269	bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
270
271
272	bl FPU_init /* Initialize FPU */
273
274
275	#if defined(NEED_LOW_LEVEL_INIT)
276	bl SPRG_init /* Initialize special purpose registers */
277	#endif
278
279	#if defined(NEED_LOW_LEVEL_INIT)
280	/* detect RAM/ROM startup (common for RAM/ROM startup) */
281	LWI r20, bsp_rom_start /* set the relocation offset */
282
283
284	LWI r30, CFG_VAL /* get CFG register content */
285	lwz r30, CFG(r31) /* set CFG register */
286
287
288
289	lwz r30, ADREN(r31) /* get content of ADREN */
290
291
292
293	TSTBITS r30, r29, ADREN_BOOT_EN
294	bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
295
296	/* do some board dependent configuration (unique for ROM startup) */
297	LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
298	stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
299
300
301	#if defined(MPC5200_BOARD_BRS5L)
302	#define CSBOOTROM_VAL 0x0101D910
303	#elif defined(MPC5200_BOARD_BRS6L)
304	#define CSBOOTROM_VAL 0x0202D910
305	#endif
306
307	#ifdef CSBOOTROM_VAL
308	LWI r30, CSBOOTROM_VAL
309	stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
310	#endif
311
312	/* FIXME: map BOOT ROM into final location with CS0 registers */
313	LWI r30, bsp_rom_start
314	rlwinm r30, r30,17,15,31
315	stw r30, CS0STR(r31) /* Set CS0STR */
316
317	LWI r30, bsp_rom_end - 1
318
319	rlwinm r30, r30,17,15,31
320	stw r30, CS0STP(r31) /* Set CS0STP */
321
322	lwz r30, ADREN(r31) /* get content of ADREN */
323	SETBITS r30, r29, ADREN_CS0_EN
324	stw r30, ADREN(r31) /* enable CS0 mapping */
325	isync
326	/* jump to same code in final BOOT ROM location */
327	LWI r30, reloc_in_CS0
328	LWI r29, bsp_ram_start
329	sub r30,r30,r29
330	LWI r29, bsp_rom_start
331	add r30,r30,r29
332	mtctr r30
333	bctr
334
335	reloc_in_CS0:
336	/* disable CSBOOT (or map it to CS0 range) */
337	lwz r30, ADREN(r31) /* get content of ADREN */
338	CLRBITS r30, r29, ADREN_BOOT_EN
339	stw r30, ADREN(r31) /* disable BOOT mapping */
340
341	/* init SDRAM */
342	LWI r30, bsp_ram_start
343	ori r30, r30, 0x1a /* size code: bank is 128MByte */
344	stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
345
346	LWI r30, bsp_ram_size
347	srawi r30, r30, 1
348	ori r30, r30, 0x1a /* size code: bank is 128MByte */
349	stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
350
351	bl SDRAM_init /* Initialize SDRAM controller */
352
353	bl XLB_init
354	/* copy .text section from ROM to RAM location (unique for ROM startup) */
355	LA r30, bsp_section_text_start /* get start address of text section in RAM */
356
357
358	add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
359
360
361	LA r29, bsp_section_text_start /* get start address of text section in RAM */
362
363
364	LA r28, bsp_section_text_size /* get size of RAM image */
365
366
367	bl copy_image /* copy text section from ROM to RAM location */
368
369
370	/* copy .data section from ROM to RAM location (unique for ROM startup) */
371	LA r30, bsp_section_data_start /* get start address of data section in RAM */
372
373
374	add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
375
376
377	LA r29, bsp_section_data_start /* get start address of data section in RAM */
378
379
380	LA r28, bsp_section_data_size /* get size of RAM image */
381
382
383	bl copy_image /* copy initialized data section from ROM to RAM location */
384
385
386	LA r29, remap_rom /* get compile time address of label */
387	mtlr r29
388
389	blrl /* now further execution RAM */
390
391	remap_rom:
392	/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
393	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
394
395
396
397	CLRBITS r30, r29, CSCONF_CE
398	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
399
400
401
402	lwz r30, ADREN(r31) /* get content of ADREN */
403
404
405
406	mr r29, r30 /* move content of r30 to r29 */
407
408
409	LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
410	andc r29,r29,r30
411
412
413	LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
414	or r29,r29,r30
415
416
417	stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
418
419
420
421	lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
422
423
424
425	SETBITS r30, r29, CSCONF_CE
426	stw r30, CSBOOTROM(r31) /* disable BOOT CS */
427
428
429
430	skip_ROM_start:
431	/* configure external DPRAM CS1 */
432	LWI r30, 0xFFFFFB10
433	stw r30, CS1CONF(r31)
434
435	/* map external DPRAM (CS1) */
436	LWI r30, bsp_dpram_start
437	srawi r30, r30, 16
438	stw r30, CS1STR(r31)
439
440	LWI r30, bsp_dpram_end
441	srawi r30, r30, 16
442	stw r30, CS1STP(r31)
443
444	lwz r30, ADREN(r31) /* get content of ADREN */
445
446	LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
447	or r30, r30,r29
448
449	stw r30, ADREN(r31) /* enable CS1 */
450
451	/* clear entire on chip SRAM (unique for ROM startup) */
452	lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
453	ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
454	LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
455
456	bl clr_mem /* Clear onchip SRAM */
457
458	#else /* defined(NEED_LOW_LEVEL_INIT) */
459	bl XLB_init
460	#endif /* defined(NEED_LOW_LEVEL_INIT) */
461	/* clear .bss section (unique for ROM startup) */
462	LWI r30, bsp_section_bss_start /* get start address of bss section */
463	LWI r29, bsp_section_bss_size /* get size of bss section */
464
465
466	bl clr_mem /* Clear the bss section */
467
468	#ifdef HAS_UBOOT
469	mr r3, r14
470	bl bsp_uboot_copy_board_info
471	#endif /* HAS_UBOOT */
472
473	/* set stack pointer (common for RAM/ROM startup) */
474	LA r1, bsp_section_text_start
475	addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
476	/* tag TOS with a NULL pointer (termination mark for stack dump) */
477	li r0, 0
478	stw r0, 0(r1)
479
480	bl __eabi /* Set up EABI and SYSV environment */
481
482	/* enable dynamic power management(common for RAM/ROM startup) */
483	bl PPC_HID0_rd /* Get the content of HID0 */
484
485	SETBITS r30, r29, HID0_DPM
486	bl PPC_HID0_wr /* Set DPM in HID0 */
487
488	/* clear arguments and do further init. in C (common for RAM/ROM startup) */
489
490	/* Clear cmdline */
491	xor r3, r3, r3
492
493	bl SYM (boot_card) /* Call the first C routine */
494
495	twiddle:
496	b twiddle /* We don't expect to return from boot_card but if we do */
497	/* wait here for watchdog to kick us into hard reset */
498
499	#if defined(NEED_LOW_LEVEL_INIT)
500	SDRAM_init:
501	mflr r12
502
503	#if defined(MPC5200_BOARD_BRS5L)
504	/* set GPIO_WKUP7 pin low for 66MHz buffering */
505	/* or high for 133MHz registered buffering */
506	LWI r30, 0x80000000
507
508	lwz r29, GPIOWE(r31)
509	or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
510	stw r29,GPIOWE(r31)
511
512	lwz r29, GPIOWOD(r31)
513	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
514	stw r29,GPIOWOD(r31)
515
516	lwz r29, GPIOWDO(r31)
517	andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
518	stw r29,GPIOWDO(r31)
519
520	lwz r29, GPIOWDD(r31)
521	or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
522	stw r29,GPIOWDD(r31)
523
524	/* activate MEM_CS1 output */
525	lwz r29, GPIOPCR(r31)
526	or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
527	stw r29,GPIOPCR(r31)
528
529	#endif
530
531	#define SDELAY_VAL 0x00000004
532
533	#if defined(MPC5200_BOARD_BRS6L)
534	#define CFG1_VAL 0x73722930
535	#else
536	/*
537	* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4
538	* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2
539	*/
540	#define CFG1_VAL 0xC4222600
541	#endif
542
543	#if defined(MPC5200_BOARD_BRS6L)
544	#define CFG2_VAL 0x47770000
545	#else
546	/* Refr.2No-Read delay=0x06, Write latency=0x0 */
547	/* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
548	/* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
549	#define CFG2_VAL 0xCCC70004
550	#endif
551
552	#if defined(MPC5200_BOARD_BRS5L)
553	/* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
554	/* Refresh counter=0xFFFF */
555	#define CTRL_VAL 0xD1470000
556	#elif defined(MPC5200_BOARD_BRS6L)
557	#define CTRL_VAL 0xF15F0F00
558	#else
559	/* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
560	/* Refresh counter=0xFFFF */
561	#define CTRL_VAL 0xD04F0000
562	#endif
563
564	#if defined(MPC5200_BOARD_BRS6L)
565	/* Enable DLL, normal drive strength */
566	#define EMODE_VAL 0x40010000
567	#endif
568
569	#if defined(MPC5200_BOARD_BRS6L)
570	/* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation/reset DLL */
571	#define MODE_VAL 0x058D0000
572	#else
573	/* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
574	#define MODE_VAL 0x008D0000
575	#endif
576
577	#if defined(MPC5200_BOARD_BRS6L)
578	/* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation */
579	#define SECOND_MODE_VAL (MODE_VAL & ~0x04000000)
580	#endif
581
582	/* SDRAM initialization according to application note AN3221 */
583
584	/* SDRAM controller setup */
585
586	LWI r3, SDELAY_VAL
587	stw r3, SDELAY(r31)
588
589	LWI r3, CFG1_VAL
590	stw r3, CFG1(r31)
591
592	LWI r3, CFG2_VAL
593	stw r3, CFG2(r31)
594
595	LWI r11, CTRL_VAL
596	stw r11, CTRL(r31)
597	lwz r3, CTRL(r31)
598
599	/* Perform a PRECHARGE ALL command */
600	ori r3, r11, CTRL_PRECHARGE_ALL
601	stw r3, CTRL(r31)
602	lwz r3, CTRL(r31)
603
604	/* Wait at least tRP time */
605	li r3, 15
606	bl ndelay
607
608	#if defined(EMODE_VAL)
609	/* Write EMODE register */
610	LWI r3, EMODE_VAL
611	stw r3, MOD(r31)
612
613	/* Wait at least tMRD time */
614	li r3, 10
615	bl ndelay
616	#endif
617
618	/* Write MODE register */
619	LWI r3, MODE_VAL
620	stw r3, MOD(r31)
621
622	/* Wait at least tMRD time */
623	li r3, 10
624	bl ndelay
625
626	/* Perform a PRECHARGE ALL command */
627	ori r3, r11, CTRL_PRECHARGE_ALL
628	stw r3, CTRL(r31)
629	lwz r3, CTRL(r31)
630
631	/* Wait at least tRP time */
632	li r3, 15
633	bl ndelay
634
635	/* Perform an AUTO REFRESH */
636	ori r3, r11, CTRL_REFRESH
637	stw r3, CTRL(r31)
638	lwz r3, CTRL(r31)
639
640	/* Wait at least tRFC time */
641	li r3, 70
642	bl ndelay
643
644	/* Perform an AUTO REFRESH */
645	ori r3, r11, CTRL_REFRESH
646	stw r3, CTRL(r31)
647	lwz r3, CTRL(r31)
648
649	/* Wait at least tRFC time */
650	li r3, 70
651	bl ndelay
652
653	#if defined(SECOND_MODE_VAL)
654	/* Write MODE register */
655	LWI r3, SECOND_MODE_VAL
656	stw r3, MOD(r31)
657	#endif
658
659	/* Disable MODE register access */
660	lis r4, CTRL_MODE_EN@h
661	andc r3, r11, r4
662	stw r3, CTRL(r31)
663	lwz r3, CTRL(r31)
664
665	mtlr r12
666	blr
667
668	copy_image:
669	mr r27, r28
670	srwi r28, r28, 2
671	mtctr r28
672
673
674	slwi r28, r28, 2
675	sub r27, r27, r28 /* maybe some residual bytes */
676
677
678	copy_image_word:
679	lswi r28, r30, 0x04
680
681	stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
682
683
684	addi r30, r30, 0x04 /* increment source pointer */
685	addi r29, r29, 0x04 /* increment destination pointer */
686
687	bdnz copy_image_word /* decrement ctr and branch if not 0 */
688
689	cmpwi r27, 0x00 /* copy image finished ? */
690	beq copy_image_end;
691	mtctr r27 /* reload counter for residual bytes */
692	copy_image_byte:
693	lswi r28, r30, 0x01
694
695	stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
696
697
698	addi r30, r30, 0x01 /* increment source pointer */
699	addi r29, r29, 0x01 /* increment destination pointer */
700
701	bdnz copy_image_byte /* decrement ctr and branch if not 0 */
702
703	copy_image_end:
704	blr
705	#endif /* defined(NEED_LOW_LEVEL_INIT) */
706
707	FID_DCache:
708	mflr r26
709
710	bl PPC_HID0_rd
711	TSTBITS r30, r29, HID0_DCE
712	bne FID_DCache_exit /* If data cache is switched of, skip further actions */
713
714	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
715	LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
716
717	FID_DCache_loop_1:
718	lwz r27, 0(r28) /* Load data at address */
719
720	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
721	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
722	cmpwi r29, 0x0
723	bne FID_DCache_loop_1 /* Loop until cache size is reached */
724
725	li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
726	LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
727	xor r27, r27, r27
728	FID_DCache_loop_2:
729
730	dcbf r27, r28 /* Flush and invalidate cache */
731
732	addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
733	subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
734	cmpwi r29, 0x0
735	bne FID_DCache_loop_2 /* Loop around until cache size is reached */
736
737	bl PPC_HID0_rd /* Read HID0 */
738	CLRBITS r30, r29, HID0_DCE
739	bl PPC_HID0_wr /* Clear DCE */
740
741	FID_DCache_exit:
742	mtlr r26
743	blr
744
745	IDUL_ICache:
746	mflr r26
747
748	bl PPC_HID0_rd
749	TSTBITS r30, r29, HID0_ICE
750	bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
751
752	CLRBITS r30, r29, HID0_ICE
753	bl PPC_HID0_wr /* Disable ICE bit */
754
755	SETBITS r30, r29, HID0_ICFI
756	bl PPC_HID0_wr /* Invalidate instruction cache */
757
758	CLRBITS r30, r29, HID0_ICFI
759	bl PPC_HID0_wr /* Disable cache invalidate */
760
761	CLRBITS r30, r29, HID0_ILOCK
762	bl PPC_HID0_wr /* Disable instruction cache lock */
763
764	IDUL_ICache_exit:
765	mtlr r26
766	blr
767
768
769	TLB_init: /* Initialize translation lookaside buffers (TLBs) */
770	xor r30, r30, r30
771	xor r29, r29, r29
772
773	TLB_init_loop:
774	tlbie r29
775	tlbsync
776	addi r29, r29, 0x1000
777	addi r30, r30, 0x01
778	cmpli 0, 0, r30, 0x0080
779	bne TLB_init_loop
780	blr
781
782	FPU_init:
783	mfmsr r30 /* get content of MSR */
784
785
786	SETBITS r30, r29, MSR_FP
787	mtmsr r30 /* enable FPU and FPU exceptions */
788	sync
789
790	lfd f0, 0(r29)
791	fmr f1, f0
792	fmr f2, f0
793	fmr f3, f0
794	fmr f4, f0
795	fmr f5, f0
796	fmr f6, f0
797	fmr f7, f0
798	fmr f8, f0
799	fmr f9, f0
800	fmr f10, f0
801	fmr f11, f0
802	fmr f12, f0
803	fmr f13, f0
804	fmr f14, f0
805	fmr f15, f0
806	fmr f16, f0
807	fmr f17, f0
808	fmr f18, f0
809	fmr f19, f0
810	fmr f20, f0
811	fmr f21, f0
812	fmr f22, f0
813	fmr f23, f0
814	fmr f24, f0
815	fmr f25, f0
816	fmr f26, f0
817	fmr f27, f0
818	fmr f28, f0
819	fmr f29, f0
820	fmr f30, f0
821	fmr f31, f0
822
823
824	mtfsfi 0, 0 /* initialize bit positons in FPSCR */
825	mtfsfi 1, 0
826	mtfsfi 2, 0
827	mtfsfi 3, 0
828	mtfsfi 4, 0
829	mtfsfi 5, 0
830	mtfsfi 6, 0
831	mtfsfi 7, 0
832
833	blr
834
835	SPRG_init: /* initialize registers */
836	xor r30, r30, r30
837
838	mtspr PPC_XER, r30
839	mtspr PPC_CTR, r30
840	mtspr DSISR, r30
841	mtspr PPC_DAR, r30
842	mtspr PPC_DEC, r30
843	mtspr SDR1, r30
844	mtspr SRR0, r30
845	mtspr SRR1, r30
846	mtspr CSSR0, r30
847	mtspr CSSR1, r30
848	mtspr SPRG0, r30
849	mtspr SPRG1, r30
850	mtspr SPRG2, r30
851	mtspr SPRG3, r30
852	mtspr SPRG4, r30
853	mtspr SPRG5, r30
854	mtspr SPRG6, r30
855	mtspr SPRG7, r30
856	mtspr PPC_EAR, r30
857	mtspr TBWU, r30
858	mtspr TBWL, r30
859	mtspr IBAT0U, r30
860	mtspr IBAT0L, r30
861	mtspr IBAT1U, r30
862	mtspr IBAT1L, r30
863	mtspr IBAT2U, r30
864	mtspr IBAT2L, r30
865	mtspr IBAT3U, r30
866	mtspr IBAT3L, r30
867	mtspr IBAT4U, r30
868	mtspr IBAT4L, r30
869	mtspr IBAT5U, r30
870	mtspr IBAT5L, r30
871	mtspr IBAT6U, r30
872	mtspr IBAT6L, r30
873	mtspr IBAT7U, r30
874	mtspr IBAT7L, r30
875	mtspr DBAT0U, r30
876	mtspr DBAT0L, r30
877	mtspr DBAT1U, r30
878	mtspr DBAT1L, r30
879	mtspr DBAT2U, r30
880	mtspr DBAT2L, r30
881	mtspr DBAT3U, r30
882	mtspr DBAT3L, r30
883	mtspr DBAT4U, r30
884	mtspr DBAT4L, r30
885	mtspr DBAT5U, r30
886	mtspr DBAT5L, r30
887	mtspr DBAT6U, r30
888	mtspr DBAT6L, r30
889	mtspr DBAT7U, r30
890	mtspr DBAT7L, r30
891	mtspr DMISS, r30
892	mtspr DCMP, r30
893	mtspr HASH1, r30
894	mtspr HASH2, r30
895	mtspr IMISS, r30
896	mtspr ICMP, r30
897	mtspr PPC_RPA, r30
898	mtsr PPC_SR0, r30
899	mtsr PPC_SR1, r30
900	mtsr PPC_SR2, r30
901	mtsr PPC_SR3, r30
902	mtsr PPC_SR4, r30
903	mtsr PPC_SR5, r30
904	mtsr PPC_SR6, r30
905	mtsr PPC_SR7, r30
906	mtsr PPC_SR8, r30
907	mtsr PPC_SR9, r30
908	mtsr PPC_SR10, r30
909	mtsr PPC_SR12, r30
910	mtsr PPC_SR13, r30
911	mtsr PPC_SR14, r30
912	mtsr PPC_SR15, r30
913
914
915
916
917
918	blr
919
920	PPC_HID0_rd: /* get HID0 content to r30 */
921
922
923	mfspr r30, HID0
924
925	blr
926
927
928	PPC_HID0_wr: /* put r30 content to HID0 */
929
930
931	mtspr HID0, r30
932
933	blr
934
935	clr_mem:
936	mr r28, r29
937	srwi r29, r29, 2
938	mtctr r29 /* set ctr reg */
939
940
941	slwi r29, r29, 2
942	sub r28, r28, r29 /* maybe some residual bytes */
943	xor r29, r29, r29
944
945
946	clr_mem_word:
947	stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
948	addi r30, r30, 0x04 /* increment r30 */
949
950	bdnz clr_mem_word /* dec counter and loop */
951
952
953	cmpwi r28, 0x00 /* clear mem. finished ? */
954	beq clr_mem_end;
955	mtctr r28 /* reload counter for residual bytes */
956	clr_mem_byte:
957	stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
958	addi r30, r30, 0x01 /* update r30 */
959
960	bdnz clr_mem_byte /* dec counter and loop */
961
962	clr_mem_end:
963	blr /* return */
964
965	XLB_init:
966	/* init arbiter and stuff... */
967	LWI r30, 0x8000a06e
968	stw r30, ARBCFG(r31) /* Set ARBCFG */
969
970	LWI r30, 0x000000ff
971	stw r30, ARBMPREN(r31) /* Set ARBMPREN */
972
973	LWI r30, 0x00001234
974	stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
975
976	LWI r30, 0x0000001e
977	stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
978
979	LWI r30, 4096
980	stw r30, ARBADRTO(r31) /* Set ARBADRTO */
981	stw r30, ARBDATTO(r31) /* Set ARBDATTO */
982
983	blr
984
985	ndelay:
986	/*
987	* The maximum core frequency is 396MHz.
988	* We have (396MHz * 1024) / 10**9 == 405.
989	*/
990	mulli r3, r3, 405
991	srwi. r3, r3, 10
992
993	beqlr
994
995	mtctr r3
996
997	ndelay_loop:
998	bdnz ndelay_loop
999
1000	blr

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