1 | /*===============================================================*\ |
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2 | | Project: RTEMS generic MPC5200 BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2005 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.org/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the irq controller handler | |
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21 | \*===============================================================*/ |
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22 | /***********************************************************************/ |
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23 | /* */ |
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24 | /* Module: irq.c */ |
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25 | /* Date: 07/17/2003 */ |
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26 | /* Purpose: RTEMS MPC5x00 CPU main interrupt handler & routines */ |
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27 | /* */ |
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28 | /*---------------------------------------------------------------------*/ |
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29 | /* */ |
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30 | /* Description: This file contains the implementation of the */ |
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31 | /* functions described in irq.h */ |
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32 | /* */ |
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33 | /*---------------------------------------------------------------------*/ |
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34 | /* */ |
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35 | /* Code */ |
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36 | /* References: MPC8260ads main interrupt handler & routines */ |
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37 | /* Module: irc.c */ |
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38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ |
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39 | /* Version 1.2 */ |
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40 | /* Date: 04/18/2002 */ |
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41 | /* */ |
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42 | /* Author(s) / Copyright(s): */ |
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43 | /* */ |
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44 | /* Copyright (C) 1998, 1999 valette@crf.canon.fr */ |
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45 | /* */ |
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46 | /* Modified for mpc8260 Andy Dachs <a.dachs@sstl.co.uk> */ |
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47 | /* Surrey Satellite Technology Limited, 2000 */ |
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48 | /* Nested exception handlers not working yet. */ |
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49 | /* */ |
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50 | /* The license and distribution terms for this file may be */ |
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51 | /* found in the file LICENSE in this distribution or at */ |
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52 | /* http://www.rtems.org/license/LICENSE. */ |
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53 | /* */ |
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54 | /*---------------------------------------------------------------------*/ |
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55 | /* */ |
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56 | /* Partially based on the code references which are named above. */ |
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57 | /* Adaptions, modifications, enhancements and any recent parts of */ |
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58 | /* the code are under the right of */ |
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59 | /* */ |
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60 | /* IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen */ |
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61 | /* Copyright(C) 2003 */ |
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62 | /* */ |
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63 | /*---------------------------------------------------------------------*/ |
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64 | /* */ |
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65 | /* IPR Engineering makes no representation or warranties with */ |
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66 | /* respect to the performance of this computer program, and */ |
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67 | /* specifically disclaims any responsibility for any damages, */ |
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68 | /* special or consequential, connected with the use of this program. */ |
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69 | /* */ |
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70 | /*---------------------------------------------------------------------*/ |
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71 | /* */ |
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72 | /* Version history: 1.0 */ |
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73 | /* */ |
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74 | /***********************************************************************/ |
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75 | |
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76 | #include <inttypes.h> |
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77 | |
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78 | #include <rtems.h> |
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79 | |
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80 | #include <libcpu/powerpc-utility.h> |
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81 | #include <bsp/vectors.h> |
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82 | |
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83 | #include <bsp.h> |
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84 | #include <bsp/irq.h> |
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85 | #include <bsp/irq-generic.h> |
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86 | #include <bsp/mpc5200.h> |
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87 | |
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88 | /* |
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89 | * bit in the SIU mask registers (PPC bit numbering) that should |
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90 | * be set to enable the relevant interrupt, mask of 32 is for unused entries |
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91 | * |
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92 | */ |
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93 | const static unsigned int SIU_MaskBit [BSP_SIU_IRQ_NUMBER] = { |
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94 | 0, 1, 2, 3, /* smart_comm, psc1, psc2, psc3 */ |
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95 | 4, 5, 6, 7, /* irda/psc6, eth, usb, ata */ |
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96 | 8, 9, 10, 11, /* pci_ctrl, pci_sc_rx, pci_sc_tx, psc4 */ |
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97 | 12, 13, 14, 15, /* psc5,spi_modf, spi_spif, i2c1 */ |
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98 | 16, 17, 18, 19, /* i2c, can1, can2, ir_rx */ |
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99 | 20, 21, 15, 16, /* ir_rx, xlb_arb, slice_tim2, irq1, */ |
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100 | 17, 18, 19, 20, /* irq2, irq3, lo_int, rtc_pint */ |
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101 | 21, 22, 23, 24, /* rtc_sint, gpio_std, gpio_wkup, tmr0 */ |
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102 | 25, 26, 27, 28, /* tmr1, tmr2, tmr3, tmr4 */ |
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103 | 29, 30, 31, 32, /* tmr5, tmr6, tmr7, res */ |
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104 | 32, 32, 32 /* res, res, res */ |
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105 | }; |
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106 | |
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107 | static unsigned char irqPrioTable [BSP_SIU_IRQ_NUMBER] = { |
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108 | /* per. int. priorities (0-7) / 4bit coding / msb is HI/LO selection */ |
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109 | /* msb = 0 -> non-critical per. int. is routed to main int. (LO_int) */ |
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110 | /* msb = 1 -> critical per. int. is routed to critical int. (HI_int) */ |
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111 | 0xF, 0, 0, 0, /* smart_comm (do not change!), psc1, psc2, psc3 */ |
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112 | 0, 0, 0, 0, /* irda, eth, usb, ata */ |
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113 | 0, 0, 0, 0, /* pci_ctrl, pci_sc_rx, pci_sc_tx, res */ |
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114 | 0, 0, 0, 0, /* res, spi_modf, spi_spif, i2c1 */ |
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115 | 0, 0, 0, 0, /* i2c, can1, can2, ir_rx */ |
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116 | 0, 0, /* ir_rx, xlb_arb */ |
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117 | /* main interrupt priorities (0-7) / 4bit coding / msb is INT/SMI selection */ |
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118 | /* msb = 0 -> main int. is routed to processor INT (low vector base 0x500 ) */ |
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119 | /* msb = 1 -> main int. is routed to processor SMI (low vector base 0x1400 ) */ |
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120 | 0, 0, /* slice_tim2, irq1 */ |
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121 | 0, 0, 0, 0, /* irq2, irq3, lo_int, rtc_pint */ |
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122 | 0, 0, 0, 0, /* rtc_sint, gpio_std, gpio_wkup, tmr0 */ |
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123 | 0, 0, 0, 0, /* tmr1, tmr2, tmr3, tmr4 */ |
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124 | 0, 0, 0, /* tmr5, tmr6, tmr7 */ |
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125 | /* critical interrupt priorities (0-3) / 2bit coding / no special purpose of msb */ |
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126 | 0, /* irq0 */ |
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127 | 0, 0, 0 /* slice_tim1, hi_int, ccs_wkup */ |
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128 | }; |
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129 | |
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130 | static uint32_t irqMaskTable [BSP_PER_IRQ_NUMBER + BSP_MAIN_IRQ_NUMBER]; |
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131 | |
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132 | /* |
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133 | * Check if symbolic IRQ name is a Processor IRQ |
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134 | */ |
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135 | static inline bool is_processor_irq( rtems_vector_number irqLine) |
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136 | { |
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137 | |
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138 | return ((irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) |
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139 | && (irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)); |
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140 | } |
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141 | |
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142 | /* |
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143 | * Check for SIU IRQ and return base index |
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144 | */ |
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145 | static inline bool is_siu_irq( rtems_vector_number irqLine) |
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146 | { |
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147 | |
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148 | return ((irqLine <= BSP_SIU_IRQ_MAX_OFFSET) |
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149 | && (irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET)); |
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150 | } |
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151 | |
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152 | /* |
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153 | * Check for SIU IRQ and return base index |
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154 | */ |
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155 | static inline int get_siu_irq_base_index( rtems_vector_number irqLine) |
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156 | { |
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157 | if (irqLine <= BSP_PER_IRQ_MAX_OFFSET) |
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158 | return BSP_PER_IRQ_LOWEST_OFFSET; |
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159 | |
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160 | if (irqLine <= BSP_MAIN_IRQ_MAX_OFFSET) |
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161 | return BSP_MAIN_IRQ_LOWEST_OFFSET; |
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162 | |
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163 | if (irqLine <= BSP_CRIT_IRQ_MAX_OFFSET) |
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164 | return BSP_CRIT_IRQ_LOWEST_OFFSET; |
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165 | |
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166 | return -1; |
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167 | } |
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168 | |
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169 | static inline void BSP_enable_per_irq_at_siu( |
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170 | rtems_vector_number irqLine |
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171 | ) |
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172 | { |
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173 | uint8_t lo_hi_ind = 0, |
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174 | prio_index_offset; |
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175 | uint32_t *reg; |
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176 | |
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177 | /* calculate the index offset of priority value bit field */ |
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178 | prio_index_offset = (irqLine - BSP_PER_IRQ_LOWEST_OFFSET) % 8; |
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179 | |
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180 | /* set interrupt priorities */ |
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181 | if (irqPrioTable [irqLine] <= 15) { |
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182 | |
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183 | /* set peripheral int priority */ |
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184 | reg = (uint32_t *) (&(mpc5200.per_pri_1)); |
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185 | |
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186 | /* choose proper register */ |
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187 | reg += (irqLine >> 3); |
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188 | |
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189 | /* set priority as given in priority table */ |
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190 | *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2))); |
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191 | |
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192 | /* test msb (hash-bit) and set LO_/HI_int indicator */ |
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193 | if ((lo_hi_ind = (irqPrioTable [irqLine] >> 3))) { |
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194 | |
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195 | /* set critical HI_int priority */ |
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196 | reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask)); |
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197 | *reg |= (irqPrioTable [BSP_SIU_IRQ_HI_INT] << 26); |
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198 | |
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199 | /* |
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200 | * critical interrupt handling for the 603le core is not |
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201 | * yet supported, routing of critical interrupts is forced |
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202 | * to core_int (bit 31 / CEb) |
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203 | */ |
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204 | mpc5200.ext_en_type |= 1; |
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205 | |
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206 | } else { |
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207 | if (irqPrioTable [irqLine] <= 15) { |
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208 | /* set main LO_int priority */ |
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209 | reg = (uint32_t *) (&(mpc5200.main_pri_1)); |
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210 | *reg |= (irqPrioTable [BSP_SIU_IRQ_LO_INT] << 16); |
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211 | } |
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212 | } |
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213 | } |
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214 | |
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215 | /* if LO_int ind., enable (unmask) main interrupt */ |
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216 | if (!lo_hi_ind) { |
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217 | mpc5200.crit_pri_main_mask &= |
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218 | ~(0x80000000 >> SIU_MaskBit [BSP_SIU_IRQ_LO_INT]); |
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219 | } |
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220 | |
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221 | /* enable (unmask) peripheral interrupt */ |
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222 | mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]); |
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223 | |
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224 | /* FIXME: Why? */ |
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225 | mpc5200.main_pri_1; |
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226 | mpc5200.crit_pri_main_mask; |
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227 | mpc5200.per_pri_1; |
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228 | mpc5200.per_mask; |
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229 | } |
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230 | |
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231 | static inline void BSP_enable_main_irq_at_siu( |
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232 | rtems_vector_number irqLine |
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233 | ) |
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234 | { |
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235 | |
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236 | uint8_t prio_index_offset; |
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237 | uint32_t *reg; |
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238 | |
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239 | /* calculate the index offset of priority value bit field */ |
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240 | prio_index_offset = (irqLine - BSP_MAIN_IRQ_LOWEST_OFFSET) % 8; |
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241 | |
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242 | /* set main interrupt priority */ |
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243 | if (irqPrioTable [irqLine] <= 15) { |
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244 | |
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245 | /* set main int priority */ |
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246 | reg = (uint32_t *) (&(mpc5200.main_pri_1)); |
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247 | |
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248 | /* choose proper register */ |
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249 | reg += (irqLine >> 3); |
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250 | |
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251 | /* set priority as given in priority table */ |
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252 | *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2))); |
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253 | |
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254 | if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) { |
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255 | /* enable external irq-pin */ |
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256 | mpc5200.ext_en_type |= (0x80000000 >> (20 + prio_index_offset)); |
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257 | } |
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258 | } |
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259 | |
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260 | /* enable (unmask) main interrupt */ |
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261 | mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]); |
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262 | |
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263 | } |
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264 | |
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265 | static inline void BSP_enable_crit_irq_at_siu( |
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266 | rtems_vector_number irqLine |
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267 | ) |
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268 | { |
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269 | uint8_t prio_index_offset; |
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270 | uint32_t *reg; |
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271 | |
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272 | prio_index_offset = irqLine - BSP_CRIT_IRQ_LOWEST_OFFSET; |
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273 | |
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274 | /* |
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275 | * critical interrupt handling for the 603Le core is not |
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276 | * yet supported, routing of critical interrupts is forced |
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277 | * to core_int (bit 31 / CEb) |
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278 | */ |
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279 | mpc5200.ext_en_type |= 1; |
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280 | |
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281 | /* set critical interrupt priorities */ |
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282 | if (irqPrioTable [irqLine] <= 3) { |
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283 | |
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284 | /* choose proper register */ |
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285 | reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask)); |
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286 | |
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287 | /* set priority as given in priority table */ |
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288 | *reg |= (irqPrioTable [irqLine] << (30 - (prio_index_offset << 1))); |
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289 | |
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290 | /* external irq0-pin */ |
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291 | if (irqLine == BSP_SIU_IRQ_IRQ1) { |
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292 | /* enable external irq-pin */ |
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293 | mpc5200.ext_en_type |= (0x80000000 >> (20 + prio_index_offset)); |
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294 | } |
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295 | } |
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296 | } |
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297 | |
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298 | static inline void BSP_disable_per_irq_at_siu( |
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299 | rtems_vector_number irqLine |
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300 | ) |
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301 | { |
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302 | uint8_t prio_index_offset; |
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303 | uint32_t *reg; |
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304 | |
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305 | /* calculate the index offset of priority value bit field */ |
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306 | prio_index_offset = (irqLine - BSP_PER_IRQ_LOWEST_OFFSET) % 8; |
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307 | |
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308 | /* disable (mask) peripheral interrupt */ |
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309 | mpc5200.per_mask |= (0x80000000 >> SIU_MaskBit [irqLine]); |
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310 | |
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311 | /* reset priority to lowest level (reset value) */ |
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312 | reg = (uint32_t *) (&(mpc5200.per_pri_1)); |
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313 | reg += (irqLine >> 3); |
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314 | *reg &= ~(15 << (28 - (prio_index_offset << 2))); |
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315 | } |
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316 | |
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317 | static inline void BSP_disable_main_irq_at_siu( |
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318 | rtems_vector_number irqLine |
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319 | ) |
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320 | { |
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321 | uint8_t prio_index_offset; |
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322 | uint32_t *reg; |
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323 | |
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324 | /* calculate the index offset of priority value bit field */ |
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325 | prio_index_offset = (irqLine - BSP_MAIN_IRQ_LOWEST_OFFSET) % 8; |
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326 | |
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327 | /* disable (mask) main interrupt */ |
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328 | mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit [irqLine]); |
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329 | |
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330 | if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) { |
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331 | /* disable external irq-pin */ |
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332 | mpc5200.ext_en_type &= ~(0x80000000 >> (20 + prio_index_offset)); |
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333 | } |
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334 | |
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335 | /* reset priority to lowest level (reset value) */ |
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336 | reg = (uint32_t *) (&(mpc5200.main_pri_1)); |
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337 | reg += (irqLine >> 3); |
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338 | *reg &= ~(15 << (28 - (prio_index_offset << 2))); |
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339 | } |
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340 | |
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341 | static inline void BSP_disable_crit_irq_at_siu( rtems_vector_number |
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342 | irqLine) |
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343 | { |
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344 | uint8_t prio_index_offset; |
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345 | uint32_t *reg; |
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346 | |
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347 | prio_index_offset = irqLine - BSP_CRIT_IRQ_LOWEST_OFFSET; |
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348 | |
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349 | /* reset critical int priority to lowest level (reset value) */ |
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350 | reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask)); |
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351 | *reg &= ~(3 << (30 - (prio_index_offset << 1))); |
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352 | |
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353 | if (irqLine == BSP_SIU_IRQ_IRQ1) { |
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354 | /* disable external irq0-pin */ |
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355 | mpc5200.ext_en_type &= ~(0x80000000 >> (20 + prio_index_offset)); |
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356 | } |
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357 | } |
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358 | |
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359 | /* |
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360 | * This function enables a given siu interrupt |
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361 | */ |
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362 | rtems_status_code bsp_interrupt_get_attributes( |
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363 | rtems_vector_number vector, |
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364 | rtems_interrupt_attributes *attributes |
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365 | ) |
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366 | { |
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367 | return RTEMS_SUCCESSFUL; |
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368 | } |
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369 | |
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370 | rtems_status_code bsp_interrupt_is_pending( |
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371 | rtems_vector_number vector, |
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372 | bool *pending |
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373 | ) |
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374 | { |
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375 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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376 | bsp_interrupt_assert(pending != NULL); |
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377 | *pending = false; |
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378 | return RTEMS_UNSATISFIED; |
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379 | } |
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380 | |
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381 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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382 | { |
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383 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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384 | return RTEMS_UNSATISFIED; |
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385 | } |
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386 | |
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387 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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388 | { |
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389 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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390 | return RTEMS_UNSATISFIED; |
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391 | } |
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392 | |
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393 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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394 | rtems_vector_number vector, |
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395 | bool *enabled |
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396 | ) |
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397 | { |
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398 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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399 | bsp_interrupt_assert(enabled != NULL); |
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400 | *enabled = false; |
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401 | return RTEMS_UNSATISFIED; |
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402 | } |
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403 | |
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404 | rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector) |
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405 | { |
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406 | int base_index = get_siu_irq_base_index( vector); |
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407 | |
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408 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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409 | |
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410 | if (is_siu_irq( vector)) { |
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411 | rtems_interrupt_level level; |
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412 | |
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413 | rtems_interrupt_disable( level); |
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414 | |
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415 | switch (base_index) { |
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416 | case BSP_PER_IRQ_LOWEST_OFFSET: |
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417 | BSP_enable_per_irq_at_siu( vector); |
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418 | break; |
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419 | case BSP_MAIN_IRQ_LOWEST_OFFSET: |
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420 | BSP_enable_main_irq_at_siu( vector); |
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421 | break; |
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422 | case BSP_CRIT_IRQ_LOWEST_OFFSET: |
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423 | BSP_enable_crit_irq_at_siu( vector); |
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424 | break; |
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425 | default: |
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426 | bsp_interrupt_assert(0); |
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427 | break; |
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428 | } |
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429 | |
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430 | rtems_interrupt_enable( level); |
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431 | } |
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432 | |
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433 | return RTEMS_SUCCESSFUL; |
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434 | } |
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435 | |
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436 | /* |
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437 | * This function disables a given siu interrupt |
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438 | */ |
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439 | rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector) |
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440 | { |
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441 | int base_index = get_siu_irq_base_index( vector); |
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442 | |
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443 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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444 | |
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445 | if (is_siu_irq( vector)) { |
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446 | rtems_interrupt_level level; |
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447 | |
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448 | rtems_interrupt_disable( level); |
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449 | |
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450 | switch (base_index) { |
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451 | case BSP_PER_IRQ_LOWEST_OFFSET: |
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452 | BSP_disable_per_irq_at_siu( vector); |
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453 | break; |
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454 | case BSP_MAIN_IRQ_LOWEST_OFFSET: |
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455 | BSP_disable_main_irq_at_siu( vector); |
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456 | break; |
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457 | case BSP_CRIT_IRQ_LOWEST_OFFSET: |
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458 | BSP_disable_crit_irq_at_siu( vector); |
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459 | break; |
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460 | default: |
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461 | bsp_interrupt_assert(0); |
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462 | break; |
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463 | } |
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464 | |
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465 | rtems_interrupt_enable( level); |
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466 | } |
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467 | |
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468 | return RTEMS_SUCCESSFUL; |
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469 | } |
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470 | |
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471 | #if (BENCHMARK_IRQ_PROCESSING == 0) |
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472 | void BSP_IRQ_Benchmarking_Reset( void) |
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473 | { |
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474 | } |
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475 | void BSP_IRQ_Benchmarking_Report( void) |
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476 | { |
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477 | } |
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478 | #else |
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479 | #include <stdio.h> |
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480 | uint64_t BSP_Starting_TBR; |
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481 | uint64_t BSP_Total_in_ISR; |
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482 | uint32_t BSP_ISR_Count; |
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483 | uint32_t BSP_Worst_ISR; |
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484 | |
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485 | #define BSP_COUNTED_IRQ 16 |
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486 | uint32_t BSP_ISR_Count_Per [BSP_COUNTED_IRQ + 1]; |
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487 | |
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488 | void BSP_IRQ_Benchmarking_Reset( void) |
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489 | { |
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490 | int i; |
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491 | |
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492 | BSP_Starting_TBR = PPC_Get_timebase_register(); |
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493 | BSP_Total_in_ISR = 0; |
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494 | BSP_ISR_Count = 0; |
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495 | BSP_Worst_ISR = 0; |
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496 | for (i = 0; i < BSP_COUNTED_IRQ; i++) |
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497 | BSP_ISR_Count_Per [i] = 0; |
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498 | } |
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499 | |
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500 | static const char *u64tostring( char *buffer, uint64_t v) |
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501 | { |
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502 | sprintf( buffer, "%lld cycles %lld usecs", v, (v / 33)); |
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503 | return buffer; |
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504 | } |
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505 | |
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506 | void BSP_IRQ_Benchmarking_Report( void) |
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507 | { |
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508 | uint64_t now; |
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509 | char buffer [96]; |
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510 | int i; |
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511 | |
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512 | now = PPC_Get_timebase_register(); |
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513 | printk( "Started at: %s\n", u64tostring( buffer, BSP_Starting_TBR)); |
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514 | printk( "Current : %s\n", u64tostring( buffer, now)); |
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515 | printk( "System up : %s\n", u64tostring( buffer, now - BSP_Starting_TBR)); |
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516 | printk( "ISRs : %d\n", BSP_ISR_Count); |
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517 | printk( "ISRs ran : %s\n", u64tostring( buffer, BSP_Total_in_ISR)); |
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518 | printk( "Worst ISR : %s\n", u64tostring( buffer, BSP_Worst_ISR)); |
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519 | for (i = 0; i < BSP_COUNTED_IRQ; i++) |
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520 | printk( "IRQ %d: %d\n", i, BSP_ISR_Count_Per [i]); |
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521 | printk( "Ticks : %d\n", Clock_driver_ticks); |
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522 | } |
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523 | #endif |
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524 | |
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525 | static void dispatch(uint32_t irq, uint32_t offset, volatile uint32_t *maskreg) |
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526 | { |
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527 | #if (ALLOW_IRQ_NESTING == 1) |
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528 | uint32_t msr; |
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529 | uint32_t mask = *maskreg; |
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530 | #endif |
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531 | |
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532 | irq += offset; |
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533 | |
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534 | #if (ALLOW_IRQ_NESTING == 1) |
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535 | *maskreg = mask | irqMaskTable [irq]; |
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536 | /* Make sure that the write operation completed (cache inhibited area) */ |
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537 | *maskreg; |
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538 | msr = ppc_external_exceptions_enable(); |
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539 | #endif |
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540 | |
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541 | bsp_interrupt_handler_dispatch(irq); |
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542 | |
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543 | #if (ALLOW_IRQ_NESTING == 1) |
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544 | ppc_external_exceptions_disable(msr); |
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545 | *maskreg = mask; |
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546 | #endif |
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547 | } |
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548 | |
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549 | /* |
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550 | * High level IRQ handler called from shared_raw_irq_code_entry |
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551 | */ |
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552 | static int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned excNum) |
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553 | { |
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554 | uint32_t irq; |
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555 | uint32_t pmce; |
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556 | |
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557 | #if (BENCHMARK_IRQ_PROCESSING == 1) |
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558 | uint64_t start, |
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559 | stop, |
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560 | thisTime; |
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561 | |
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562 | start = PPC_Get_timebase_register(); |
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563 | BSP_ISR_Count++; |
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564 | if (excNum < BSP_COUNTED_IRQ) |
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565 | BSP_ISR_Count_Per [excNum]++; |
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566 | else |
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567 | printk( "not counting %d\n", excNum); |
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568 | #endif |
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569 | |
---|
570 | /* get the content of main interrupt status register */ |
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571 | pmce = mpc5200.pmce; |
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572 | |
---|
573 | /* critical interrupts are routed to the core_int, see premature |
---|
574 | * initialization |
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575 | */ |
---|
576 | while ((pmce & (PMCE_CSE_STICKY | PMCE_MSE_STICKY)) != 0) { |
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577 | /* first: check for critical interrupt sources (hierarchical order) |
---|
578 | * -> HI_int indicates peripheral sources |
---|
579 | */ |
---|
580 | if ((pmce & PMCE_CSE_STICKY) != 0) { |
---|
581 | /* get source of critical interrupt */ |
---|
582 | irq = PMCE_CSE_SOURCE(pmce); |
---|
583 | |
---|
584 | switch (irq) { |
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585 | /* peripheral HI_int interrupt source detected */ |
---|
586 | case 2: |
---|
587 | /* check for valid peripheral interrupt source */ |
---|
588 | if ((pmce & PMCE_PSE_STICKY) != 0) { |
---|
589 | /* get source of peripheral interrupt */ |
---|
590 | irq = PMCE_PSE_SOURCE(pmce); |
---|
591 | |
---|
592 | dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask); |
---|
593 | } else { |
---|
594 | /* this case may not occur: no valid peripheral |
---|
595 | * interrupt source */ |
---|
596 | printk( "No valid peripheral HI_int interrupt source\n"); |
---|
597 | } |
---|
598 | break; |
---|
599 | |
---|
600 | /* irq0, slice timer 1 or ccs wakeup detected */ |
---|
601 | case 0: |
---|
602 | case 1: |
---|
603 | case 3: |
---|
604 | |
---|
605 | /* add proper offset for critical interrupts in the siu |
---|
606 | * handler array */ |
---|
607 | irq += BSP_CRIT_IRQ_LOWEST_OFFSET; |
---|
608 | |
---|
609 | /* Dispatch interrupt handlers */ |
---|
610 | bsp_interrupt_handler_dispatch( irq); |
---|
611 | |
---|
612 | break; |
---|
613 | |
---|
614 | default: |
---|
615 | /* error: unknown interrupt source */ |
---|
616 | printk( "Unknown HI_int interrupt source\n"); |
---|
617 | break; |
---|
618 | } |
---|
619 | } |
---|
620 | |
---|
621 | /* second: check for main interrupt sources (hierarchical order) |
---|
622 | * -> LO_int indicates peripheral sources */ |
---|
623 | if ((pmce & PMCE_MSE_STICKY) != 0) { |
---|
624 | /* get source of main interrupt */ |
---|
625 | irq = PMCE_MSE_SOURCE(pmce); |
---|
626 | |
---|
627 | if (irq == 4) { |
---|
628 | /* peripheral LO_int interrupt source detected */ |
---|
629 | /* check for valid peripheral interrupt source */ |
---|
630 | if ((pmce & PMCE_PSE_STICKY) != 0) { |
---|
631 | /* get source of peripheral interrupt */ |
---|
632 | irq = PMCE_PSE_SOURCE(pmce); |
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633 | |
---|
634 | dispatch(irq, BSP_PER_IRQ_LOWEST_OFFSET, &mpc5200.per_mask); |
---|
635 | } else { |
---|
636 | /* this case may not occur: no valid peripheral |
---|
637 | * interrupt source */ |
---|
638 | printk( "No valid peripheral LO_int interrupt source\n"); |
---|
639 | } |
---|
640 | } else if (irq <= 16) { |
---|
641 | /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer |
---|
642 | * 2 is always routed to SMI) */ |
---|
643 | dispatch(irq, BSP_MAIN_IRQ_LOWEST_OFFSET, &mpc5200.crit_pri_main_mask); |
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644 | } else { |
---|
645 | /* error: unknown interrupt source */ |
---|
646 | printk( "Unknown peripheral LO_int interrupt source\n"); |
---|
647 | } |
---|
648 | } |
---|
649 | |
---|
650 | /* force re-evaluation of interrupts */ |
---|
651 | mpc5200.pmce = PMCE_CSE_STICKY | PMCE_MSE_STICKY | PMCE_PSE_STICKY; |
---|
652 | |
---|
653 | /* get the content of main interrupt status register */ |
---|
654 | pmce = mpc5200.pmce; |
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655 | } |
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656 | |
---|
657 | #if (BENCHMARK_IRQ_PROCESSING == 1) |
---|
658 | stop = PPC_Get_timebase_register(); |
---|
659 | thisTime = stop - start; |
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660 | BSP_Total_in_ISR += thisTime; |
---|
661 | if (thisTime > BSP_Worst_ISR) |
---|
662 | BSP_Worst_ISR = thisTime; |
---|
663 | #endif |
---|
664 | |
---|
665 | return 0; |
---|
666 | } |
---|
667 | |
---|
668 | /* |
---|
669 | * setup irqMaskTable to support a priorized/nested interrupt environment |
---|
670 | */ |
---|
671 | static void setup_irqMaskTable( void) |
---|
672 | { |
---|
673 | rtems_irq_prio prio = 0; |
---|
674 | uint32_t i = 0, |
---|
675 | j = 0, |
---|
676 | mask = 0; |
---|
677 | |
---|
678 | /* set up the priority dependent masks for peripheral interrupts */ |
---|
679 | for (i = BSP_PER_IRQ_LOWEST_OFFSET; i <= BSP_PER_IRQ_MAX_OFFSET; i++) { |
---|
680 | prio = irqPrioTable [i]; |
---|
681 | mask = 0; |
---|
682 | |
---|
683 | for (j = BSP_PER_IRQ_LOWEST_OFFSET; j <= BSP_PER_IRQ_MAX_OFFSET; j++) { |
---|
684 | if (prio > irqPrioTable [j]) { |
---|
685 | mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET)); |
---|
686 | } |
---|
687 | |
---|
688 | if ((prio == irqPrioTable [j]) && (j >= i)) { |
---|
689 | mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET)); |
---|
690 | } |
---|
691 | } |
---|
692 | |
---|
693 | irqMaskTable [i] = mask; |
---|
694 | } |
---|
695 | |
---|
696 | /* set up the priority dependent masks for main interrupts */ |
---|
697 | for (i = BSP_MAIN_IRQ_LOWEST_OFFSET; i <= BSP_MAIN_IRQ_MAX_OFFSET; i++) { |
---|
698 | prio = irqPrioTable [i]; |
---|
699 | mask = 0; |
---|
700 | |
---|
701 | for (j = BSP_MAIN_IRQ_LOWEST_OFFSET; j <= BSP_MAIN_IRQ_MAX_OFFSET; j++) { |
---|
702 | if (prio > irqPrioTable [j]) { |
---|
703 | mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET)); |
---|
704 | } |
---|
705 | |
---|
706 | if ((prio == irqPrioTable [j]) && (j >= i)) { |
---|
707 | mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET)); |
---|
708 | } |
---|
709 | } |
---|
710 | |
---|
711 | irqMaskTable [i] = mask; |
---|
712 | } |
---|
713 | } |
---|
714 | |
---|
715 | /* |
---|
716 | * Initialize MPC5x00 SIU interrupt management |
---|
717 | */ |
---|
718 | static void BSP_SIU_irq_init( void) |
---|
719 | { |
---|
720 | |
---|
721 | /* disable all peripheral interrupts */ |
---|
722 | mpc5200.per_mask = 0xFFFFFC00; |
---|
723 | |
---|
724 | /* peripheral interrupt priorities according to reset value */ |
---|
725 | mpc5200.per_pri_1 = 0xF0000000; |
---|
726 | mpc5200.per_pri_2 = 0x00000000; |
---|
727 | mpc5200.per_pri_3 = 0x00000000; |
---|
728 | |
---|
729 | /* disable external interrupts IRQ0-4 / critical interrupts are routed to core_int */ |
---|
730 | mpc5200.ext_en_type = 0x0F000001; |
---|
731 | |
---|
732 | /* disable main interrupts / crit. int. priorities according to reset values */ |
---|
733 | mpc5200.crit_pri_main_mask = 0x0001FFFF; |
---|
734 | |
---|
735 | /* main priorities according to reset value */ |
---|
736 | mpc5200.main_pri_1 = 0; |
---|
737 | mpc5200.main_pri_2 = 0; |
---|
738 | |
---|
739 | /* reset all status indicators */ |
---|
740 | mpc5200.csa = 0x0001FFFF; |
---|
741 | mpc5200.msa = 0x0001FFFF; |
---|
742 | mpc5200.psa = 0x003FFFFF; |
---|
743 | mpc5200.psa_be = 0x03000000; |
---|
744 | |
---|
745 | setup_irqMaskTable(); |
---|
746 | } |
---|
747 | |
---|
748 | rtems_status_code bsp_interrupt_facility_initialize( void) |
---|
749 | { |
---|
750 | BSP_SIU_irq_init(); |
---|
751 | |
---|
752 | /* Install exception handler */ |
---|
753 | if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) { |
---|
754 | return RTEMS_IO_ERROR; |
---|
755 | } |
---|
756 | if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) { |
---|
757 | return RTEMS_IO_ERROR; |
---|
758 | } |
---|
759 | |
---|
760 | return RTEMS_SUCCESSFUL; |
---|
761 | } |
---|
762 | |
---|
763 | void bsp_interrupt_handler_default( rtems_vector_number vector) |
---|
764 | { |
---|
765 | if (vector != BSP_DECREMENTER) { |
---|
766 | printk( "Spurious interrupt: 0x%08" PRIx32 "\n", vector); |
---|
767 | } |
---|
768 | } |
---|