source: rtems/bsps/powerpc/gen5200/ata/ata-dma-pio-single.c

Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

Update company name

The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.

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1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (C) 2011, 2013 embedded brains GmbH & Co. KG
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define NDEBUG
29
30#include <bsp/ata.h>
31
32#include <libcpu/powerpc-utility.h>
33
34#include <bsp.h>
35#include <bsp/fatal.h>
36#include <bsp/irq.h>
37
38typedef enum {
39  DATA_CURRENT = 0,
40  DATA_END,
41  DATA_REG
42} variables;
43
44typedef enum {
45  INC_0_NE = 0,
46  INC_2_NE
47} increments;
48
49/*
50 * for
51 *   idx0 = DATA_CURRENT, idx1 = DATA_REG
52 *   idx0 != DATA_END
53 *   idx0 += 2, idx1 += 0
54 * do
55 *   *idx0 = *idx1 [INT, 16 bit] OR *idx1 = *idx0 [INT, 16 bit]
56 */
57static const uint32_t ops[] = {
58  LCD(0, VAR(DATA_CURRENT), 0, VAR(DATA_REG), TERM_FIRST, VAR(DATA_END), INC_2_NE, INC_0_NE),
59    0, /* Transfer opcode, see transfer() */
60};
61
62static bool is_last_transfer(const ata_driver_dma_pio_single *self)
63{
64  return self->transfer_current + 1 == self->transfer_end;
65}
66
67static void start_sector_transfer(ata_driver_dma_pio_single *self)
68{
69  uint16_t *current = ata_sg_get_sector_data_begin(&self->sg_context, self->transfer_current);
70  bestcomm_task_set_variable(&self->task, DATA_CURRENT, (uint32_t) current);
71  bestcomm_task_set_variable(&self->task, DATA_END, (uint32_t) ata_sg_get_sector_data_end(&self->sg_context, current));
72  bestcomm_task_start(&self->task);
73
74  bool last = is_last_transfer(self);
75  ++self->transfer_current;
76
77  if (!last) {
78    ata_flush_sector(ata_sg_get_sector_data_begin(&self->sg_context, self->transfer_current));
79  }
80}
81
82static void dma_pio_single_interrupt_handler(void *arg)
83{
84  ata_driver_dma_pio_single *self = arg;
85  bool ok = ata_check_status();
86  bool send_event = false;
87  if (ok && self->transfer_current != self->transfer_end) {
88    bool enable_dma_interrupt = self->read && is_last_transfer(self);
89    if (enable_dma_interrupt) {
90      bestcomm_task_irq_clear(&self->task);
91      bestcomm_task_irq_enable(&self->task);
92    }
93
94    start_sector_transfer(self);
95  } else {
96    send_event = true;
97  }
98
99  if (send_event) {
100    bestcomm_task_wakeup_event_task(&self->task);
101  }
102}
103
104static bool transfer_dma_pio_single(ata_driver *super, bool read, rtems_blkdev_sg_buffer *sg, size_t sg_count)
105{
106  bool ok = true;
107  ata_driver_dma_pio_single *self = (ata_driver_dma_pio_single *) super;
108
109  self->read = read;
110  ata_sg_reset(&self->sg_context, sg, sg_count);
111  rtems_blkdev_bnum start_sector = ata_sg_get_start_sector(&self->sg_context);
112  rtems_blkdev_bnum sector_count = ata_sg_get_sector_count(&self->sg_context);
113  rtems_blkdev_bnum relative_sector = 0;
114
115  ata_flush_sector(ata_sg_get_sector_data_begin(&self->sg_context, relative_sector));
116
117  uint8_t command = ata_read_or_write_sectors_command(read);
118
119  uint32_t opcode;
120  if (read) {
121    opcode = DRD1A(INT, INIT_ALWAYS, DEST_DEREF_IDX(0), SZ_16, SRC_DEREF_IDX(1), SZ_16);
122  } else {
123    opcode = DRD1A(INT, INIT_ALWAYS, DEST_DEREF_IDX(1), SZ_16, SRC_DEREF_IDX(0), SZ_16);
124  }
125
126  bestcomm_task_irq_disable(&self->task);
127  bestcomm_task_associate_with_current_task(&self->task);
128
129  size_t transfer_opcode_index = 1; /* See ops */
130  bestcomm_task_set_opcode(&self->task, transfer_opcode_index, opcode);
131
132  while (ok && relative_sector < sector_count) {
133    rtems_blkdev_bnum remaining_sectors = sector_count - relative_sector;
134    rtems_blkdev_bnum transfer_count = ata_max_transfer_count(remaining_sectors);
135
136    self->transfer_current = relative_sector;
137    self->transfer_end = relative_sector + transfer_count;
138
139    ok = ata_execute_io_command(command, start_sector + relative_sector, transfer_count);
140    if (ok) {
141      if (!read) {
142        ok = ata_wait_for_data_request();
143        assert(ok);
144
145        rtems_interrupt_level level;
146        rtems_interrupt_disable(level);
147        start_sector_transfer(self);
148        rtems_interrupt_enable(level);
149      }
150
151      bestcomm_task_wait(&self->task);
152
153      ok = ata_check_status();
154
155      relative_sector += ATA_PER_TRANSFER_SECTOR_COUNT_MAX;
156    }
157  }
158
159  return ok;
160}
161
162static int io_control_dma_pio_single(
163  rtems_disk_device *dd,
164  uint32_t cmd,
165  void *arg
166)
167{
168  return ata_driver_io_control(dd, cmd, arg, transfer_dma_pio_single);
169}
170
171void ata_driver_dma_pio_single_create(ata_driver_dma_pio_single *self, const char *device_file_path, TaskId task_index)
172{
173  ata_driver_create(&self->super, device_file_path, io_control_dma_pio_single);
174
175  self->read = false;
176
177  if (ata_driver_is_card_present(&self->super)) {
178    bestcomm_task_create_and_load(&self->task, task_index, ops, sizeof(ops));
179
180    bestcomm_task_set_variable(&self->task, DATA_REG, (uint32_t) &ATA->write.data);
181
182    bestcomm_task_set_increment_and_condition(&self->task, INC_0_NE, 0, COND_NE);
183    bestcomm_task_set_increment_and_condition(&self->task, INC_2_NE, 2, COND_NE);
184
185    bestcomm_task_enable_combined_write(&self->task, true);
186    bestcomm_task_enable_read_buffer(&self->task, true);
187    bestcomm_task_enable_speculative_read(&self->task, true);
188
189    ata_clear_interrupts();
190
191    rtems_status_code sc = rtems_interrupt_handler_install(
192      BSP_SIU_IRQ_ATA,
193      "ATA",
194      RTEMS_INTERRUPT_UNIQUE,
195      dma_pio_single_interrupt_handler,
196      self
197    );
198    if (sc != RTEMS_SUCCESSFUL) {
199      bsp_fatal(MPC5200_FATAL_ATA_DMA_SINGLE_IRQ_INSTALL);
200    }
201  }
202}
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