1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /* |
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4 | * Copyright (C) 2011, 2013 embedded brains GmbH & Co. KG |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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25 | * POSSIBILITY OF SUCH DAMAGE. |
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26 | */ |
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27 | |
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28 | #define NDEBUG |
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29 | |
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30 | #include <bsp/ata.h> |
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31 | |
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32 | #include <libcpu/powerpc-utility.h> |
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33 | |
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34 | #include <bsp.h> |
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35 | #include <bsp/fatal.h> |
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36 | #include <bsp/irq.h> |
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37 | |
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38 | typedef enum { |
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39 | DATA_CURRENT = 0, |
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40 | DATA_END, |
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41 | DATA_REG |
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42 | } variables; |
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43 | |
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44 | typedef enum { |
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45 | INC_0_NE = 0, |
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46 | INC_2_NE |
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47 | } increments; |
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48 | |
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49 | /* |
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50 | * for |
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51 | * idx0 = DATA_CURRENT, idx1 = DATA_REG |
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52 | * idx0 != DATA_END |
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53 | * idx0 += 2, idx1 += 0 |
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54 | * do |
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55 | * *idx0 = *idx1 [INT, 16 bit] OR *idx1 = *idx0 [INT, 16 bit] |
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56 | */ |
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57 | static const uint32_t ops[] = { |
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58 | LCD(0, VAR(DATA_CURRENT), 0, VAR(DATA_REG), TERM_FIRST, VAR(DATA_END), INC_2_NE, INC_0_NE), |
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59 | 0, /* Transfer opcode, see transfer() */ |
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60 | }; |
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61 | |
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62 | static bool is_last_transfer(const ata_driver_dma_pio_single *self) |
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63 | { |
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64 | return self->transfer_current + 1 == self->transfer_end; |
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65 | } |
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66 | |
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67 | static void start_sector_transfer(ata_driver_dma_pio_single *self) |
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68 | { |
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69 | uint16_t *current = ata_sg_get_sector_data_begin(&self->sg_context, self->transfer_current); |
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70 | bestcomm_task_set_variable(&self->task, DATA_CURRENT, (uint32_t) current); |
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71 | bestcomm_task_set_variable(&self->task, DATA_END, (uint32_t) ata_sg_get_sector_data_end(&self->sg_context, current)); |
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72 | bestcomm_task_start(&self->task); |
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73 | |
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74 | bool last = is_last_transfer(self); |
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75 | ++self->transfer_current; |
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76 | |
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77 | if (!last) { |
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78 | ata_flush_sector(ata_sg_get_sector_data_begin(&self->sg_context, self->transfer_current)); |
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79 | } |
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80 | } |
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81 | |
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82 | static void dma_pio_single_interrupt_handler(void *arg) |
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83 | { |
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84 | ata_driver_dma_pio_single *self = arg; |
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85 | bool ok = ata_check_status(); |
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86 | bool send_event = false; |
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87 | if (ok && self->transfer_current != self->transfer_end) { |
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88 | bool enable_dma_interrupt = self->read && is_last_transfer(self); |
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89 | if (enable_dma_interrupt) { |
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90 | bestcomm_task_irq_clear(&self->task); |
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91 | bestcomm_task_irq_enable(&self->task); |
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92 | } |
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93 | |
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94 | start_sector_transfer(self); |
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95 | } else { |
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96 | send_event = true; |
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97 | } |
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98 | |
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99 | if (send_event) { |
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100 | bestcomm_task_wakeup_event_task(&self->task); |
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101 | } |
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102 | } |
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103 | |
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104 | static bool transfer_dma_pio_single(ata_driver *super, bool read, rtems_blkdev_sg_buffer *sg, size_t sg_count) |
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105 | { |
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106 | bool ok = true; |
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107 | ata_driver_dma_pio_single *self = (ata_driver_dma_pio_single *) super; |
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108 | |
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109 | self->read = read; |
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110 | ata_sg_reset(&self->sg_context, sg, sg_count); |
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111 | rtems_blkdev_bnum start_sector = ata_sg_get_start_sector(&self->sg_context); |
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112 | rtems_blkdev_bnum sector_count = ata_sg_get_sector_count(&self->sg_context); |
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113 | rtems_blkdev_bnum relative_sector = 0; |
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114 | |
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115 | ata_flush_sector(ata_sg_get_sector_data_begin(&self->sg_context, relative_sector)); |
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116 | |
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117 | uint8_t command = ata_read_or_write_sectors_command(read); |
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118 | |
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119 | uint32_t opcode; |
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120 | if (read) { |
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121 | opcode = DRD1A(INT, INIT_ALWAYS, DEST_DEREF_IDX(0), SZ_16, SRC_DEREF_IDX(1), SZ_16); |
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122 | } else { |
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123 | opcode = DRD1A(INT, INIT_ALWAYS, DEST_DEREF_IDX(1), SZ_16, SRC_DEREF_IDX(0), SZ_16); |
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124 | } |
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125 | |
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126 | bestcomm_task_irq_disable(&self->task); |
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127 | bestcomm_task_associate_with_current_task(&self->task); |
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128 | |
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129 | size_t transfer_opcode_index = 1; /* See ops */ |
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130 | bestcomm_task_set_opcode(&self->task, transfer_opcode_index, opcode); |
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131 | |
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132 | while (ok && relative_sector < sector_count) { |
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133 | rtems_blkdev_bnum remaining_sectors = sector_count - relative_sector; |
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134 | rtems_blkdev_bnum transfer_count = ata_max_transfer_count(remaining_sectors); |
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135 | |
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136 | self->transfer_current = relative_sector; |
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137 | self->transfer_end = relative_sector + transfer_count; |
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138 | |
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139 | ok = ata_execute_io_command(command, start_sector + relative_sector, transfer_count); |
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140 | if (ok) { |
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141 | if (!read) { |
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142 | ok = ata_wait_for_data_request(); |
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143 | assert(ok); |
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144 | |
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145 | rtems_interrupt_level level; |
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146 | rtems_interrupt_disable(level); |
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147 | start_sector_transfer(self); |
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148 | rtems_interrupt_enable(level); |
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149 | } |
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150 | |
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151 | bestcomm_task_wait(&self->task); |
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152 | |
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153 | ok = ata_check_status(); |
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154 | |
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155 | relative_sector += ATA_PER_TRANSFER_SECTOR_COUNT_MAX; |
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156 | } |
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157 | } |
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158 | |
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159 | return ok; |
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160 | } |
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161 | |
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162 | static int io_control_dma_pio_single( |
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163 | rtems_disk_device *dd, |
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164 | uint32_t cmd, |
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165 | void *arg |
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166 | ) |
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167 | { |
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168 | return ata_driver_io_control(dd, cmd, arg, transfer_dma_pio_single); |
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169 | } |
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170 | |
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171 | void ata_driver_dma_pio_single_create(ata_driver_dma_pio_single *self, const char *device_file_path, TaskId task_index) |
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172 | { |
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173 | ata_driver_create(&self->super, device_file_path, io_control_dma_pio_single); |
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174 | |
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175 | self->read = false; |
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176 | |
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177 | if (ata_driver_is_card_present(&self->super)) { |
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178 | bestcomm_task_create_and_load(&self->task, task_index, ops, sizeof(ops)); |
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179 | |
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180 | bestcomm_task_set_variable(&self->task, DATA_REG, (uint32_t) &ATA->write.data); |
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181 | |
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182 | bestcomm_task_set_increment_and_condition(&self->task, INC_0_NE, 0, COND_NE); |
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183 | bestcomm_task_set_increment_and_condition(&self->task, INC_2_NE, 2, COND_NE); |
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184 | |
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185 | bestcomm_task_enable_combined_write(&self->task, true); |
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186 | bestcomm_task_enable_read_buffer(&self->task, true); |
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187 | bestcomm_task_enable_speculative_read(&self->task, true); |
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188 | |
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189 | ata_clear_interrupts(); |
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190 | |
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191 | rtems_status_code sc = rtems_interrupt_handler_install( |
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192 | BSP_SIU_IRQ_ATA, |
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193 | "ATA", |
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194 | RTEMS_INTERRUPT_UNIQUE, |
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195 | dma_pio_single_interrupt_handler, |
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196 | self |
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197 | ); |
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198 | if (sc != RTEMS_SUCCESSFUL) { |
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199 | bsp_fatal(MPC5200_FATAL_ATA_DMA_SINGLE_IRQ_INSTALL); |
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200 | } |
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201 | } |
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202 | } |
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