source: rtems/bsps/powerpc/gen5200/README @ 90232bc

5
Last change on this file since 90232bc was eb36d11, checked in by Sebastian Huber <sebastian.huber@…>, on 04/25/18 at 13:06:08

bsps: Move documentation, etc. files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.
  • Property mode set to 100644
File size: 1.4 KB
Line 
1#
2#  README
3#
4
5BSP NAME:           gen5200
6BOARD:              various boards based on MPC5200 Controller:
7                    MicroSys PM520 with Carrier board CR825
8BUS:                N/A
9CPU FAMILY:         ppc
10CPU:                PowerPC MPC5200
11COPROCESSORS:       Hardware FPU
12MODE:               32 bit mode, I and D cache enabled
13DEBUG MONITOR:      None
14
15PERIPHERALS
16===========
17TIMERS:             GPT
18SERIAL PORTS:       3 PSCs                     
19                    2 CAN IFs
20                    1 I2C IF
21REAL-TIME CLOCK:    PCF8563
22DMA:                for Ethernet and CompactFlash
23VIDEO:              none
24SCSI:               none
25IDE:                1 CompactFlash Slot supported
26NETWORKING:         1 FEC Fast Ethernet
27
28DRIVER INFORMATION
29==================
30CLOCK DRIVER:       using one GPT
31IOSUPP DRIVER:      none
32SHMSUPP:            none
33TIMER DRIVER:       Timebase register (lower 32 bits only)
34
35STDIO
36=====
37PORT:               PSC1
38ELECTRICAL:         RS-232
39BAUD:               9600
40BITS PER CHARACTER: 8
41PARITY:             None
42STOP BITS:          1
43
44NOTES
45=====
46On-chip resources:
47        PSC1            /dev/console /dev/tty00
48        PSC2            /dev/tty01
49        PSC3            /dev/tty02
50
51
52Board description
53-----------------
54
55Clock rate:     external clock: 33MHz
56Bus width:      32 bit Flash, 32 bit SDRAM
57FLASH:          8MByte
58RAM:            64MByte SDRAM
59
60
61Debugging/ Code loading:
62------------------------
63
64Tested using the Lauterbach TRACE32 ICD debugger.
65
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