[b7a6d23a] | 1 | /* Adjust a PCI bus range's I/O address space by adding an offset */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Authorship |
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| 5 | * ---------- |
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| 6 | * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was |
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| 7 | * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, |
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[2cb449d] | 8 | * Stanford Linear Accelerator Center, Stanford University. |
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[b7a6d23a] | 9 | * |
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| 10 | * Acknowledgement of sponsorship |
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| 11 | * ------------------------------ |
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| 12 | * The 'beatnik' BSP was produced by |
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| 13 | * the Stanford Linear Accelerator Center, Stanford University, |
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[2cb449d] | 14 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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[b7a6d23a] | 15 | * |
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| 16 | * Government disclaimer of liability |
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| 17 | * ---------------------------------- |
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| 18 | * Neither the United States nor the United States Department of Energy, |
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| 19 | * nor any of their employees, makes any warranty, express or implied, or |
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| 20 | * assumes any legal liability or responsibility for the accuracy, |
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| 21 | * completeness, or usefulness of any data, apparatus, product, or process |
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| 22 | * disclosed, or represents that its use would not infringe privately owned |
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| 23 | * rights. |
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| 24 | * |
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| 25 | * Stanford disclaimer of liability |
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| 26 | * -------------------------------- |
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| 27 | * Stanford University makes no representations or warranties, express or |
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| 28 | * implied, nor assumes any liability for the use of this software. |
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| 29 | * |
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| 30 | * Stanford disclaimer of copyright |
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| 31 | * -------------------------------- |
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| 32 | * Stanford University, owner of the copyright, hereby disclaims its |
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| 33 | * copyright and all other rights in this software. Hence, anyone may |
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| 34 | * freely use it for any purpose without restriction. |
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| 35 | * |
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| 36 | * Maintenance of notices |
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| 37 | * ---------------------- |
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| 38 | * In the interest of clarity regarding the origin and status of this |
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| 39 | * SLAC software, this and all the preceding Stanford University notices |
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| 40 | * are to remain affixed to any copy or derivative of this software made |
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| 41 | * or distributed by the recipient and are to be affixed to any copy of |
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| 42 | * software made or distributed by the recipient that contains a copy or |
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| 43 | * derivative of this software. |
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| 44 | * |
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| 45 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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| 46 | */ |
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| 47 | |
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| 48 | #include <rtems.h> |
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| 49 | #include <rtems/bspIo.h> |
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| 50 | #include <bsp/pci.h> |
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| 51 | #include <stdint.h> |
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[2cb449d] | 52 | #include "pci_io_remap.h" |
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[b7a6d23a] | 53 | |
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| 54 | #ifndef PCI_MULTI_FUN |
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| 55 | #define PCI_MULTI_FUN 0x80 |
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| 56 | #endif |
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| 57 | |
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| 58 | #ifndef PCI_HEADER_TYPE_MSK |
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| 59 | #define PCI_HEADER_TYPE_MSK 0x7f |
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| 60 | #endif |
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| 61 | |
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| 62 | /* Reconfigure all I/O base address registers for a range of PCI busses |
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| 63 | * (from and including 'bus_from' up to and not including 'bus_to'). |
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| 64 | * adding an offset. This involves adjusting the base and limit registers |
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| 65 | * of PCI-PCI bridges, too. |
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| 66 | * |
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| 67 | * RESTRICTIONS: 'offset' must be 4k aligned (PCI req.); no argument check |
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[2cb449d] | 68 | * on the bus numbers is done. |
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[b7a6d23a] | 69 | * |
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| 70 | * RETURNS: 0 on success and a number > 0 indicating the number of |
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| 71 | * non-32bit bridges found where the offset couldn't be added. |
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| 72 | * Devices behind such a bridge are not accessible through I/O |
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| 73 | * and should probably be switched off (not done by this code). |
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| 74 | */ |
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| 75 | int |
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| 76 | rtems_pci_io_remap(int bus_from, int bus_to, uint32_t offset) |
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| 77 | { |
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[2cb449d] | 78 | int rval = 0; |
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| 79 | int bus, dev, fun, maxf; |
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| 80 | int bar, numBars = 0; |
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| 81 | uint8_t b; |
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| 82 | uint16_t s; |
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| 83 | uint32_t d; |
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| 84 | unsigned int bas, lim; |
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| 85 | |
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| 86 | if ( offset & ((1<<12)-1) ) { |
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[1c193a2] | 87 | rtems_panic("rtems_pci_io_remap(): offset must be 4k aligned"); |
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[2cb449d] | 88 | return -1; |
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| 89 | } |
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| 90 | |
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| 91 | |
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| 92 | for ( bus=bus_from; bus < bus_to; bus++ ) { |
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| 93 | for ( dev = 0; dev<PCI_MAX_DEVICES; dev++ ) { |
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| 94 | |
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| 95 | maxf = 1; |
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| 96 | |
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| 97 | for ( fun = 0; fun < maxf; fun++ ) { |
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| 98 | pci_read_config_word( bus, dev, fun, PCI_VENDOR_ID, &s ); |
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| 99 | if ( 0xffff == s ) |
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| 100 | continue; |
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| 101 | |
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| 102 | pci_read_config_byte( bus, dev, fun, PCI_HEADER_TYPE, &b ); |
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| 103 | |
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| 104 | /* readjust the max. function number to scan if this is a multi-function |
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| 105 | * device. |
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| 106 | */ |
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| 107 | if ( 0 == fun && (PCI_MULTI_FUN & b) ) |
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| 108 | maxf = PCI_MAX_FUNCTIONS; |
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| 109 | |
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| 110 | /* Check the header type; panic if unknown. |
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| 111 | * header type 0 has 6 bars, header type 1 (PCI-PCI bridge) has 2 |
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| 112 | */ |
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| 113 | b &= PCI_HEADER_TYPE_MSK; |
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| 114 | switch ( b ) { |
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| 115 | default: |
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| 116 | printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun); |
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[1c193a2] | 117 | rtems_panic("rtems_pci_io_remap(): unknown PCI header type"); |
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[2cb449d] | 118 | return -1; /* keep compiler happy */ |
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| 119 | |
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| 120 | case PCI_HEADER_TYPE_CARDBUS: |
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| 121 | printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun); |
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[1c193a2] | 122 | rtems_panic("rtems_pci_io_remap(): don't know how to deal with Cardbus bridge"); |
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[2cb449d] | 123 | return -1; |
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| 124 | |
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| 125 | case PCI_HEADER_TYPE_NORMAL: |
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| 126 | numBars = 6*4; /* loop below counts reg. offset in bytes */ |
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| 127 | break; |
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| 128 | |
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| 129 | case PCI_HEADER_TYPE_BRIDGE: |
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| 130 | numBars = 2*4; /* loop below counts reg. offset in bytes */ |
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| 131 | break; |
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| 132 | |
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| 133 | } |
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| 134 | |
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| 135 | for ( bar = 0; bar < numBars; bar+=4 ) { |
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| 136 | pci_read_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, &d ); |
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| 137 | if ( PCI_BASE_ADDRESS_SPACE_IO & d ) { |
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| 138 | /* It's an I/O BAR; remap */ |
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| 139 | d &= PCI_BASE_ADDRESS_IO_MASK; |
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| 140 | if ( d ) { |
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| 141 | /* IO bar was configured; add offset */ |
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| 142 | d += offset; |
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| 143 | pci_write_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, d ); |
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| 144 | } |
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| 145 | } else { |
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| 146 | /* skip upper half of 64-bit window */ |
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| 147 | d &= PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
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| 148 | if ( PCI_BASE_ADDRESS_MEM_TYPE_64 == d ) |
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| 149 | bar+=4; |
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| 150 | } |
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| 151 | } |
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| 152 | |
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| 153 | /* Now it's time to deal with bridges */ |
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| 154 | if ( PCI_HEADER_TYPE_BRIDGE == b ) { |
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| 155 | /* must adjust the limit registers */ |
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| 156 | pci_read_config_byte( bus, dev, fun, PCI_IO_LIMIT, &b ); |
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| 157 | pci_read_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, &s ); |
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| 158 | lim = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8); |
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| 159 | lim += offset; |
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| 160 | |
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| 161 | pci_read_config_byte( bus, dev, fun, PCI_IO_BASE, &b ); |
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| 162 | pci_read_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, &s ); |
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| 163 | bas = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8); |
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| 164 | bas += offset; |
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| 165 | |
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| 166 | b &= PCI_IO_RANGE_TYPE_MASK; |
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| 167 | switch ( b ) { |
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| 168 | default: |
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| 169 | printk("Unknown IO range type 0x%x (@%i/%i/%i)\n", b, bus, dev, fun); |
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[1c193a2] | 170 | rtems_panic("rtems_pci_io_remap(): unknown IO range type"); |
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[2cb449d] | 171 | return -1; |
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| 172 | |
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| 173 | case PCI_IO_RANGE_TYPE_16: |
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| 174 | if ( bas > 0xffff || lim > 0xffff ) { |
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| 175 | printk("PCI I/O range type 1 (16bit) bridge (@%i/%i/%i) found:\n", bus, dev, fun); |
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| 176 | printk("WARNING: base (0x%08x) or limit (0x%08x) exceed 16-bit;\n", bas, lim); |
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| 177 | printk(" devices behind this bridge are NOT accessible!\n"); |
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| 178 | |
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| 179 | /* FIXME: should we disable devices behind this bridge ? */ |
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| 180 | bas = lim = 0; |
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| 181 | } |
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| 182 | break; |
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| 183 | |
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| 184 | case PCI_IO_RANGE_TYPE_32: |
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| 185 | break; |
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| 186 | } |
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| 187 | |
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| 188 | b = (uint8_t)((bas>>8) & PCI_IO_RANGE_MASK); |
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| 189 | pci_write_config_byte( bus, dev, fun, PCI_IO_BASE, b ); |
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| 190 | |
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| 191 | s = (uint16_t)((bas>>16)&0xffff); |
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| 192 | pci_write_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, s); |
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| 193 | |
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| 194 | b = (uint8_t)((lim>>8) & PCI_IO_RANGE_MASK); |
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| 195 | pci_write_config_byte( bus, dev, fun, PCI_IO_LIMIT, b ); |
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| 196 | s = (uint16_t)((lim>>16)&0xffff); |
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| 197 | pci_write_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, s ); |
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| 198 | } |
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| 199 | } |
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| 200 | } |
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| 201 | } |
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| 202 | return rval; |
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[b7a6d23a] | 203 | } |
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