1 | /* PCI configuration space access */ |
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2 | |
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3 | /* |
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4 | * Acknowledgements: |
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5 | * Valuable information was obtained from the following drivers |
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6 | * netbsd: (C) Allegro Networks Inc; Wasabi Systems Inc. |
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7 | * linux: (C) MontaVista, Software, Inc; Chris Zankel, Mark A. Greer. |
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8 | * rtems: (C) Brookhaven National Laboratory; K. Feng |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Original file header of libbsp/shared/pci.c where this file is based upon. |
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13 | * |
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14 | * Copyright (C) 1999 valette@crf.canon.fr |
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15 | * |
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16 | * This code is heavily inspired by the public specification of STREAM V2 |
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17 | * that can be found at : |
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18 | * |
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19 | * <http://www.chorus.com/Documentation/index.html> by following |
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20 | * the STREAM API Specification Document link. |
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21 | * |
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22 | * The license and distribution terms for this file may be |
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23 | * found in the file LICENSE in this distribution or at |
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24 | * http://www.rtems.org/license/LICENSE. |
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25 | * |
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26 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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27 | * - separated bridge detection code out of this file |
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28 | */ |
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29 | |
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30 | #include <rtems.h> |
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31 | #include <bsp.h> |
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32 | #include <libcpu/io.h> |
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33 | #include <bsp/pci.h> |
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34 | #include <rtems/bspIo.h> |
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35 | #include <stdint.h> |
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36 | |
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37 | /* set to max so we get early access to hose 0 */ |
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38 | unsigned BSP_pci_hose1_bus_base = (unsigned)-1; |
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39 | |
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40 | #define MV64x60_PCI0_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8) |
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41 | #define MV64x60_PCI0_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc) |
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42 | #define MV64x60_PCI1_CONFIG_ADDR (BSP_MV64x60_BASE + 0xc78) |
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43 | #define MV64x60_PCI1_CONFIG_DATA (BSP_MV64x60_BASE + 0xc7c) |
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44 | |
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45 | #define PCI_BUS2HOSE(bus) (bus<BSP_pci_hose1_bus_base?0:1) |
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46 | |
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47 | void detect_host_bridge(void) |
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48 | { |
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49 | |
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50 | } |
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51 | |
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52 | typedef struct { |
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53 | volatile unsigned char *pci_config_addr; |
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54 | volatile unsigned char *pci_config_data; |
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55 | } PciHoseCfg; |
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56 | |
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57 | static PciHoseCfg hoses[2] = { |
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58 | { |
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59 | pci_config_addr: (volatile unsigned char *)(MV64x60_PCI0_CONFIG_ADDR), |
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60 | pci_config_data: (volatile unsigned char *)(MV64x60_PCI0_CONFIG_DATA), |
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61 | }, |
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62 | { |
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63 | pci_config_addr: (volatile unsigned char *)(MV64x60_PCI1_CONFIG_ADDR), |
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64 | pci_config_data: (volatile unsigned char *)(MV64x60_PCI1_CONFIG_DATA), |
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65 | } |
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66 | }; |
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67 | |
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68 | #define pci hoses[hose] |
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69 | |
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70 | #define HOSE_PREAMBLE \ |
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71 | uint8_t hose; \ |
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72 | if (bus < BSP_pci_hose1_bus_base) { \ |
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73 | hose = 0; \ |
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74 | } else { \ |
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75 | hose = 1; \ |
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76 | bus -= BSP_pci_hose1_bus_base; \ |
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77 | } |
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78 | |
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79 | |
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80 | /* Sigh; we have to copy those out from the shared area... */ |
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81 | static int |
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82 | indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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83 | unsigned char function, |
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84 | unsigned char offset, uint8_t *val) { |
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85 | HOSE_PREAMBLE; |
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86 | out_be32((volatile uint32_t *) pci.pci_config_addr, |
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87 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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88 | *val = in_8(pci.pci_config_data + (offset&3)); |
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89 | return PCIBIOS_SUCCESSFUL; |
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90 | } |
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91 | |
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92 | static int |
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93 | indirect_pci_read_config_word(unsigned char bus, unsigned char slot, |
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94 | unsigned char function, |
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95 | unsigned char offset, uint16_t *val) { |
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96 | HOSE_PREAMBLE; |
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97 | *val = 0xffff; |
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98 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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99 | out_be32((uint32_t*) pci.pci_config_addr, |
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100 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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101 | *val = in_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3))); |
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102 | return PCIBIOS_SUCCESSFUL; |
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103 | } |
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104 | |
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105 | static int |
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106 | indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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107 | unsigned char function, |
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108 | unsigned char offset, uint32_t *val) { |
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109 | HOSE_PREAMBLE; |
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110 | *val = 0xffffffff; |
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111 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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112 | out_be32((uint32_t*) pci.pci_config_addr, |
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113 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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114 | *val = in_le32((volatile uint32_t *)pci.pci_config_data); |
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115 | return PCIBIOS_SUCCESSFUL; |
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116 | } |
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117 | |
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118 | static int |
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119 | indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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120 | unsigned char function, |
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121 | unsigned char offset, uint8_t val) { |
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122 | HOSE_PREAMBLE; |
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123 | out_be32((uint32_t*) pci.pci_config_addr, |
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124 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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125 | out_8(pci.pci_config_data + (offset&3), val); |
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126 | return PCIBIOS_SUCCESSFUL; |
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127 | } |
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128 | |
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129 | static int |
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130 | indirect_pci_write_config_word(unsigned char bus, unsigned char slot, |
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131 | unsigned char function, |
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132 | unsigned char offset, uint16_t val) { |
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133 | HOSE_PREAMBLE; |
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134 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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135 | out_be32((uint32_t*) pci.pci_config_addr, |
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136 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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137 | out_le16((volatile uint16_t *)(pci.pci_config_data + (offset&3)), val); |
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138 | return PCIBIOS_SUCCESSFUL; |
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139 | } |
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140 | |
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141 | static int |
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142 | indirect_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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143 | unsigned char function, |
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144 | unsigned char offset, uint32_t val) { |
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145 | HOSE_PREAMBLE; |
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146 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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147 | out_be32((uint32_t*) pci.pci_config_addr, |
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148 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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149 | out_le32((volatile uint32_t *)pci.pci_config_data, val); |
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150 | return PCIBIOS_SUCCESSFUL; |
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151 | } |
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152 | |
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153 | const pci_config_access_functions pci_hosed_indirect_functions = { |
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154 | indirect_pci_read_config_byte, |
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155 | indirect_pci_read_config_word, |
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156 | indirect_pci_read_config_dword, |
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157 | indirect_pci_write_config_byte, |
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158 | indirect_pci_write_config_word, |
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159 | indirect_pci_write_config_dword |
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160 | }; |
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161 | |
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162 | |
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163 | extern unsigned char ucMaxPCIBus; /* importing this is ugly */ |
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164 | |
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165 | /* This is a very ugly hack. I don't want to change the shared |
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166 | * code to support multiple hoses so we hide everything under |
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167 | * the hood with horrible kludges for now. Sorry. |
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168 | */ |
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169 | void |
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170 | BSP_pci_initialize(void) |
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171 | { |
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172 | |
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173 | #if 0 /* These values are already set up for the shared/pci.c code */ |
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174 | { |
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175 | extern pci_config_access_functions pci_indirect_functions; |
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176 | /* by means of the PCI_CONFIG_ADDR/PCI_CONFIG_DATA macros (bsp.h) */ |
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177 | BSP_pci_configuration.pci_config_addr = hoses[0].pci_config_addr; |
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178 | BSP_pci_configuration.pci_config_data = hoses[0].pci_config_data; |
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179 | BSP_pci_configuration.pci_functions = &pci_indirect_functions; |
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180 | } |
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181 | #endif |
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182 | /* initialize the first hose */ |
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183 | /* scan hose 0 and sets the maximum bus number */ |
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184 | pci_initialize(); |
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185 | /* remember the boundary */ |
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186 | BSP_pci_hose1_bus_base = pci_bus_count(); |
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187 | /* so far, so good -- now comes the cludgy part: */ |
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188 | /* hack/reset the bus count */ |
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189 | ucMaxPCIBus = 0; |
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190 | /* scan hose 1 */ |
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191 | BSP_pci_configuration.pci_config_addr = hoses[1].pci_config_addr; |
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192 | BSP_pci_configuration.pci_config_data = hoses[1].pci_config_data; |
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193 | pci_initialize(); |
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194 | /* check for overflow of an unsigned char */ |
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195 | if ( BSP_pci_hose1_bus_base + pci_bus_count() > 255 ) { |
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196 | rtems_panic("Too many PCI busses in the system"); |
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197 | } |
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198 | /* readjust total number */ |
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199 | ucMaxPCIBus+=BSP_pci_hose1_bus_base; |
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200 | |
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201 | /* install new access functions that can hide the hoses */ |
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202 | BSP_pci_configuration.pci_config_addr = (volatile unsigned char *)0xdeadbeef; |
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203 | BSP_pci_configuration.pci_config_data = (volatile unsigned char *)0xdeadbeef; |
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204 | BSP_pci_configuration.pci_functions = &pci_hosed_indirect_functions; |
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205 | } |
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206 | |
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207 | #define PCI_ERR_BITS 0xf900 |
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208 | #define PCI_STATUS_OK(x) (!((x)&PCI_ERR_BITS)) |
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209 | |
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210 | /* For now, just clear errors in the PCI status reg. |
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211 | * |
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212 | * Returns: (for diagnostic purposes) |
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213 | * original settings (i.e. before applying the clearing |
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214 | * sequence) |
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215 | * (pci_status(hose_1)&0xff00) | ((pci_status(hose_2)>>8)&0xff) |
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216 | */ |
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217 | |
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218 | static unsigned long clear_hose_errors(int bus, int quiet) |
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219 | { |
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220 | unsigned long rval; |
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221 | uint16_t pcistat; |
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222 | int count; |
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223 | int hose = PCI_BUS2HOSE(bus); |
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224 | |
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225 | /* read error status for info return */ |
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226 | pci_read_config_word(bus,0,0,PCI_STATUS,&pcistat); |
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227 | rval = pcistat; |
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228 | |
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229 | count=10; |
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230 | do { |
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231 | /* clear error reporting registers */ |
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232 | |
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233 | /* clear PCI status register */ |
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234 | pci_write_config_word(bus,0,0,PCI_STATUS, PCI_ERR_BITS); |
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235 | |
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236 | /* read new status */ |
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237 | pci_read_config_word(bus,0,0,PCI_STATUS, &pcistat); |
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238 | |
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239 | } while ( ! PCI_STATUS_OK(pcistat) && count-- ); |
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240 | |
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241 | if ( !PCI_STATUS_OK(rval) && !quiet) { |
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242 | printk("Cleared PCI errors at discovery (hose %i): pci_stat was 0x%04lx\n", hose, rval); |
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243 | } |
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244 | if ( !PCI_STATUS_OK(pcistat) ) { |
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245 | printk("Unable to clear PCI errors at discovery (hose %i) still 0x%04x after 10 attempts\n",hose, pcistat); |
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246 | } |
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247 | return rval; |
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248 | } |
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249 | |
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250 | unsigned short |
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251 | (*_BSP_clear_vmebridge_errors)(int) = 0; |
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252 | |
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253 | unsigned long |
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254 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
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255 | { |
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256 | unsigned long rval; |
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257 | |
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258 | /* MCP is not connected */ |
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259 | if ( enableMCP ) |
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260 | return -1; |
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261 | |
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262 | rval = (clear_hose_errors(0, quiet) & PCI_ERR_BITS)>>8; |
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263 | rval |= clear_hose_errors(BSP_pci_hose1_bus_base, quiet) & PCI_ERR_BITS; |
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264 | |
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265 | /* Tsi148 doesn't propagate VME bus errors to PCI status reg. */ |
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266 | if ( _BSP_clear_vmebridge_errors ) |
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267 | rval |= _BSP_clear_vmebridge_errors(quiet)<<16; |
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268 | |
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269 | return rval; |
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270 | } |
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