1 | #ifndef RTEMS_COMPAT_DEFS_H |
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2 | #define RTEMS_COMPAT_DEFS_H |
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3 | |
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4 | /* Symbol definitions for a particular driver */ |
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5 | |
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6 | /* Copyright: Till Straumann <strauman@slac.stanford.edu>, 2005; |
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7 | * License: see LICENSE file. |
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8 | */ |
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9 | |
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10 | /* Number of device instances the driver should support |
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11 | * - may be limited to 1 depending on IRQ API |
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12 | * (braindamaged PC586 and powerpc) |
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13 | */ |
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14 | #define NETDRIVER_SLOTS 1 |
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15 | /* String name to print with error messages */ |
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16 | #define NETDRIVER "PCN" |
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17 | /* Name snippet used to make global symbols unique to this driver */ |
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18 | #define NETDRIVER_PREFIX pcn |
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19 | |
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20 | /* Define according to endianness of the *ethernet*chip* |
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21 | * (not the CPU - most probably are LE) |
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22 | * This must be either NET_CHIP_LE or NET_CHIP_BE |
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23 | */ |
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24 | |
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25 | #define NET_CHIP_LE |
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26 | #undef NET_CHIP_BE |
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27 | |
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28 | /* Define either NET_CHIP_MEM_IO or NET_CHIP_PORT_IO, |
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29 | * depending whether the CPU sees it in memory address space |
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30 | * or (e.g. x86) uses special I/O instructions. |
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31 | */ |
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32 | #define NET_CHIP_MEM_IO |
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33 | #undef NET_CHIP_PORT_IO |
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34 | |
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35 | /* The name of the hijacked 'bus handle' field in the softc |
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36 | * structure. We use this field to store the chip's base address. |
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37 | */ |
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38 | #define NET_SOFTC_BHANDLE_FIELD pcn_bhandle |
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39 | |
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40 | /* define the names of the 'if_XXXreg.h' and 'if_XXXvar.h' headers |
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41 | * (only if present, i.e., if the BSDNET driver has no respective |
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42 | * header, leave this undefined). |
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43 | * |
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44 | */ |
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45 | #undef IF_REG_HEADER <if_XXXreg.h> |
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46 | #undef IF_VAR_HEADER <if_XXXvar.h> |
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47 | |
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48 | /* define if a pci device */ |
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49 | #define NETDRIVER_PCI <bsp/pci.h> |
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50 | |
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51 | /* Macros to disable and enable interrupts, respectively. |
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52 | * The 'disable' macro is expanded in the ISR, the 'enable' |
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53 | * macro is expanded in the driver task. |
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54 | * The global network semaphore usually provides mutex |
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55 | * protection of the device registers. |
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56 | * Special care must be taken when coding the 'disable' macro, |
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57 | * however to MAKE SURE THERE ARE NO OTHER SIDE EFFECTS such |
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58 | * as: |
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59 | * - macro must not clear any status flags |
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60 | * - macro must save/restore any context information |
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61 | * (e.g., a address register pointer or a bank switch register) |
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62 | * |
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63 | * ARGUMENT: the macro arg is a pointer to the driver's 'softc' structure |
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64 | */ |
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65 | |
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66 | /* Here EXAMPLES for the pcnet chip which addresses registers indirectly |
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67 | * through a 'address-pointer' (RAP) and 'data-port' (RDP) register pair: |
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68 | #define NET_DISABLE_IRQS(sc) do { \ |
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69 | unsigned rap = CSR_READ_4((sc),PCN_IO32_RAP); \ |
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70 | unsigned val; \ |
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71 | CSR_WRITE_4((sc),PCN_IO32_RAP,PCN_CSR_CSR); \ |
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72 | val = CSR_READ_4((sc),PCN_IO32_RDP); \ |
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73 | CSR_WRITE_4((sc), PCN_IO32_RDP, val & ~(CSR0_INT_STATUS_MASK | PCN_CSR_INTEN)); \ |
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74 | CSR_WRITE_4((sc), PCN_IO32_RAP, rap); \ |
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75 | } while (0) |
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76 | |
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77 | #define NET_ENABLE_IRQS(sc) do { \ |
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78 | unsigned flags,val; \ |
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79 | rtems_interrupt_disable(flags); \ |
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80 | CSR_WRITE_4((sc),PCN_IO32_RAP,PCN_CSR_CSR); \ |
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81 | val = CSR_READ_4((sc),PCN_IO32_RDP); \ |
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82 | CSR_WRITE_4((sc), PCN_IO32_RDP, (val & ~CSR0_INT_STATUS_MASK) | PCN_CSR_INTEN); \ |
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83 | rtems_interrupt_enable(flags); \ |
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84 | } while (0) |
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85 | */ |
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86 | |
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87 | /* Driver may provide a macro/function to copy the hardware address |
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88 | * from the device into 'softc.arpcom'. |
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89 | * If this is undefined, the driver must to the copy itself. |
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90 | * Preferrably, it should check soft.arpcom.ac_enaddr for all |
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91 | * zeros and leave it alone if it is nonzero, i.e., write it |
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92 | * to the hardware. |
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93 | #define NET_READ_MAC_ADDR(sc) |
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94 | */ |
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95 | |
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96 | #define KASSERT(a...) do {} while (0) |
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97 | #endif |
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