| 1 | /*- |
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| 2 | * Copyright (c) 1997, Stefan Esser <se@freebsd.org> |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice unmodified, this list of conditions, and the following |
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| 10 | * disclaimer. |
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| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * |
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| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 25 | * |
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| 26 | * $FreeBSD: /repoman/r/ncvs/src/sys/dev/pci/pcireg.h,v 1.39.4.3 2005/04/02 05:03:34 jmg Exp $ |
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| 27 | * |
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| 28 | */ |
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| 29 | |
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| 30 | /* |
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| 31 | * PCIM_xxx: mask to locate subfield in register |
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| 32 | * PCIR_xxx: config register offset |
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| 33 | * PCIC_xxx: device class |
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| 34 | * PCIS_xxx: device subclass |
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| 35 | * PCIP_xxx: device programming interface |
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| 36 | * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) |
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| 37 | * PCID_xxx: device ID |
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| 38 | * PCIY_xxx: capability identification number |
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| 39 | */ |
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| 40 | |
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| 41 | /* some PCI bus constants */ |
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| 42 | |
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| 43 | #define PCI_BUSMAX 255 |
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| 44 | #define PCI_SLOTMAX 31 |
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| 45 | #define PCI_FUNCMAX 7 |
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| 46 | #define PCI_REGMAX 255 |
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| 47 | #define PCI_MAXHDRTYPE 2 |
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| 48 | |
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| 49 | /* PCI config header registers for all devices */ |
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| 50 | |
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| 51 | #define PCIR_DEVVENDOR 0x00 |
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| 52 | #define PCIR_VENDOR 0x00 |
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| 53 | #define PCIR_DEVICE 0x02 |
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| 54 | #define PCIR_COMMAND 0x04 |
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| 55 | #define PCIM_CMD_PORTEN 0x0001 |
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| 56 | #define PCIM_CMD_MEMEN 0x0002 |
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| 57 | #define PCIM_CMD_BUSMASTEREN 0x0004 |
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| 58 | #define PCIM_CMD_SPECIALEN 0x0008 |
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| 59 | #define PCIM_CMD_MWRICEN 0x0010 |
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| 60 | #define PCIM_CMD_PERRESPEN 0x0040 |
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| 61 | #define PCIM_CMD_SERRESPEN 0x0100 |
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| 62 | #define PCIM_CMD_BACKTOBACK 0x0200 |
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| 63 | #define PCIR_STATUS 0x06 |
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| 64 | #define PCIM_STATUS_CAPPRESENT 0x0010 |
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| 65 | #define PCIM_STATUS_66CAPABLE 0x0020 |
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| 66 | #define PCIM_STATUS_BACKTOBACK 0x0080 |
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| 67 | #define PCIM_STATUS_PERRREPORT 0x0100 |
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| 68 | #define PCIM_STATUS_SEL_FAST 0x0000 |
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| 69 | #define PCIM_STATUS_SEL_MEDIMUM 0x0200 |
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| 70 | #define PCIM_STATUS_SEL_SLOW 0x0400 |
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| 71 | #define PCIM_STATUS_SEL_MASK 0x0600 |
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| 72 | #define PCIM_STATUS_STABORT 0x0800 |
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| 73 | #define PCIM_STATUS_RTABORT 0x1000 |
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| 74 | #define PCIM_STATUS_RMABORT 0x2000 |
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| 75 | #define PCIM_STATUS_SERR 0x4000 |
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| 76 | #define PCIM_STATUS_PERR 0x8000 |
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| 77 | #define PCIR_REVID 0x08 |
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| 78 | #define PCIR_PROGIF 0x09 |
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| 79 | #define PCIR_SUBCLASS 0x0a |
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| 80 | #define PCIR_CLASS 0x0b |
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| 81 | #define PCIR_CACHELNSZ 0x0c |
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| 82 | #define PCIR_LATTIMER 0x0d |
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| 83 | #define PCIR_HDRTYPE 0x0e |
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| 84 | #ifndef BURN_BRIDGES |
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| 85 | #define PCIR_HEADERTYPE PCIR_HDRTYPE |
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| 86 | #endif |
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| 87 | #define PCIM_HDRTYPE 0x7f |
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| 88 | #define PCIM_HDRTYPE_NORMAL 0x00 |
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| 89 | #define PCIM_HDRTYPE_BRIDGE 0x01 |
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| 90 | #define PCIM_HDRTYPE_CARDBUS 0x02 |
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| 91 | #define PCIM_MFDEV 0x80 |
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| 92 | #define PCIR_BIST 0x0f |
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| 93 | |
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| 94 | /* Capability Identification Numbers */ |
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| 95 | |
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| 96 | #define PCIY_PMG 0x01 /* PCI Power Management */ |
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| 97 | #define PCIY_AGP 0x02 /* AGP */ |
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| 98 | #define PCIY_VPD 0x03 /* Vital Product Data */ |
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| 99 | #define PCIY_SLOTID 0x04 /* Slot Identification */ |
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| 100 | #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ |
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| 101 | #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ |
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| 102 | #define PCIY_PCIX 0x07 /* PCI-X */ |
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| 103 | #define PCIY_HT 0x08 /* HyperTransport */ |
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| 104 | #define PCIY_VENDOR 0x09 /* Vendor Unique */ |
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| 105 | #define PCIY_DEBUG 0x0a /* Debug port */ |
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| 106 | #define PCIY_CRES 0x0b /* CompactPCI central resource control */ |
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| 107 | #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ |
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| 108 | #define PCIY_AGP8X 0x0e /* AGP 8x */ |
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| 109 | #define PCIY_SECDEV 0x0f /* Secure Device */ |
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| 110 | #define PCIY_EXPRESS 0x10 /* PCI Express */ |
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| 111 | #define PCIY_MSIX 0x11 /* MSI-X */ |
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| 112 | |
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| 113 | /* config registers for header type 0 devices */ |
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| 114 | |
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| 115 | #define PCIR_BARS 0x10 |
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| 116 | #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) |
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| 117 | #ifndef BURN_BRIDGES |
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| 118 | #define PCIR_MAPS PCIR_BARS |
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| 119 | #endif |
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| 120 | #define PCIR_CARDBUSCIS 0x28 |
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| 121 | #define PCIR_SUBVEND_0 0x2c |
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| 122 | #define PCIR_SUBDEV_0 0x2e |
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| 123 | #define PCIR_BIOS 0x30 |
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| 124 | #define PCIM_BIOS_ENABLE 0x01 |
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| 125 | #define PCIR_CAP_PTR 0x34 |
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| 126 | #define PCIR_INTLINE 0x3c |
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| 127 | #define PCIR_INTPIN 0x3d |
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| 128 | #define PCIR_MINGNT 0x3e |
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| 129 | #define PCIR_MAXLAT 0x3f |
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| 130 | |
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| 131 | /* config registers for header type 1 (PCI-to-PCI bridge) devices */ |
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| 132 | |
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| 133 | #define PCIR_SECSTAT_1 0x1e |
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| 134 | |
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| 135 | #define PCIR_PRIBUS_1 0x18 |
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| 136 | #define PCIR_SECBUS_1 0x19 |
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| 137 | #define PCIR_SUBBUS_1 0x1a |
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| 138 | #define PCIR_SECLAT_1 0x1b |
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| 139 | |
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| 140 | #define PCIR_IOBASEL_1 0x1c |
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| 141 | #define PCIR_IOLIMITL_1 0x1d |
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| 142 | #define PCIR_IOBASEH_1 0x30 |
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| 143 | #define PCIR_IOLIMITH_1 0x32 |
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| 144 | #define PCIM_BRIO_16 0x0 |
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| 145 | #define PCIM_BRIO_32 0x1 |
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| 146 | #define PCIM_BRIO_MASK 0xf |
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| 147 | |
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| 148 | #define PCIR_MEMBASE_1 0x20 |
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| 149 | #define PCIR_MEMLIMIT_1 0x22 |
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| 150 | |
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| 151 | #define PCIR_PMBASEL_1 0x24 |
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| 152 | #define PCIR_PMLIMITL_1 0x26 |
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| 153 | #define PCIR_PMBASEH_1 0x28 |
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| 154 | #define PCIR_PMLIMITH_1 0x2c |
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| 155 | |
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| 156 | #define PCIR_BRIDGECTL_1 0x3e |
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| 157 | |
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| 158 | #define PCIR_SUBVEND_1 0x34 |
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| 159 | #define PCIR_SUBDEV_1 0x36 |
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| 160 | |
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| 161 | /* config registers for header type 2 (CardBus) devices */ |
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| 162 | |
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| 163 | #define PCIR_SECSTAT_2 0x16 |
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| 164 | |
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| 165 | #define PCIR_PRIBUS_2 0x18 |
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| 166 | #define PCIR_SECBUS_2 0x19 |
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| 167 | #define PCIR_SUBBUS_2 0x1a |
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| 168 | #define PCIR_SECLAT_2 0x1b |
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| 169 | |
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| 170 | #define PCIR_MEMBASE0_2 0x1c |
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| 171 | #define PCIR_MEMLIMIT0_2 0x20 |
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| 172 | #define PCIR_MEMBASE1_2 0x24 |
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| 173 | #define PCIR_MEMLIMIT1_2 0x28 |
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| 174 | #define PCIR_IOBASE0_2 0x2c |
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| 175 | #define PCIR_IOLIMIT0_2 0x30 |
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| 176 | #define PCIR_IOBASE1_2 0x34 |
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| 177 | #define PCIR_IOLIMIT1_2 0x38 |
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| 178 | |
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| 179 | #define PCIR_BRIDGECTL_2 0x3e |
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| 180 | |
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| 181 | #define PCIR_SUBVEND_2 0x40 |
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| 182 | #define PCIR_SUBDEV_2 0x42 |
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| 183 | |
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| 184 | #define PCIR_PCCARDIF_2 0x44 |
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| 185 | |
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| 186 | /* PCI device class, subclass and programming interface definitions */ |
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| 187 | |
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| 188 | #define PCIC_OLD 0x00 |
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| 189 | #define PCIS_OLD_NONVGA 0x00 |
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| 190 | #define PCIS_OLD_VGA 0x01 |
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| 191 | |
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| 192 | #define PCIC_STORAGE 0x01 |
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| 193 | #define PCIS_STORAGE_SCSI 0x00 |
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| 194 | #define PCIS_STORAGE_IDE 0x01 |
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| 195 | #define PCIP_STORAGE_IDE_MODEPRIM 0x01 |
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| 196 | #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 |
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| 197 | #define PCIP_STORAGE_IDE_MODESEC 0x04 |
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| 198 | #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 |
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| 199 | #define PCIP_STORAGE_IDE_MASTERDEV 0x80 |
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| 200 | #define PCIS_STORAGE_FLOPPY 0x02 |
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| 201 | #define PCIS_STORAGE_IPI 0x03 |
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| 202 | #define PCIS_STORAGE_RAID 0x04 |
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| 203 | #define PCIS_STORAGE_OTHER 0x80 |
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| 204 | |
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| 205 | #define PCIC_NETWORK 0x02 |
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| 206 | #define PCIS_NETWORK_ETHERNET 0x00 |
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| 207 | #define PCIS_NETWORK_TOKENRING 0x01 |
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| 208 | #define PCIS_NETWORK_FDDI 0x02 |
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| 209 | #define PCIS_NETWORK_ATM 0x03 |
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| 210 | #define PCIS_NETWORK_ISDN 0x04 |
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| 211 | #define PCIS_NETWORK_OTHER 0x80 |
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| 212 | |
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| 213 | #define PCIC_DISPLAY 0x03 |
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| 214 | #define PCIS_DISPLAY_VGA 0x00 |
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| 215 | #define PCIS_DISPLAY_XGA 0x01 |
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| 216 | #define PCIS_DISPLAY_3D 0x02 |
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| 217 | #define PCIS_DISPLAY_OTHER 0x80 |
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| 218 | |
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| 219 | #define PCIC_MULTIMEDIA 0x04 |
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| 220 | #define PCIS_MULTIMEDIA_VIDEO 0x00 |
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| 221 | #define PCIS_MULTIMEDIA_AUDIO 0x01 |
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| 222 | #define PCIS_MULTIMEDIA_TELE 0x02 |
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| 223 | #define PCIS_MULTIMEDIA_OTHER 0x80 |
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| 224 | |
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| 225 | #define PCIC_MEMORY 0x05 |
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| 226 | #define PCIS_MEMORY_RAM 0x00 |
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| 227 | #define PCIS_MEMORY_FLASH 0x01 |
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| 228 | #define PCIS_MEMORY_OTHER 0x80 |
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| 229 | |
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| 230 | #define PCIC_BRIDGE 0x06 |
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| 231 | #define PCIS_BRIDGE_HOST 0x00 |
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| 232 | #define PCIS_BRIDGE_ISA 0x01 |
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| 233 | #define PCIS_BRIDGE_EISA 0x02 |
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| 234 | #define PCIS_BRIDGE_MCA 0x03 |
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| 235 | #define PCIS_BRIDGE_PCI 0x04 |
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| 236 | #define PCIS_BRIDGE_PCMCIA 0x05 |
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| 237 | #define PCIS_BRIDGE_NUBUS 0x06 |
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| 238 | #define PCIS_BRIDGE_CARDBUS 0x07 |
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| 239 | #define PCIS_BRIDGE_RACEWAY 0x08 |
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| 240 | #define PCIS_BRIDGE_OTHER 0x80 |
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| 241 | |
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| 242 | #define PCIC_SIMPLECOMM 0x07 |
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| 243 | #define PCIS_SIMPLECOMM_UART 0x00 |
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| 244 | #define PCIP_SIMPLECOMM_UART_16550A 0x02 |
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| 245 | #define PCIS_SIMPLECOMM_PAR 0x01 |
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| 246 | #define PCIS_SIMPLECOMM_MULSER 0x02 |
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| 247 | #define PCIS_SIMPLECOMM_MODEM 0x03 |
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| 248 | #define PCIS_SIMPLECOMM_OTHER 0x80 |
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| 249 | |
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| 250 | #define PCIC_BASEPERIPH 0x08 |
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| 251 | #define PCIS_BASEPERIPH_PIC 0x00 |
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| 252 | #define PCIS_BASEPERIPH_DMA 0x01 |
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| 253 | #define PCIS_BASEPERIPH_TIMER 0x02 |
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| 254 | #define PCIS_BASEPERIPH_RTC 0x03 |
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| 255 | #define PCIS_BASEPERIPH_PCIHOT 0x04 |
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| 256 | #define PCIS_BASEPERIPH_OTHER 0x80 |
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| 257 | |
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| 258 | #define PCIC_INPUTDEV 0x09 |
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| 259 | #define PCIS_INPUTDEV_KEYBOARD 0x00 |
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| 260 | #define PCIS_INPUTDEV_DIGITIZER 0x01 |
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| 261 | #define PCIS_INPUTDEV_MOUSE 0x02 |
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| 262 | #define PCIS_INPUTDEV_SCANNER 0x03 |
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| 263 | #define PCIS_INPUTDEV_GAMEPORT 0x04 |
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| 264 | #define PCIS_INPUTDEV_OTHER 0x80 |
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| 265 | |
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| 266 | #define PCIC_DOCKING 0x0a |
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| 267 | #define PCIS_DOCKING_GENERIC 0x00 |
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| 268 | #define PCIS_DOCKING_OTHER 0x80 |
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| 269 | |
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| 270 | #define PCIC_PROCESSOR 0x0b |
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| 271 | #define PCIS_PROCESSOR_386 0x00 |
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| 272 | #define PCIS_PROCESSOR_486 0x01 |
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| 273 | #define PCIS_PROCESSOR_PENTIUM 0x02 |
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| 274 | #define PCIS_PROCESSOR_ALPHA 0x10 |
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| 275 | #define PCIS_PROCESSOR_POWERPC 0x20 |
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| 276 | #define PCIS_PROCESSOR_MIPS 0x30 |
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| 277 | #define PCIS_PROCESSOR_COPROC 0x40 |
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| 278 | |
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| 279 | #define PCIC_SERIALBUS 0x0c |
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| 280 | #define PCIS_SERIALBUS_FW 0x00 |
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| 281 | #define PCIS_SERIALBUS_ACCESS 0x01 |
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| 282 | #define PCIS_SERIALBUS_SSA 0x02 |
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| 283 | #define PCIS_SERIALBUS_USB 0x03 |
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| 284 | #define PCIP_SERIALBUS_USB_UHCI 0x00 |
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| 285 | #define PCIP_SERIALBUS_USB_OHCI 0x10 |
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| 286 | #define PCIP_SERIALBUS_USB_EHCI 0x20 |
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| 287 | #define PCIS_SERIALBUS_FC 0x04 |
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| 288 | #define PCIS_SERIALBUS_SMBUS 0x05 |
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| 289 | |
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| 290 | #define PCIC_WIRELESS 0x0d |
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| 291 | #define PCIS_WIRELESS_IRDA 0x00 |
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| 292 | #define PCIS_WIRELESS_IR 0x01 |
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| 293 | #define PCIS_WIRELESS_RF 0x10 |
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| 294 | #define PCIS_WIRELESS_OTHER 0x80 |
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| 295 | |
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| 296 | #define PCIC_INTELLIIO 0x0e |
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| 297 | #define PCIS_INTELLIIO_I2O 0x00 |
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| 298 | |
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| 299 | #define PCIC_SATCOM 0x0f |
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| 300 | #define PCIS_SATCOM_TV 0x01 |
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| 301 | #define PCIS_SATCOM_AUDIO 0x02 |
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| 302 | #define PCIS_SATCOM_VOICE 0x03 |
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| 303 | #define PCIS_SATCOM_DATA 0x04 |
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| 304 | |
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| 305 | #define PCIC_CRYPTO 0x10 |
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| 306 | #define PCIS_CRYPTO_NETCOMP 0x00 |
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| 307 | #define PCIS_CRYPTO_ENTERTAIN 0x10 |
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| 308 | #define PCIS_CRYPTO_OTHER 0x80 |
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| 309 | |
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| 310 | #define PCIC_DASP 0x11 |
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| 311 | #define PCIS_DASP_DPIO 0x00 |
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| 312 | #define PCIS_DASP_OTHER 0x80 |
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| 313 | |
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| 314 | #define PCIC_OTHER 0xff |
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| 315 | |
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| 316 | /* PCI power manangement */ |
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| 317 | |
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| 318 | #define PCIR_POWER_CAP 0x2 |
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| 319 | #define PCIM_PCAP_SPEC 0x0007 |
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| 320 | #define PCIM_PCAP_PMEREQCLK 0x0008 |
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| 321 | #define PCIM_PCAP_PMEREQPWR 0x0010 |
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| 322 | #define PCIM_PCAP_DEVSPECINIT 0x0020 |
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| 323 | #define PCIM_PCAP_DYNCLOCK 0x0040 |
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| 324 | #define PCIM_PCAP_SECCLOCK 0x00c0 |
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| 325 | #define PCIM_PCAP_CLOCKMASK 0x00c0 |
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| 326 | #define PCIM_PCAP_REQFULLCLOCK 0x0100 |
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| 327 | #define PCIM_PCAP_D1SUPP 0x0200 |
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| 328 | #define PCIM_PCAP_D2SUPP 0x0400 |
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| 329 | #define PCIM_PCAP_D0PME 0x1000 |
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| 330 | #define PCIM_PCAP_D1PME 0x2000 |
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| 331 | #define PCIM_PCAP_D2PME 0x4000 |
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| 332 | |
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| 333 | #define PCIR_POWER_STATUS 0x4 |
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| 334 | #define PCIM_PSTAT_D0 0x0000 |
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| 335 | #define PCIM_PSTAT_D1 0x0001 |
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| 336 | #define PCIM_PSTAT_D2 0x0002 |
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| 337 | #define PCIM_PSTAT_D3 0x0003 |
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| 338 | #define PCIM_PSTAT_DMASK 0x0003 |
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| 339 | #define PCIM_PSTAT_REPENABLE 0x0010 |
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| 340 | #define PCIM_PSTAT_PMEENABLE 0x0100 |
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| 341 | #define PCIM_PSTAT_D0POWER 0x0000 |
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| 342 | #define PCIM_PSTAT_D1POWER 0x0200 |
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| 343 | #define PCIM_PSTAT_D2POWER 0x0400 |
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| 344 | #define PCIM_PSTAT_D3POWER 0x0600 |
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| 345 | #define PCIM_PSTAT_D0HEAT 0x0800 |
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| 346 | #define PCIM_PSTAT_D1HEAT 0x1000 |
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| 347 | #define PCIM_PSTAT_D2HEAT 0x1200 |
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| 348 | #define PCIM_PSTAT_D3HEAT 0x1400 |
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| 349 | #define PCIM_PSTAT_DATAUNKN 0x0000 |
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| 350 | #define PCIM_PSTAT_DATADIV10 0x2000 |
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| 351 | #define PCIM_PSTAT_DATADIV100 0x4000 |
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| 352 | #define PCIM_PSTAT_DATADIV1000 0x6000 |
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| 353 | #define PCIM_PSTAT_DATADIVMASK 0x6000 |
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| 354 | #define PCIM_PSTAT_PME 0x8000 |
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| 355 | |
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| 356 | #define PCIR_POWER_PMCSR 0x6 |
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| 357 | #define PCIM_PMCSR_DCLOCK 0x10 |
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| 358 | #define PCIM_PMCSR_B2SUPP 0x20 |
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| 359 | #define PCIM_BMCSR_B3SUPP 0x40 |
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| 360 | #define PCIM_BMCSR_BPCE 0x80 |
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| 361 | |
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| 362 | #define PCIR_POWER_DATA 0x7 |
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| 363 | |
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| 364 | /* PCI Message Signalled Interrupts (MSI) */ |
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| 365 | #define PCIR_MSI_CTRL 0x2 |
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| 366 | #define PCIM_MSICTRL_VECTOR 0x0100 |
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| 367 | #define PCIM_MSICTRL_64BIT 0x0080 |
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| 368 | #define PCIM_MSICTRL_MME_MASK 0x0070 |
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| 369 | #define PCIM_MSICTRL_MME_1 0x0000 |
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| 370 | #define PCIM_MSICTRL_MME_2 0x0010 |
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| 371 | #define PCIM_MSICTRL_MME_4 0x0020 |
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| 372 | #define PCIM_MSICTRL_MME_8 0x0030 |
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| 373 | #define PCIM_MSICTRL_MME_16 0x0040 |
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| 374 | #define PCIM_MSICTRL_MME_32 0x0050 |
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| 375 | #define PCIM_MSICTRL_MMC_MASK 0x000E |
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| 376 | #define PCIM_MSICTRL_MMC_1 0x0000 |
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| 377 | #define PCIM_MSICTRL_MMC_2 0x0002 |
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| 378 | #define PCIM_MSICTRL_MMC_4 0x0004 |
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| 379 | #define PCIM_MSICTRL_MMC_8 0x0006 |
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| 380 | #define PCIM_MSICTRL_MMC_16 0x0008 |
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| 381 | #define PCIM_MSICTRL_MMC_32 0x000A |
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| 382 | #define PCIM_MSICTRL_MSI_ENABLE 0x0001 |
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| 383 | #define PCIR_MSI_ADDR 0x4 |
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| 384 | #define PCIR_MSI_ADDR_HIGH 0x8 |
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| 385 | #define PCIR_MSI_DATA 0x8 |
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| 386 | #define PCIR_MSI_DATA_64BIT 0xc |
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| 387 | #define PCIR_MSI_MASK 0x10 |
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| 388 | #define PCIR_MSI_PENDING 0x14 |
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| 389 | |
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| 390 | /* PCI-X definitions */ |
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| 391 | #define PCIXR_COMMAND 0x96 |
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| 392 | #define PCIXR_DEVADDR 0x98 |
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| 393 | #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ |
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| 394 | #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ |
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| 395 | #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ |
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| 396 | #define PCIXR_STATUS 0x9A |
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| 397 | #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ |
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| 398 | #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ |
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| 399 | #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ |
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| 400 | #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ |
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| 401 | #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ |
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| 402 | #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ |
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| 403 | #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ |
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| 404 | #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ |
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| 405 | #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ |
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