source: rtems/bsps/powerpc/beatnik/net/if_em/if_em_hw.c @ efdb4a7

5
Last change on this file since efdb4a7 was efdb4a7, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 9, 2018 at 8:37:53 AM

bsp/beatnik: Fix warnings

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File size: 221.3 KB
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1/*******************************************************************************
2
3  Copyright (c) 2001-2005, Intel Corporation
4  All rights reserved.
5 
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8 
9   1. Redistributions of source code must retain the above copyright notice,
10      this list of conditions and the following disclaimer.
11 
12   2. Redistributions in binary form must reproduce the above copyright
13      notice, this list of conditions and the following disclaimer in the
14      documentation and/or other materials provided with the distribution.
15 
16   3. Neither the name of the Intel Corporation nor the names of its
17      contributors may be used to endorse or promote products derived from
18      this software without specific prior written permission.
19 
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33
34/* if_em_hw.c
35 * Shared functions for accessing and configuring the MAC
36 */
37
38#include <sys/cdefs.h>
39#ifdef __rtems__
40#include "rtemscompat_defs.h"
41#include "../porting/rtemscompat.h"
42#include "if_em_hw.h"
43#else
44__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/em/if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $");
45
46#include <dev/em/if_em_hw.h>
47#endif
48
49static int32_t em_set_phy_type(struct em_hw *hw);
50static void em_phy_init_script(struct em_hw *hw);
51static int32_t em_setup_copper_link(struct em_hw *hw);
52static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
53static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
54static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
55static int32_t em_config_mac_to_phy(struct em_hw *hw);
56static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
57static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
58static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
59                                     uint16_t count);
60static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
61static int32_t em_phy_reset_dsp(struct em_hw *hw);
62static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
63                                      uint16_t words, uint16_t *data);
64static int32_t em_write_eeprom_microwire(struct em_hw *hw,
65                                            uint16_t offset, uint16_t words,
66                                            uint16_t *data);
67static int32_t em_spi_eeprom_ready(struct em_hw *hw);
68static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
69static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
70static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
71                                    uint16_t count);
72static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
73                                      uint16_t phy_data);
74static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
75                                     uint16_t *phy_data);
76static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
77static int32_t em_acquire_eeprom(struct em_hw *hw);
78static void em_release_eeprom(struct em_hw *hw);
79static void em_standby_eeprom(struct em_hw *hw);
80static int32_t em_set_vco_speed(struct em_hw *hw);
81static int32_t em_polarity_reversal_workaround(struct em_hw *hw);
82static int32_t em_set_phy_mode(struct em_hw *hw);
83static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer);
84static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length);
85
86/* IGP cable length table */
87static const
88uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
89    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
90      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
91      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
92      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
93      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
94      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
95      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
96      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
97
98/******************************************************************************
99 * Set the phy type member in the hw struct.
100 *
101 * hw - Struct containing variables accessed by shared code
102 *****************************************************************************/
103int32_t
104em_set_phy_type(struct em_hw *hw)
105{
106    DEBUGFUNC("em_set_phy_type");
107
108    if(hw->mac_type == em_undefined)
109        return -E1000_ERR_PHY_TYPE;
110
111    switch(hw->phy_id) {
112    case M88E1000_E_PHY_ID:
113    case M88E1000_I_PHY_ID:
114    case M88E1011_I_PHY_ID:
115    case M88E1111_I_PHY_ID:
116        hw->phy_type = em_phy_m88;
117        break;
118    case IGP01E1000_I_PHY_ID:
119        if(hw->mac_type == em_82541 ||
120           hw->mac_type == em_82541_rev_2 ||
121           hw->mac_type == em_82547 ||
122           hw->mac_type == em_82547_rev_2) {
123            hw->phy_type = em_phy_igp;
124            break;
125        }
126        /* Fall Through */
127    default:
128        /* Should never have loaded on this device */
129        hw->phy_type = em_phy_undefined;
130        return -E1000_ERR_PHY_TYPE;
131    }
132
133    return E1000_SUCCESS;
134}
135
136/******************************************************************************
137 * IGP phy init script - initializes the GbE PHY
138 *
139 * hw - Struct containing variables accessed by shared code
140 *****************************************************************************/
141static void
142em_phy_init_script(struct em_hw *hw)
143{
144    uint16_t phy_saved_data;
145
146    DEBUGFUNC("em_phy_init_script");
147
148    if(hw->phy_init_script) {
149        msec_delay(20);
150
151        /* Save off the current value of register 0x2F5B to be restored at
152         * the end of this routine. */
153        em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
154
155        /* Disabled the PHY transmitter */
156        em_write_phy_reg(hw, 0x2F5B, 0x0003);
157
158        msec_delay(20);
159
160        em_write_phy_reg(hw,0x0000,0x0140);
161
162        msec_delay(5);
163
164        switch(hw->mac_type) {
165        case em_82541:
166        case em_82547:
167            em_write_phy_reg(hw, 0x1F95, 0x0001);
168
169            em_write_phy_reg(hw, 0x1F71, 0xBD21);
170
171            em_write_phy_reg(hw, 0x1F79, 0x0018);
172
173            em_write_phy_reg(hw, 0x1F30, 0x1600);
174
175            em_write_phy_reg(hw, 0x1F31, 0x0014);
176
177            em_write_phy_reg(hw, 0x1F32, 0x161C);
178
179            em_write_phy_reg(hw, 0x1F94, 0x0003);
180
181            em_write_phy_reg(hw, 0x1F96, 0x003F);
182
183            em_write_phy_reg(hw, 0x2010, 0x0008);
184            break;
185
186        case em_82541_rev_2:
187        case em_82547_rev_2:
188            em_write_phy_reg(hw, 0x1F73, 0x0099);
189            break;
190        default:
191            break;
192        }
193
194        em_write_phy_reg(hw, 0x0000, 0x3300);
195
196        msec_delay(20);
197
198        /* Now enable the transmitter */
199        em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
200
201        if(hw->mac_type == em_82547) {
202            uint16_t fused, fine, coarse;
203
204            /* Move to analog registers page */
205            em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
206
207            if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
208                em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
209
210                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
211                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
212
213                if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
214                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
215                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
216                } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
217                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
218
219                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
220                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
221                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
222
223                em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
224                em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
225                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
226            }
227        }
228    }
229}
230
231/******************************************************************************
232 * Set the mac type member in the hw struct.
233 *
234 * hw - Struct containing variables accessed by shared code
235 *****************************************************************************/
236int32_t
237em_set_mac_type(struct em_hw *hw)
238{
239    DEBUGFUNC("em_set_mac_type");
240
241    switch (hw->device_id) {
242    case E1000_DEV_ID_82542:
243        switch (hw->revision_id) {
244        case E1000_82542_2_0_REV_ID:
245            hw->mac_type = em_82542_rev2_0;
246            break;
247        case E1000_82542_2_1_REV_ID:
248            hw->mac_type = em_82542_rev2_1;
249            break;
250        default:
251            /* Invalid 82542 revision ID */
252            return -E1000_ERR_MAC_TYPE;
253        }
254        break;
255    case E1000_DEV_ID_82543GC_FIBER:
256    case E1000_DEV_ID_82543GC_COPPER:
257        hw->mac_type = em_82543;
258        break;
259    case E1000_DEV_ID_82544EI_COPPER:
260    case E1000_DEV_ID_82544EI_FIBER:
261    case E1000_DEV_ID_82544GC_COPPER:
262    case E1000_DEV_ID_82544GC_LOM:
263        hw->mac_type = em_82544;
264        break;
265    case E1000_DEV_ID_82540EM:
266    case E1000_DEV_ID_82540EM_LOM:
267    case E1000_DEV_ID_82540EP:
268    case E1000_DEV_ID_82540EP_LOM:
269    case E1000_DEV_ID_82540EP_LP:
270        hw->mac_type = em_82540;
271        break;
272    case E1000_DEV_ID_82545EM_COPPER:
273    case E1000_DEV_ID_82545EM_FIBER:
274        hw->mac_type = em_82545;
275        break;
276    case E1000_DEV_ID_82545GM_COPPER:
277    case E1000_DEV_ID_82545GM_FIBER:
278    case E1000_DEV_ID_82545GM_SERDES:
279        hw->mac_type = em_82545_rev_3;
280        break;
281    case E1000_DEV_ID_82546EB_COPPER:
282    case E1000_DEV_ID_82546EB_FIBER:
283    case E1000_DEV_ID_82546EB_QUAD_COPPER:
284        hw->mac_type = em_82546;
285        break;
286    case E1000_DEV_ID_82546GB_COPPER:
287    case E1000_DEV_ID_82546GB_FIBER:
288    case E1000_DEV_ID_82546GB_SERDES:
289    case E1000_DEV_ID_82546GB_PCIE:
290    case E1000_DEV_ID_82546GB_QUAD_COPPER:
291        hw->mac_type = em_82546_rev_3;
292        break;
293    case E1000_DEV_ID_82541EI:
294    case E1000_DEV_ID_82541ER_LOM:
295    case E1000_DEV_ID_82541EI_MOBILE:
296        hw->mac_type = em_82541;
297        break;
298    case E1000_DEV_ID_82541ER:
299    case E1000_DEV_ID_82541GI:
300    case E1000_DEV_ID_82541GI_LF:
301    case E1000_DEV_ID_82541GI_MOBILE:
302        hw->mac_type = em_82541_rev_2;
303        break;
304    case E1000_DEV_ID_82547EI:
305    case E1000_DEV_ID_82547EI_MOBILE:
306        hw->mac_type = em_82547;
307        break;
308    case E1000_DEV_ID_82547GI:
309        hw->mac_type = em_82547_rev_2;
310        break;
311    case E1000_DEV_ID_82573E:
312    case E1000_DEV_ID_82573E_IAMT:
313        hw->mac_type = em_82573;
314        break;
315    default:
316        /* Should never have loaded on this device */
317        return -E1000_ERR_MAC_TYPE;
318    }
319
320    switch(hw->mac_type) {
321    case em_82573:
322        hw->eeprom_semaphore_present = TRUE;
323        /* fall through */
324    case em_82541:
325    case em_82547:
326    case em_82541_rev_2:
327    case em_82547_rev_2:
328        hw->asf_firmware_present = TRUE;
329        break;
330    default:
331        break;
332    }
333
334    return E1000_SUCCESS;
335}
336
337/*****************************************************************************
338 * Set media type and TBI compatibility.
339 *
340 * hw - Struct containing variables accessed by shared code
341 * **************************************************************************/
342void
343em_set_media_type(struct em_hw *hw)
344{
345    uint32_t status;
346
347    DEBUGFUNC("em_set_media_type");
348
349    if(hw->mac_type != em_82543) {
350        /* tbi_compatibility is only valid on 82543 */
351        hw->tbi_compatibility_en = FALSE;
352    }
353
354    switch (hw->device_id) {
355    case E1000_DEV_ID_82545GM_SERDES:
356    case E1000_DEV_ID_82546GB_SERDES:
357        hw->media_type = em_media_type_internal_serdes;
358        break;
359    default:
360        if(hw->mac_type >= em_82543) {
361            status = E1000_READ_REG(hw, STATUS);
362            if(status & E1000_STATUS_TBIMODE) {
363                hw->media_type = em_media_type_fiber;
364                /* tbi_compatibility not valid on fiber */
365                hw->tbi_compatibility_en = FALSE;
366            } else {
367                hw->media_type = em_media_type_copper;
368            }
369        } else {
370            /* This is an 82542 (fiber only) */
371            hw->media_type = em_media_type_fiber;
372        }
373    }
374}
375
376/******************************************************************************
377 * Reset the transmit and receive units; mask and clear all interrupts.
378 *
379 * hw - Struct containing variables accessed by shared code
380 *****************************************************************************/
381int32_t
382em_reset_hw(struct em_hw *hw)
383{
384    uint32_t ctrl;
385    uint32_t ctrl_ext;
386    uint32_t manc;
387    uint32_t led_ctrl;
388    uint32_t timeout;
389    uint32_t extcnf_ctrl;
390    int32_t ret_val;
391
392    DEBUGFUNC("em_reset_hw");
393
394    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
395    if(hw->mac_type == em_82542_rev2_0) {
396        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
397        em_pci_clear_mwi(hw);
398    }
399
400    if(hw->bus_type == em_bus_type_pci_express) {
401        /* Prevent the PCI-E bus from sticking if there is no TLP connection
402         * on the last TLP read/write transaction when MAC is reset.
403         */
404        if(em_disable_pciex_master(hw) != E1000_SUCCESS) {
405            DEBUGOUT("PCI-E Master disable polling has failed.\n");
406        }
407    }
408
409    /* Clear interrupt mask to stop board from generating interrupts */
410    DEBUGOUT("Masking off all interrupts\n");
411    E1000_WRITE_REG(hw, IMC, 0xffffffff);
412
413    /* Disable the Transmit and Receive units.  Then delay to allow
414     * any pending transactions to complete before we hit the MAC with
415     * the global reset.
416     */
417    E1000_WRITE_REG(hw, RCTL, 0);
418    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
419    E1000_WRITE_FLUSH(hw);
420
421    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
422    hw->tbi_compatibility_on = FALSE;
423
424    /* Delay to allow any outstanding PCI transactions to complete before
425     * resetting the device
426     */
427    msec_delay(10);
428
429    ctrl = E1000_READ_REG(hw, CTRL);
430
431    /* Must reset the PHY before resetting the MAC */
432    if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
433        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
434        msec_delay(5);
435    }
436
437    /* Must acquire the MDIO ownership before MAC reset.
438     * Ownership defaults to firmware after a reset. */
439    if(hw->mac_type == em_82573) {
440        timeout = 10;
441
442        extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
443        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
444
445        do {
446            E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
447            extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
448
449            if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
450                break;
451            else
452                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
453
454            msec_delay(2);
455            timeout--;
456        } while(timeout);
457    }
458
459    /* Issue a global reset to the MAC.  This will reset the chip's
460     * transmit, receive, DMA, and link units.  It will not effect
461     * the current PCI configuration.  The global reset bit is self-
462     * clearing, and should clear within a microsecond.
463     */
464    DEBUGOUT("Issuing a global reset to MAC\n");
465
466    switch(hw->mac_type) {
467        case em_82544:
468        case em_82540:
469        case em_82545:
470#ifndef __arm__
471        case em_82546:
472#endif
473        case em_82541:
474        case em_82541_rev_2:
475            /* These controllers can't ack the 64-bit write when issuing the
476             * reset, so use IO-mapping as a workaround to issue the reset */
477            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
478            break;
479        case em_82545_rev_3:
480        case em_82546_rev_3:
481            /* Reset is performed on a shadow of the control register */
482            E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
483            break;
484        default:
485            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
486            break;
487    }
488
489    /* After MAC reset, force reload of EEPROM to restore power-on settings to
490     * device.  Later controllers reload the EEPROM automatically, so just wait
491     * for reload to complete.
492     */
493    switch(hw->mac_type) {
494        case em_82542_rev2_0:
495        case em_82542_rev2_1:
496        case em_82543:
497        case em_82544:
498            /* Wait for reset to complete */
499            usec_delay(10);
500            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
501            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
502            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
503            E1000_WRITE_FLUSH(hw);
504            /* Wait for EEPROM reload */
505            msec_delay(2);
506            break;
507        case em_82541:
508        case em_82541_rev_2:
509        case em_82547:
510        case em_82547_rev_2:
511            /* Wait for EEPROM reload */
512            msec_delay(20);
513            break;
514        case em_82573:
515            usec_delay(10);
516            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
517            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
518            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
519            E1000_WRITE_FLUSH(hw);
520            /* fall through */
521            ret_val = em_get_auto_rd_done(hw);
522            if(ret_val)
523                /* We don't want to continue accessing MAC registers. */
524                return ret_val;
525            break;
526        default:
527            /* Wait for EEPROM reload (it happens automatically) */
528            msec_delay(5);
529            break;
530    }
531
532    /* Disable HW ARPs on ASF enabled adapters */
533    if(hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) {
534        manc = E1000_READ_REG(hw, MANC);
535        manc &= ~(E1000_MANC_ARP_EN);
536        E1000_WRITE_REG(hw, MANC, manc);
537    }
538
539    if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
540        em_phy_init_script(hw);
541
542        /* Configure activity LED after PHY reset */
543        led_ctrl = E1000_READ_REG(hw, LEDCTL);
544        led_ctrl &= IGP_ACTIVITY_LED_MASK;
545        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
546        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
547    }
548
549    /* Clear interrupt mask to stop board from generating interrupts */
550    DEBUGOUT("Masking off all interrupts\n");
551    E1000_WRITE_REG(hw, IMC, 0xffffffff);
552
553    /* Clear any pending interrupt events. */
554    E1000_READ_REG(hw, ICR);
555
556    /* If MWI was previously enabled, reenable it. */
557    if(hw->mac_type == em_82542_rev2_0) {
558        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
559            em_pci_set_mwi(hw);
560    }
561#ifdef __rtems__
562        msec_delay(100);
563#endif
564
565    return E1000_SUCCESS;
566}
567
568/******************************************************************************
569 * Performs basic configuration of the adapter.
570 *
571 * hw - Struct containing variables accessed by shared code
572 *
573 * Assumes that the controller has previously been reset and is in a
574 * post-reset uninitialized state. Initializes the receive address registers,
575 * multicast table, and VLAN filter table. Calls routines to setup link
576 * configuration and flow control settings. Clears all on-chip counters. Leaves
577 * the transmit and receive units disabled and uninitialized.
578 *****************************************************************************/
579int32_t
580em_init_hw(struct em_hw *hw)
581{
582    uint32_t ctrl;
583    uint32_t i;
584    int32_t ret_val;
585    uint16_t pcix_cmd_word;
586    uint16_t pcix_stat_hi_word;
587    uint16_t cmd_mmrbc;
588    uint16_t stat_mmrbc;
589    uint32_t mta_size;
590
591    DEBUGFUNC("em_init_hw");
592
593    /* Initialize Identification LED */
594    ret_val = em_id_led_init(hw);
595    if(ret_val) {
596        DEBUGOUT("Error Initializing Identification LED\n");
597        return ret_val;
598    }
599
600    /* Set the media type and TBI compatibility */
601    em_set_media_type(hw);
602
603    /* Disabling VLAN filtering. */
604    DEBUGOUT("Initializing the IEEE VLAN\n");
605    if (hw->mac_type < em_82545_rev_3)
606        E1000_WRITE_REG(hw, VET, 0);
607    em_clear_vfta(hw);
608
609    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
610    if(hw->mac_type == em_82542_rev2_0) {
611        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
612        em_pci_clear_mwi(hw);
613        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
614        E1000_WRITE_FLUSH(hw);
615        msec_delay(5);
616    }
617
618    /* Setup the receive address. This involves initializing all of the Receive
619     * Address Registers (RARs 0 - 15).
620     */
621    em_init_rx_addrs(hw);
622
623    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
624    if(hw->mac_type == em_82542_rev2_0) {
625        E1000_WRITE_REG(hw, RCTL, 0);
626        E1000_WRITE_FLUSH(hw);
627        msec_delay(1);
628        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
629            em_pci_set_mwi(hw);
630    }
631
632    /* Zero out the Multicast HASH table */
633    DEBUGOUT("Zeroing the MTA\n");
634    mta_size = E1000_MC_TBL_SIZE;
635    for(i = 0; i < mta_size; i++)
636        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
637
638    /* Set the PCI priority bit correctly in the CTRL register.  This
639     * determines if the adapter gives priority to receives, or if it
640     * gives equal priority to transmits and receives.  Valid only on
641     * 82542 and 82543 silicon.
642     */
643    if(hw->dma_fairness && hw->mac_type <= em_82543) {
644        ctrl = E1000_READ_REG(hw, CTRL);
645        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
646    }
647
648    switch(hw->mac_type) {
649    case em_82545_rev_3:
650    case em_82546_rev_3:
651        break;
652    default:
653        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
654        if(hw->bus_type == em_bus_type_pcix) {
655            em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
656            em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
657                &pcix_stat_hi_word);
658            cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
659                PCIX_COMMAND_MMRBC_SHIFT;
660            stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
661                PCIX_STATUS_HI_MMRBC_SHIFT;
662            if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
663                stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
664            if(cmd_mmrbc > stat_mmrbc) {
665                pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
666                pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
667                em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
668                    &pcix_cmd_word);
669            }
670        }
671        break;
672    }
673
674    /* Call a subroutine to configure the link and setup flow control. */
675    ret_val = em_setup_link(hw);
676
677    /* Set the transmit descriptor write-back policy */
678    if(hw->mac_type > em_82544) {
679        ctrl = E1000_READ_REG(hw, TXDCTL);
680        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
681        switch (hw->mac_type) {
682        default:
683            break;
684        case em_82573:
685            ctrl |= E1000_TXDCTL_COUNT_DESC;
686            break;
687        }
688        E1000_WRITE_REG(hw, TXDCTL, ctrl);
689    }
690
691    if (hw->mac_type == em_82573) {
692        em_enable_tx_pkt_filtering(hw); 
693    }
694
695
696    /* Clear all of the statistics registers (clear on read).  It is
697     * important that we do this after we have tried to establish link
698     * because the symbol error count will increment wildly if there
699     * is no link.
700     */
701    em_clear_hw_cntrs(hw);
702
703    return ret_val;
704}
705
706/******************************************************************************
707 * Adjust SERDES output amplitude based on EEPROM setting.
708 *
709 * hw - Struct containing variables accessed by shared code.
710 *****************************************************************************/
711static int32_t
712em_adjust_serdes_amplitude(struct em_hw *hw)
713{
714    uint16_t eeprom_data;
715    int32_t  ret_val;
716
717    DEBUGFUNC("em_adjust_serdes_amplitude");
718
719    if(hw->media_type != em_media_type_internal_serdes)
720        return E1000_SUCCESS;
721
722    switch(hw->mac_type) {
723    case em_82545_rev_3:
724    case em_82546_rev_3:
725        break;
726    default:
727        return E1000_SUCCESS;
728    }
729
730    ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
731    if (ret_val) {
732        return ret_val;
733    }
734
735    if(eeprom_data != EEPROM_RESERVED_WORD) {
736        /* Adjust SERDES output amplitude only. */
737        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 
738        ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
739        if(ret_val)
740            return ret_val;
741    }
742
743    return E1000_SUCCESS;
744}
745
746/******************************************************************************
747 * Configures flow control and link settings.
748 *
749 * hw - Struct containing variables accessed by shared code
750 *
751 * Determines which flow control settings to use. Calls the apropriate media-
752 * specific link configuration function. Configures the flow control settings.
753 * Assuming the adapter has a valid link partner, a valid link should be
754 * established. Assumes the hardware has previously been reset and the
755 * transmitter and receiver are not enabled.
756 *****************************************************************************/
757int32_t
758em_setup_link(struct em_hw *hw)
759{
760    uint32_t ctrl_ext;
761    int32_t ret_val;
762    uint16_t eeprom_data;
763
764    DEBUGFUNC("em_setup_link");
765
766    /* Read and store word 0x0F of the EEPROM. This word contains bits
767     * that determine the hardware's default PAUSE (flow control) mode,
768     * a bit that determines whether the HW defaults to enabling or
769     * disabling auto-negotiation, and the direction of the
770     * SW defined pins. If there is no SW over-ride of the flow
771     * control setting, then the variable hw->fc will
772     * be initialized based on a value in the EEPROM.
773     */
774    if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
775        DEBUGOUT("EEPROM Read Error\n");
776        return -E1000_ERR_EEPROM;
777    }
778
779    if(hw->fc == em_fc_default) {
780        if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
781            hw->fc = em_fc_none;
782        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
783                EEPROM_WORD0F_ASM_DIR)
784            hw->fc = em_fc_tx_pause;
785        else
786            hw->fc = em_fc_full;
787    }
788
789    /* We want to save off the original Flow Control configuration just
790     * in case we get disconnected and then reconnected into a different
791     * hub or switch with different Flow Control capabilities.
792     */
793    if(hw->mac_type == em_82542_rev2_0)
794        hw->fc &= (~em_fc_tx_pause);
795
796    if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
797        hw->fc &= (~em_fc_rx_pause);
798
799    hw->original_fc = hw->fc;
800
801    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
802
803    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
804     * polarity value for the SW controlled pins, and setup the
805     * Extended Device Control reg with that info.
806     * This is needed because one of the SW controlled pins is used for
807     * signal detection.  So this should be done before em_setup_pcs_link()
808     * or em_phy_setup() is called.
809     */
810    if(hw->mac_type == em_82543) {
811        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
812                    SWDPIO__EXT_SHIFT);
813        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
814    }
815
816    /* Call the necessary subroutine to configure the link. */
817    ret_val = (hw->media_type == em_media_type_copper) ?
818              em_setup_copper_link(hw) :
819              em_setup_fiber_serdes_link(hw);
820
821    /* Initialize the flow control address, type, and PAUSE timer
822     * registers to their default values.  This is done even if flow
823     * control is disabled, because it does not hurt anything to
824     * initialize these registers.
825     */
826    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
827
828    E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
829    E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
830    E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
831
832    E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
833
834    /* Set the flow control receive threshold registers.  Normally,
835     * these registers will be set to a default threshold that may be
836     * adjusted later by the driver's runtime code.  However, if the
837     * ability to transmit pause frames in not enabled, then these
838     * registers will be set to 0.
839     */
840    if(!(hw->fc & em_fc_tx_pause)) {
841        E1000_WRITE_REG(hw, FCRTL, 0);
842        E1000_WRITE_REG(hw, FCRTH, 0);
843    } else {
844        /* We need to set up the Receive Threshold high and low water marks
845         * as well as (optionally) enabling the transmission of XON frames.
846         */
847        if(hw->fc_send_xon) {
848            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
849            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
850        } else {
851            E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
852            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
853        }
854    }
855    return ret_val;
856}
857
858/******************************************************************************
859 * Sets up link for a fiber based or serdes based adapter
860 *
861 * hw - Struct containing variables accessed by shared code
862 *
863 * Manipulates Physical Coding Sublayer functions in order to configure
864 * link. Assumes the hardware has been previously reset and the transmitter
865 * and receiver are not enabled.
866 *****************************************************************************/
867static int32_t
868em_setup_fiber_serdes_link(struct em_hw *hw)
869{
870    uint32_t ctrl;
871    uint32_t status;
872    uint32_t txcw = 0;
873    uint32_t i;
874    uint32_t signal = 0;
875    int32_t ret_val;
876
877    DEBUGFUNC("em_setup_fiber_serdes_link");
878
879    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
880     * set when the optics detect a signal. On older adapters, it will be
881     * cleared when there is a signal.  This applies to fiber media only.
882     * If we're on serdes media, adjust the output amplitude to value set in
883     * the EEPROM.
884     */
885    ctrl = E1000_READ_REG(hw, CTRL);
886    if(hw->media_type == em_media_type_fiber)
887        signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
888
889    ret_val = em_adjust_serdes_amplitude(hw);
890    if(ret_val)
891        return ret_val;
892
893    /* Take the link out of reset */
894    ctrl &= ~(E1000_CTRL_LRST);
895
896    /* Adjust VCO speed to improve BER performance */
897    ret_val = em_set_vco_speed(hw);
898    if(ret_val)
899        return ret_val;
900
901    em_config_collision_dist(hw);
902
903    /* Check for a software override of the flow control settings, and setup
904     * the device accordingly.  If auto-negotiation is enabled, then software
905     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
906     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
907     * auto-negotiation is disabled, then software will have to manually
908     * configure the two flow control enable bits in the CTRL register.
909     *
910     * The possible values of the "fc" parameter are:
911     *      0:  Flow control is completely disabled
912     *      1:  Rx flow control is enabled (we can receive pause frames, but
913     *          not send pause frames).
914     *      2:  Tx flow control is enabled (we can send pause frames but we do
915     *          not support receiving pause frames).
916     *      3:  Both Rx and TX flow control (symmetric) are enabled.
917     */
918    switch (hw->fc) {
919    case em_fc_none:
920        /* Flow control is completely disabled by a software over-ride. */
921        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
922        break;
923    case em_fc_rx_pause:
924        /* RX Flow control is enabled and TX Flow control is disabled by a
925         * software over-ride. Since there really isn't a way to advertise
926         * that we are capable of RX Pause ONLY, we will advertise that we
927         * support both symmetric and asymmetric RX PAUSE. Later, we will
928         *  disable the adapter's ability to send PAUSE frames.
929         */
930        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
931        break;
932    case em_fc_tx_pause:
933        /* TX Flow control is enabled, and RX Flow control is disabled, by a
934         * software over-ride.
935         */
936        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
937        break;
938    case em_fc_full:
939        /* Flow control (both RX and TX) is enabled by a software over-ride. */
940        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
941        break;
942    default:
943        DEBUGOUT("Flow control param set incorrectly\n");
944        return -E1000_ERR_CONFIG;
945        break;
946    }
947
948    /* Since auto-negotiation is enabled, take the link out of reset (the link
949     * will be in reset, because we previously reset the chip). This will
950     * restart auto-negotiation.  If auto-neogtiation is successful then the
951     * link-up status bit will be set and the flow control enable bits (RFCE
952     * and TFCE) will be set according to their negotiated value.
953     */
954    DEBUGOUT("Auto-negotiation enabled\n");
955
956    E1000_WRITE_REG(hw, TXCW, txcw);
957    E1000_WRITE_REG(hw, CTRL, ctrl);
958    E1000_WRITE_FLUSH(hw);
959
960    hw->txcw = txcw;
961    msec_delay(1);
962
963    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
964     * indication in the Device Status Register.  Time-out if a link isn't
965     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
966     * less than 500 milliseconds even if the other end is doing it in SW).
967     * For internal serdes, we just assume a signal is present, then poll.
968     */
969    if(hw->media_type == em_media_type_internal_serdes ||
970       (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
971        DEBUGOUT("Looking for Link\n");
972        for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
973            msec_delay(10);
974            status = E1000_READ_REG(hw, STATUS);
975            if(status & E1000_STATUS_LU) break;
976        }
977        if(i == (LINK_UP_TIMEOUT / 10)) {
978            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
979            hw->autoneg_failed = 1;
980            /* AutoNeg failed to achieve a link, so we'll call
981             * em_check_for_link. This routine will force the link up if
982             * we detect a signal. This will allow us to communicate with
983             * non-autonegotiating link partners.
984             */
985            ret_val = em_check_for_link(hw);
986            if(ret_val) {
987                DEBUGOUT("Error while checking for link\n");
988                return ret_val;
989            }
990            hw->autoneg_failed = 0;
991        } else {
992            hw->autoneg_failed = 0;
993            DEBUGOUT("Valid Link Found\n");
994        }
995    } else {
996        DEBUGOUT("No Signal Detected\n");
997    }
998    return E1000_SUCCESS;
999}
1000
1001/******************************************************************************
1002* Make sure we have a valid PHY and change PHY mode before link setup.
1003*
1004* hw - Struct containing variables accessed by shared code
1005******************************************************************************/
1006static int32_t
1007em_copper_link_preconfig(struct em_hw *hw)
1008{
1009    uint32_t ctrl;
1010    int32_t ret_val;
1011    uint16_t phy_data;
1012
1013    DEBUGFUNC("em_copper_link_preconfig");
1014
1015    ctrl = E1000_READ_REG(hw, CTRL);
1016    /* With 82543, we need to force speed and duplex on the MAC equal to what
1017     * the PHY speed and duplex configuration is. In addition, we need to
1018     * perform a hardware reset on the PHY to take it out of reset.
1019     */
1020    if(hw->mac_type > em_82543) {
1021        ctrl |= E1000_CTRL_SLU;
1022        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1023        E1000_WRITE_REG(hw, CTRL, ctrl);
1024    } else {
1025        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1026        E1000_WRITE_REG(hw, CTRL, ctrl);
1027        ret_val = em_phy_hw_reset(hw);
1028        if(ret_val)
1029            return ret_val;
1030    }
1031
1032    /* Make sure we have a valid PHY */
1033    ret_val = em_detect_gig_phy(hw);
1034    if(ret_val) {
1035        DEBUGOUT("Error, did not detect valid phy.\n");
1036        return ret_val;
1037    }
1038    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1039
1040    /* Set PHY to class A mode (if necessary) */
1041    ret_val = em_set_phy_mode(hw);
1042    if(ret_val)
1043        return ret_val;
1044
1045    if((hw->mac_type == em_82545_rev_3) ||
1046       (hw->mac_type == em_82546_rev_3)) {
1047        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1048        phy_data |= 0x00000008;
1049        ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1050    }
1051
1052    if(hw->mac_type <= em_82543 ||
1053       hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
1054       hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
1055        hw->phy_reset_disable = FALSE;
1056
1057   return E1000_SUCCESS;
1058}
1059
1060
1061/********************************************************************
1062* Copper link setup for em_phy_igp series.
1063*
1064* hw - Struct containing variables accessed by shared code
1065*********************************************************************/
1066static int32_t
1067em_copper_link_igp_setup(struct em_hw *hw)
1068{
1069    uint32_t led_ctrl;
1070    int32_t ret_val;
1071    uint16_t phy_data;
1072
1073    DEBUGFUNC("em_copper_link_igp_setup");
1074
1075    if (hw->phy_reset_disable)
1076        return E1000_SUCCESS;
1077   
1078    ret_val = em_phy_reset(hw);
1079    if (ret_val) {
1080        DEBUGOUT("Error Resetting the PHY\n");
1081        return ret_val;
1082    }
1083
1084    /* Wait 10ms for MAC to configure PHY from eeprom settings */
1085    msec_delay(15);
1086
1087    /* Configure activity LED after PHY reset */
1088    led_ctrl = E1000_READ_REG(hw, LEDCTL);
1089    led_ctrl &= IGP_ACTIVITY_LED_MASK;
1090    led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1091    E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1092
1093    /* disable lplu d3 during driver init */
1094    ret_val = em_set_d3_lplu_state(hw, FALSE);
1095    if (ret_val) {
1096        DEBUGOUT("Error Disabling LPLU D3\n");
1097        return ret_val;
1098    }
1099
1100    /* disable lplu d0 during driver init */
1101    ret_val = em_set_d0_lplu_state(hw, FALSE);
1102    if (ret_val) {
1103        DEBUGOUT("Error Disabling LPLU D0\n");
1104        return ret_val;
1105    }
1106    /* Configure mdi-mdix settings */
1107    ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1108    if (ret_val)
1109        return ret_val;
1110
1111    if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1112        hw->dsp_config_state = em_dsp_config_disabled;
1113        /* Force MDI for earlier revs of the IGP PHY */
1114        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1115        hw->mdix = 1;
1116
1117    } else {
1118        hw->dsp_config_state = em_dsp_config_enabled;
1119        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1120
1121        switch (hw->mdix) {
1122        case 1:
1123            phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1124            break;
1125        case 2:
1126            phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1127            break;
1128        case 0:
1129        default:
1130            phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1131            break;
1132        }
1133    }
1134    ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1135    if(ret_val)
1136        return ret_val;
1137
1138    /* set auto-master slave resolution settings */
1139    if(hw->autoneg) {
1140        em_ms_type phy_ms_setting = hw->master_slave;
1141
1142        if(hw->ffe_config_state == em_ffe_config_active)
1143            hw->ffe_config_state = em_ffe_config_enabled;
1144
1145        if(hw->dsp_config_state == em_dsp_config_activated)
1146            hw->dsp_config_state = em_dsp_config_enabled;
1147
1148        /* when autonegotiation advertisment is only 1000Mbps then we
1149          * should disable SmartSpeed and enable Auto MasterSlave
1150          * resolution as hardware default. */
1151        if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1152            /* Disable SmartSpeed */
1153            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1154            if(ret_val)
1155                return ret_val;
1156            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1157            ret_val = em_write_phy_reg(hw,
1158                                                  IGP01E1000_PHY_PORT_CONFIG,
1159                                                  phy_data);
1160            if(ret_val)
1161                return ret_val;
1162            /* Set auto Master/Slave resolution process */
1163            ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1164            if(ret_val)
1165                return ret_val;
1166            phy_data &= ~CR_1000T_MS_ENABLE;
1167            ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1168            if(ret_val)
1169                return ret_val;
1170        }
1171
1172        ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1173        if(ret_val)
1174            return ret_val;
1175
1176        /* load defaults for future use */
1177        hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1178                                        ((phy_data & CR_1000T_MS_VALUE) ?
1179                                         em_ms_force_master :
1180                                         em_ms_force_slave) :
1181                                         em_ms_auto;
1182
1183        switch (phy_ms_setting) {
1184        case em_ms_force_master:
1185            phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1186            break;
1187        case em_ms_force_slave:
1188            phy_data |= CR_1000T_MS_ENABLE;
1189            phy_data &= ~(CR_1000T_MS_VALUE);
1190            break;
1191        case em_ms_auto:
1192            phy_data &= ~CR_1000T_MS_ENABLE;
1193            default:
1194            break;
1195        }
1196        ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1197        if(ret_val)
1198            return ret_val;
1199        }
1200
1201   return E1000_SUCCESS;
1202}
1203
1204
1205/********************************************************************
1206* Copper link setup for em_phy_m88 series.
1207*
1208* hw - Struct containing variables accessed by shared code
1209*********************************************************************/
1210static int32_t
1211em_copper_link_mgp_setup(struct em_hw *hw)
1212{
1213    int32_t ret_val;
1214    uint16_t phy_data;
1215
1216    DEBUGFUNC("em_copper_link_mgp_setup");
1217
1218    if(hw->phy_reset_disable)
1219        return E1000_SUCCESS;
1220   
1221    /* Enable CRS on TX. This must be set for half-duplex operation. */
1222    ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1223    if(ret_val)
1224        return ret_val;
1225
1226    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1227
1228    /* Options:
1229     *   MDI/MDI-X = 0 (default)
1230     *   0 - Auto for all speeds
1231     *   1 - MDI mode
1232     *   2 - MDI-X mode
1233     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1234     */
1235    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1236
1237    switch (hw->mdix) {
1238    case 1:
1239        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1240        break;
1241    case 2:
1242        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1243        break;
1244    case 3:
1245        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1246        break;
1247    case 0:
1248    default:
1249        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1250        break;
1251    }
1252
1253    /* Options:
1254     *   disable_polarity_correction = 0 (default)
1255     *       Automatic Correction for Reversed Cable Polarity
1256     *   0 - Disabled
1257     *   1 - Enabled
1258     */
1259    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1260    if(hw->disable_polarity_correction == 1)
1261        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1262    ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1263    if(ret_val)
1264        return ret_val;
1265
1266    /* Force TX_CLK in the Extended PHY Specific Control Register
1267     * to 25MHz clock.
1268     */
1269    ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1270    if(ret_val)
1271        return ret_val;
1272
1273    phy_data |= M88E1000_EPSCR_TX_CLK_25;
1274
1275    if (hw->phy_revision < M88E1011_I_REV_4) {
1276        /* Configure Master and Slave downshift values */
1277        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1278                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1279        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1280                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1281        ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1282        if(ret_val)
1283            return ret_val;
1284    }
1285
1286    /* SW Reset the PHY so all changes take effect */
1287    ret_val = em_phy_reset(hw);
1288    if(ret_val) {
1289        DEBUGOUT("Error Resetting the PHY\n");
1290        return ret_val;
1291    }
1292
1293   return E1000_SUCCESS;
1294}
1295
1296/********************************************************************
1297* Setup auto-negotiation and flow control advertisements,
1298* and then perform auto-negotiation.
1299*
1300* hw - Struct containing variables accessed by shared code
1301*********************************************************************/
1302static int32_t
1303em_copper_link_autoneg(struct em_hw *hw)
1304{
1305    int32_t ret_val;
1306    uint16_t phy_data;
1307
1308    DEBUGFUNC("em_copper_link_autoneg");
1309
1310    /* Perform some bounds checking on the hw->autoneg_advertised
1311     * parameter.  If this variable is zero, then set it to the default.
1312     */
1313    hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1314
1315    /* If autoneg_advertised is zero, we assume it was not defaulted
1316     * by the calling code so we set to advertise full capability.
1317     */
1318    if(hw->autoneg_advertised == 0)
1319        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1320
1321    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1322    ret_val = em_phy_setup_autoneg(hw);
1323    if(ret_val) {
1324        DEBUGOUT("Error Setting up Auto-Negotiation\n");
1325        return ret_val;
1326    }
1327    DEBUGOUT("Restarting Auto-Neg\n");
1328
1329    /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1330     * the Auto Neg Restart bit in the PHY control register.
1331     */
1332    ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
1333    if(ret_val)
1334        return ret_val;
1335
1336    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1337    ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
1338    if(ret_val)
1339        return ret_val;
1340
1341    /* Does the user want to wait for Auto-Neg to complete here, or
1342     * check at a later time (for example, callback routine).
1343     */
1344    if(hw->wait_autoneg_complete) {
1345        ret_val = em_wait_autoneg(hw);
1346        if(ret_val) {
1347            DEBUGOUT("Error while waiting for autoneg to complete\n");
1348            return ret_val;
1349        }
1350    }
1351
1352    hw->get_link_status = TRUE;
1353
1354    return E1000_SUCCESS;
1355}
1356
1357
1358/******************************************************************************
1359* Config the MAC and the PHY after link is up.
1360*   1) Set up the MAC to the current PHY speed/duplex
1361*      if we are on 82543.  If we
1362*      are on newer silicon, we only need to configure
1363*      collision distance in the Transmit Control Register.
1364*   2) Set up flow control on the MAC to that established with
1365*      the link partner.
1366*   3) Config DSP to improve Gigabit link quality for some PHY revisions.   
1367*
1368* hw - Struct containing variables accessed by shared code
1369******************************************************************************/
1370static int32_t
1371em_copper_link_postconfig(struct em_hw *hw)
1372{
1373    int32_t ret_val;
1374    DEBUGFUNC("em_copper_link_postconfig");
1375   
1376    if(hw->mac_type >= em_82544) {
1377        em_config_collision_dist(hw);
1378    } else {
1379        ret_val = em_config_mac_to_phy(hw);
1380        if(ret_val) {
1381            DEBUGOUT("Error configuring MAC to PHY settings\n");
1382            return ret_val;
1383        }
1384    }
1385    ret_val = em_config_fc_after_link_up(hw);
1386    if(ret_val) {
1387        DEBUGOUT("Error Configuring Flow Control\n");
1388        return ret_val;
1389    }
1390
1391    /* Config DSP to improve Giga link quality */
1392    if(hw->phy_type == em_phy_igp) {
1393        ret_val = em_config_dsp_after_link_change(hw, TRUE);
1394        if(ret_val) {
1395            DEBUGOUT("Error Configuring DSP after link up\n");
1396            return ret_val;
1397        }
1398    }
1399               
1400    return E1000_SUCCESS;
1401}
1402
1403/******************************************************************************
1404* Detects which PHY is present and setup the speed and duplex
1405*
1406* hw - Struct containing variables accessed by shared code
1407******************************************************************************/
1408static int32_t
1409em_setup_copper_link(struct em_hw *hw)
1410{
1411    int32_t ret_val;
1412    uint16_t i;
1413    uint16_t phy_data;
1414
1415    DEBUGFUNC("em_setup_copper_link");
1416
1417    /* Check if it is a valid PHY and set PHY mode if necessary. */
1418    ret_val = em_copper_link_preconfig(hw);
1419    if(ret_val)
1420        return ret_val;
1421
1422    if (hw->phy_type == em_phy_igp ||
1423        hw->phy_type == em_phy_igp_2) {
1424        ret_val = em_copper_link_igp_setup(hw);
1425        if(ret_val)
1426            return ret_val;
1427    } else if (hw->phy_type == em_phy_m88) {
1428        ret_val = em_copper_link_mgp_setup(hw);
1429        if(ret_val)
1430            return ret_val;
1431    }
1432
1433    if(hw->autoneg) {
1434        /* Setup autoneg and flow control advertisement
1435          * and perform autonegotiation */   
1436        ret_val = em_copper_link_autoneg(hw);
1437        if(ret_val)
1438            return ret_val;           
1439    } else {
1440        /* PHY will be set to 10H, 10F, 100H,or 100F
1441          * depending on value from forced_speed_duplex. */
1442        DEBUGOUT("Forcing speed and duplex\n");
1443        ret_val = em_phy_force_speed_duplex(hw);
1444        if(ret_val) {
1445            DEBUGOUT("Error Forcing Speed and Duplex\n");
1446            return ret_val;
1447        }
1448    }
1449
1450    /* Check link status. Wait up to 100 microseconds for link to become
1451     * valid.
1452     */
1453    for(i = 0; i < 10; i++) {
1454        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
1455        if(ret_val)
1456            return ret_val;
1457        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
1458        if(ret_val)
1459            return ret_val;
1460
1461        if(phy_data & MII_SR_LINK_STATUS) {
1462            /* Config the MAC and PHY after link is up */
1463            ret_val = em_copper_link_postconfig(hw);
1464            if(ret_val)
1465                return ret_val;
1466           
1467            DEBUGOUT("Valid link established!!!\n");
1468            return E1000_SUCCESS;
1469        }
1470        usec_delay(10);
1471    }
1472
1473    DEBUGOUT("Unable to establish link!!!\n");
1474    return E1000_SUCCESS;
1475}
1476
1477/******************************************************************************
1478* Configures PHY autoneg and flow control advertisement settings
1479*
1480* hw - Struct containing variables accessed by shared code
1481******************************************************************************/
1482int32_t
1483em_phy_setup_autoneg(struct em_hw *hw)
1484{
1485    int32_t ret_val;
1486    uint16_t mii_autoneg_adv_reg;
1487    uint16_t mii_1000t_ctrl_reg;
1488
1489    DEBUGFUNC("em_phy_setup_autoneg");
1490
1491    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1492    ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1493    if(ret_val)
1494        return ret_val;
1495
1496    /* Read the MII 1000Base-T Control Register (Address 9). */
1497    ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1498    if(ret_val)
1499        return ret_val;
1500
1501    /* Need to parse both autoneg_advertised and fc and set up
1502     * the appropriate PHY registers.  First we will parse for
1503     * autoneg_advertised software override.  Since we can advertise
1504     * a plethora of combinations, we need to check each bit
1505     * individually.
1506     */
1507
1508    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1509     * Advertisement Register (Address 4) and the 1000 mb speed bits in
1510     * the  1000Base-T Control Register (Address 9).
1511     */
1512    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1513    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1514
1515    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1516
1517    /* Do we want to advertise 10 Mb Half Duplex? */
1518    if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1519        DEBUGOUT("Advertise 10mb Half duplex\n");
1520        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1521    }
1522
1523    /* Do we want to advertise 10 Mb Full Duplex? */
1524    if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1525        DEBUGOUT("Advertise 10mb Full duplex\n");
1526        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1527    }
1528
1529    /* Do we want to advertise 100 Mb Half Duplex? */
1530    if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1531        DEBUGOUT("Advertise 100mb Half duplex\n");
1532        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1533    }
1534
1535    /* Do we want to advertise 100 Mb Full Duplex? */
1536    if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1537        DEBUGOUT("Advertise 100mb Full duplex\n");
1538        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1539    }
1540
1541    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1542    if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1543        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1544    }
1545
1546    /* Do we want to advertise 1000 Mb Full Duplex? */
1547    if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1548        DEBUGOUT("Advertise 1000mb Full duplex\n");
1549        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1550    }
1551
1552    /* Check for a software override of the flow control settings, and
1553     * setup the PHY advertisement registers accordingly.  If
1554     * auto-negotiation is enabled, then software will have to set the
1555     * "PAUSE" bits to the correct value in the Auto-Negotiation
1556     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1557     *
1558     * The possible values of the "fc" parameter are:
1559     *      0:  Flow control is completely disabled
1560     *      1:  Rx flow control is enabled (we can receive pause frames
1561     *          but not send pause frames).
1562     *      2:  Tx flow control is enabled (we can send pause frames
1563     *          but we do not support receiving pause frames).
1564     *      3:  Both Rx and TX flow control (symmetric) are enabled.
1565     *  other:  No software override.  The flow control configuration
1566     *          in the EEPROM is used.
1567     */
1568    switch (hw->fc) {
1569    case em_fc_none: /* 0 */
1570        /* Flow control (RX & TX) is completely disabled by a
1571         * software over-ride.
1572         */
1573        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1574        break;
1575    case em_fc_rx_pause: /* 1 */
1576        /* RX Flow control is enabled, and TX Flow control is
1577         * disabled, by a software over-ride.
1578         */
1579        /* Since there really isn't a way to advertise that we are
1580         * capable of RX Pause ONLY, we will advertise that we
1581         * support both symmetric and asymmetric RX PAUSE.  Later
1582         * (in em_config_fc_after_link_up) we will disable the
1583         *hw's ability to send PAUSE frames.
1584         */
1585        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1586        break;
1587    case em_fc_tx_pause: /* 2 */
1588        /* TX Flow control is enabled, and RX Flow control is
1589         * disabled, by a software over-ride.
1590         */
1591        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1592        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1593        break;
1594    case em_fc_full: /* 3 */
1595        /* Flow control (both RX and TX) is enabled by a software
1596         * over-ride.
1597         */
1598        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1599        break;
1600    default:
1601        DEBUGOUT("Flow control param set incorrectly\n");
1602        return -E1000_ERR_CONFIG;
1603    }
1604
1605    ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1606    if(ret_val)
1607        return ret_val;
1608
1609    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1610
1611    ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);   
1612    if(ret_val)
1613        return ret_val;
1614
1615    return E1000_SUCCESS;
1616}
1617
1618/******************************************************************************
1619* Force PHY speed and duplex settings to hw->forced_speed_duplex
1620*
1621* hw - Struct containing variables accessed by shared code
1622******************************************************************************/
1623static int32_t
1624em_phy_force_speed_duplex(struct em_hw *hw)
1625{
1626    uint32_t ctrl;
1627    int32_t ret_val;
1628    uint16_t mii_ctrl_reg;
1629    uint16_t mii_status_reg;
1630    uint16_t phy_data;
1631    uint16_t i;
1632
1633    DEBUGFUNC("em_phy_force_speed_duplex");
1634
1635    /* Turn off Flow control if we are forcing speed and duplex. */
1636    hw->fc = em_fc_none;
1637
1638    DEBUGOUT1("hw->fc = %d\n", hw->fc);
1639
1640    /* Read the Device Control Register. */
1641    ctrl = E1000_READ_REG(hw, CTRL);
1642
1643    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1644    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1645    ctrl &= ~(DEVICE_SPEED_MASK);
1646
1647    /* Clear the Auto Speed Detect Enable bit. */
1648    ctrl &= ~E1000_CTRL_ASDE;
1649
1650    /* Read the MII Control Register. */
1651    ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1652    if(ret_val)
1653        return ret_val;
1654
1655    /* We need to disable autoneg in order to force link and duplex. */
1656
1657    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1658
1659    /* Are we forcing Full or Half Duplex? */
1660    if(hw->forced_speed_duplex == em_100_full ||
1661       hw->forced_speed_duplex == em_10_full) {
1662        /* We want to force full duplex so we SET the full duplex bits in the
1663         * Device and MII Control Registers.
1664         */
1665        ctrl |= E1000_CTRL_FD;
1666        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1667        DEBUGOUT("Full Duplex\n");
1668    } else {
1669        /* We want to force half duplex so we CLEAR the full duplex bits in
1670         * the Device and MII Control Registers.
1671         */
1672        ctrl &= ~E1000_CTRL_FD;
1673        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1674        DEBUGOUT("Half Duplex\n");
1675    }
1676
1677    /* Are we forcing 100Mbps??? */
1678    if(hw->forced_speed_duplex == em_100_full ||
1679       hw->forced_speed_duplex == em_100_half) {
1680        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1681        ctrl |= E1000_CTRL_SPD_100;
1682        mii_ctrl_reg |= MII_CR_SPEED_100;
1683        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1684        DEBUGOUT("Forcing 100mb ");
1685    } else {
1686        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1687        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1688        mii_ctrl_reg |= MII_CR_SPEED_10;
1689        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1690        DEBUGOUT("Forcing 10mb ");
1691    }
1692
1693    em_config_collision_dist(hw);
1694
1695    /* Write the configured values back to the Device Control Reg. */
1696    E1000_WRITE_REG(hw, CTRL, ctrl);
1697
1698    if (hw->phy_type == em_phy_m88) {
1699        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1700        if(ret_val)
1701            return ret_val;
1702
1703        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1704         * forced whenever speed are duplex are forced.
1705         */
1706        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1707        ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1708        if(ret_val)
1709            return ret_val;
1710
1711        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1712
1713        /* Need to reset the PHY or these changes will be ignored */
1714        mii_ctrl_reg |= MII_CR_RESET;
1715    } else {
1716        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
1717         * forced whenever speed or duplex are forced.
1718         */
1719        ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1720        if(ret_val)
1721            return ret_val;
1722
1723        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1724        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1725
1726        ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1727        if(ret_val)
1728            return ret_val;
1729    }
1730
1731    /* Write back the modified PHY MII control register. */
1732    ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1733    if(ret_val)
1734        return ret_val;
1735
1736    usec_delay(1);
1737
1738    /* The wait_autoneg_complete flag may be a little misleading here.
1739     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1740     * But we do want to delay for a period while forcing only so we
1741     * don't generate false No Link messages.  So we will wait here
1742     * only if the user has set wait_autoneg_complete to 1, which is
1743     * the default.
1744     */
1745    if(hw->wait_autoneg_complete) {
1746        /* We will wait for autoneg to complete. */
1747        DEBUGOUT("Waiting for forced speed/duplex link.\n");
1748        mii_status_reg = 0;
1749
1750        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1751        for(i = PHY_FORCE_TIME; i > 0; i--) {
1752            /* Read the MII Status Register and wait for Auto-Neg Complete bit
1753             * to be set.
1754             */
1755            ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1756            if(ret_val)
1757                return ret_val;
1758
1759            ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1760            if(ret_val)
1761                return ret_val;
1762
1763            if(mii_status_reg & MII_SR_LINK_STATUS) break;
1764            msec_delay(100);
1765        }
1766        if((i == 0) &&
1767           (hw->phy_type == em_phy_m88)) {
1768            /* We didn't get link.  Reset the DSP and wait again for link. */
1769            ret_val = em_phy_reset_dsp(hw);
1770            if(ret_val) {
1771                DEBUGOUT("Error Resetting PHY DSP\n");
1772                return ret_val;
1773            }
1774        }
1775        /* This loop will early-out if the link condition has been met.  */
1776        for(i = PHY_FORCE_TIME; i > 0; i--) {
1777            if(mii_status_reg & MII_SR_LINK_STATUS) break;
1778            msec_delay(100);
1779            /* Read the MII Status Register and wait for Auto-Neg Complete bit
1780             * to be set.
1781             */
1782            ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1783            if(ret_val)
1784                return ret_val;
1785
1786            ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1787            if(ret_val)
1788                return ret_val;
1789        }
1790    }
1791
1792    if (hw->phy_type == em_phy_m88) {
1793        /* Because we reset the PHY above, we need to re-force TX_CLK in the
1794         * Extended PHY Specific Control Register to 25MHz clock.  This value
1795         * defaults back to a 2.5MHz clock when the PHY is reset.
1796         */
1797        ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1798        if(ret_val)
1799            return ret_val;
1800
1801        phy_data |= M88E1000_EPSCR_TX_CLK_25;
1802        ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1803        if(ret_val)
1804            return ret_val;
1805
1806        /* In addition, because of the s/w reset above, we need to enable CRS on
1807         * TX.  This must be set for both full and half duplex operation.
1808         */
1809        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1810        if(ret_val)
1811            return ret_val;
1812
1813        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1814        ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1815        if(ret_val)
1816            return ret_val;
1817
1818        if((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
1819           (!hw->autoneg) &&
1820           (hw->forced_speed_duplex == em_10_full ||
1821            hw->forced_speed_duplex == em_10_half)) {
1822            ret_val = em_polarity_reversal_workaround(hw);
1823            if(ret_val)
1824                return ret_val;
1825        }
1826    }
1827    return E1000_SUCCESS;
1828}
1829
1830/******************************************************************************
1831* Sets the collision distance in the Transmit Control register
1832*
1833* hw - Struct containing variables accessed by shared code
1834*
1835* Link should have been established previously. Reads the speed and duplex
1836* information from the Device Status register.
1837******************************************************************************/
1838void
1839em_config_collision_dist(struct em_hw *hw)
1840{
1841    uint32_t tctl;
1842
1843    DEBUGFUNC("em_config_collision_dist");
1844
1845    tctl = E1000_READ_REG(hw, TCTL);
1846
1847    tctl &= ~E1000_TCTL_COLD;
1848    tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1849
1850    E1000_WRITE_REG(hw, TCTL, tctl);
1851    E1000_WRITE_FLUSH(hw);
1852}
1853
1854/******************************************************************************
1855* Sets MAC speed and duplex settings to reflect the those in the PHY
1856*
1857* hw - Struct containing variables accessed by shared code
1858* mii_reg - data to write to the MII control register
1859*
1860* The contents of the PHY register containing the needed information need to
1861* be passed in.
1862******************************************************************************/
1863static int32_t
1864em_config_mac_to_phy(struct em_hw *hw)
1865{
1866    uint32_t ctrl;
1867    int32_t ret_val;
1868    uint16_t phy_data;
1869
1870    DEBUGFUNC("em_config_mac_to_phy");
1871
1872    /* 82544 or newer MAC, Auto Speed Detection takes care of
1873    * MAC speed/duplex configuration.*/
1874    if (hw->mac_type >= em_82544)
1875        return E1000_SUCCESS;
1876
1877    /* Read the Device Control Register and set the bits to Force Speed
1878     * and Duplex.
1879     */
1880    ctrl = E1000_READ_REG(hw, CTRL);
1881    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1882    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1883
1884    /* Set up duplex in the Device Control and Transmit Control
1885     * registers depending on negotiated values.
1886     */
1887    ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1888    if(ret_val)
1889        return ret_val;
1890
1891    if(phy_data & M88E1000_PSSR_DPLX) 
1892        ctrl |= E1000_CTRL_FD;
1893    else 
1894        ctrl &= ~E1000_CTRL_FD;
1895
1896    em_config_collision_dist(hw);
1897
1898    /* Set up speed in the Device Control register depending on
1899     * negotiated values.
1900     */
1901    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1902        ctrl |= E1000_CTRL_SPD_1000;
1903    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1904        ctrl |= E1000_CTRL_SPD_100;
1905
1906    /* Write the configured values back to the Device Control Reg. */
1907    E1000_WRITE_REG(hw, CTRL, ctrl);
1908    return E1000_SUCCESS;
1909}
1910
1911/******************************************************************************
1912 * Forces the MAC's flow control settings.
1913 *
1914 * hw - Struct containing variables accessed by shared code
1915 *
1916 * Sets the TFCE and RFCE bits in the device control register to reflect
1917 * the adapter settings. TFCE and RFCE need to be explicitly set by
1918 * software when a Copper PHY is used because autonegotiation is managed
1919 * by the PHY rather than the MAC. Software must also configure these
1920 * bits when link is forced on a fiber connection.
1921 *****************************************************************************/
1922int32_t
1923em_force_mac_fc(struct em_hw *hw)
1924{
1925    uint32_t ctrl;
1926
1927    DEBUGFUNC("em_force_mac_fc");
1928
1929    /* Get the current configuration of the Device Control Register */
1930    ctrl = E1000_READ_REG(hw, CTRL);
1931
1932    /* Because we didn't get link via the internal auto-negotiation
1933     * mechanism (we either forced link or we got link via PHY
1934     * auto-neg), we have to manually enable/disable transmit an
1935     * receive flow control.
1936     *
1937     * The "Case" statement below enables/disable flow control
1938     * according to the "hw->fc" parameter.
1939     *
1940     * The possible values of the "fc" parameter are:
1941     *      0:  Flow control is completely disabled
1942     *      1:  Rx flow control is enabled (we can receive pause
1943     *          frames but not send pause frames).
1944     *      2:  Tx flow control is enabled (we can send pause frames
1945     *          frames but we do not receive pause frames).
1946     *      3:  Both Rx and TX flow control (symmetric) is enabled.
1947     *  other:  No other values should be possible at this point.
1948     */
1949
1950    switch (hw->fc) {
1951    case em_fc_none:
1952        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1953        break;
1954    case em_fc_rx_pause:
1955        ctrl &= (~E1000_CTRL_TFCE);
1956        ctrl |= E1000_CTRL_RFCE;
1957        break;
1958    case em_fc_tx_pause:
1959        ctrl &= (~E1000_CTRL_RFCE);
1960        ctrl |= E1000_CTRL_TFCE;
1961        break;
1962    case em_fc_full:
1963        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1964        break;
1965    default:
1966        DEBUGOUT("Flow control param set incorrectly\n");
1967        return -E1000_ERR_CONFIG;
1968    }
1969
1970    /* Disable TX Flow Control for 82542 (rev 2.0) */
1971    if(hw->mac_type == em_82542_rev2_0)
1972        ctrl &= (~E1000_CTRL_TFCE);
1973
1974    E1000_WRITE_REG(hw, CTRL, ctrl);
1975    return E1000_SUCCESS;
1976}
1977
1978/******************************************************************************
1979 * Configures flow control settings after link is established
1980 *
1981 * hw - Struct containing variables accessed by shared code
1982 *
1983 * Should be called immediately after a valid link has been established.
1984 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1985 * and autonegotiation is enabled, the MAC flow control settings will be set
1986 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1987 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1988 *****************************************************************************/
1989int32_t
1990em_config_fc_after_link_up(struct em_hw *hw)
1991{
1992    int32_t ret_val;
1993    uint16_t mii_status_reg;
1994    uint16_t mii_nway_adv_reg;
1995    uint16_t mii_nway_lp_ability_reg;
1996    uint16_t speed;
1997    uint16_t duplex;
1998
1999    DEBUGFUNC("em_config_fc_after_link_up");
2000
2001    /* Check for the case where we have fiber media and auto-neg failed
2002     * so we had to force link.  In this case, we need to force the
2003     * configuration of the MAC to match the "fc" parameter.
2004     */
2005    if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
2006       ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2007       ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
2008        ret_val = em_force_mac_fc(hw);
2009        if(ret_val) {
2010            DEBUGOUT("Error forcing flow control settings\n");
2011            return ret_val;
2012        }
2013    }
2014
2015    /* Check for the case where we have copper media and auto-neg is
2016     * enabled.  In this case, we need to check and see if Auto-Neg
2017     * has completed, and if so, how the PHY and link partner has
2018     * flow control configured.
2019     */
2020    if((hw->media_type == em_media_type_copper) && hw->autoneg) {
2021        /* Read the MII Status Register and check to see if AutoNeg
2022         * has completed.  We read this twice because this reg has
2023         * some "sticky" (latched) bits.
2024         */
2025        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2026        if(ret_val)
2027            return ret_val;
2028        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2029        if(ret_val)
2030            return ret_val;
2031
2032        if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2033            /* The AutoNeg process has completed, so we now need to
2034             * read both the Auto Negotiation Advertisement Register
2035             * (Address 4) and the Auto_Negotiation Base Page Ability
2036             * Register (Address 5) to determine how flow control was
2037             * negotiated.
2038             */
2039            ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
2040                                         &mii_nway_adv_reg);
2041            if(ret_val)
2042                return ret_val;
2043            ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
2044                                         &mii_nway_lp_ability_reg);
2045            if(ret_val)
2046                return ret_val;
2047
2048            /* Two bits in the Auto Negotiation Advertisement Register
2049             * (Address 4) and two bits in the Auto Negotiation Base
2050             * Page Ability Register (Address 5) determine flow control
2051             * for both the PHY and the link partner.  The following
2052             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2053             * 1999, describes these PAUSE resolution bits and how flow
2054             * control is determined based upon these settings.
2055             * NOTE:  DC = Don't Care
2056             *
2057             *   LOCAL DEVICE  |   LINK PARTNER
2058             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2059             *-------|---------|-------|---------|--------------------
2060             *   0   |    0    |  DC   |   DC    | em_fc_none
2061             *   0   |    1    |   0   |   DC    | em_fc_none
2062             *   0   |    1    |   1   |    0    | em_fc_none
2063             *   0   |    1    |   1   |    1    | em_fc_tx_pause
2064             *   1   |    0    |   0   |   DC    | em_fc_none
2065             *   1   |   DC    |   1   |   DC    | em_fc_full
2066             *   1   |    1    |   0   |    0    | em_fc_none
2067             *   1   |    1    |   0   |    1    | em_fc_rx_pause
2068             *
2069             */
2070            /* Are both PAUSE bits set to 1?  If so, this implies
2071             * Symmetric Flow Control is enabled at both ends.  The
2072             * ASM_DIR bits are irrelevant per the spec.
2073             *
2074             * For Symmetric Flow Control:
2075             *
2076             *   LOCAL DEVICE  |   LINK PARTNER
2077             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2078             *-------|---------|-------|---------|--------------------
2079             *   1   |   DC    |   1   |   DC    | em_fc_full
2080             *
2081             */
2082            if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2083               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2084                /* Now we need to check if the user selected RX ONLY
2085                 * of pause frames.  In this case, we had to advertise
2086                 * FULL flow control because we could not advertise RX
2087                 * ONLY. Hence, we must now check to see if we need to
2088                 * turn OFF  the TRANSMISSION of PAUSE frames.
2089                 */
2090                if(hw->original_fc == em_fc_full) {
2091                    hw->fc = em_fc_full;
2092                    DEBUGOUT("Flow Control = FULL.\r\n");
2093                } else {
2094                    hw->fc = em_fc_rx_pause;
2095                    DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2096                }
2097            }
2098            /* For receiving PAUSE frames ONLY.
2099             *
2100             *   LOCAL DEVICE  |   LINK PARTNER
2101             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2102             *-------|---------|-------|---------|--------------------
2103             *   0   |    1    |   1   |    1    | em_fc_tx_pause
2104             *
2105             */
2106            else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2107                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2108                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2109                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2110                hw->fc = em_fc_tx_pause;
2111                DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2112            }
2113            /* For transmitting PAUSE frames ONLY.
2114             *
2115             *   LOCAL DEVICE  |   LINK PARTNER
2116             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2117             *-------|---------|-------|---------|--------------------
2118             *   1   |    1    |   0   |    1    | em_fc_rx_pause
2119             *
2120             */
2121            else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2122                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2123                    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2124                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2125                hw->fc = em_fc_rx_pause;
2126                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2127            }
2128            /* Per the IEEE spec, at this point flow control should be
2129             * disabled.  However, we want to consider that we could
2130             * be connected to a legacy switch that doesn't advertise
2131             * desired flow control, but can be forced on the link
2132             * partner.  So if we advertised no flow control, that is
2133             * what we will resolve to.  If we advertised some kind of
2134             * receive capability (Rx Pause Only or Full Flow Control)
2135             * and the link partner advertised none, we will configure
2136             * ourselves to enable Rx Flow Control only.  We can do
2137             * this safely for two reasons:  If the link partner really
2138             * didn't want flow control enabled, and we enable Rx, no
2139             * harm done since we won't be receiving any PAUSE frames
2140             * anyway.  If the intent on the link partner was to have
2141             * flow control enabled, then by us enabling RX only, we
2142             * can at least receive pause frames and process them.
2143             * This is a good idea because in most cases, since we are
2144             * predominantly a server NIC, more times than not we will
2145             * be asked to delay transmission of packets than asking
2146             * our link partner to pause transmission of frames.
2147             */
2148            else if((hw->original_fc == em_fc_none ||
2149                     hw->original_fc == em_fc_tx_pause) ||
2150                    hw->fc_strict_ieee) {
2151                hw->fc = em_fc_none;
2152                DEBUGOUT("Flow Control = NONE.\r\n");
2153            } else {
2154                hw->fc = em_fc_rx_pause;
2155                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2156            }
2157
2158            /* Now we need to do one last check...  If we auto-
2159             * negotiated to HALF DUPLEX, flow control should not be
2160             * enabled per IEEE 802.3 spec.
2161             */
2162            ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
2163            if(ret_val) {
2164                DEBUGOUT("Error getting link speed and duplex\n");
2165                return ret_val;
2166            }
2167
2168            if(duplex == HALF_DUPLEX)
2169                hw->fc = em_fc_none;
2170
2171            /* Now we call a subroutine to actually force the MAC
2172             * controller to use the correct flow control settings.
2173             */
2174            ret_val = em_force_mac_fc(hw);
2175            if(ret_val) {
2176                DEBUGOUT("Error forcing flow control settings\n");
2177                return ret_val;
2178            }
2179        } else {
2180            DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2181        }
2182    }
2183    return E1000_SUCCESS;
2184}
2185
2186/******************************************************************************
2187 * Checks to see if the link status of the hardware has changed.
2188 *
2189 * hw - Struct containing variables accessed by shared code
2190 *
2191 * Called by any function that needs to check the link status of the adapter.
2192 *****************************************************************************/
2193int32_t
2194em_check_for_link(struct em_hw *hw)
2195{
2196    uint32_t rxcw = 0;
2197    uint32_t ctrl;
2198    uint32_t status;
2199    uint32_t rctl;
2200    uint32_t icr;
2201    uint32_t signal = 0;
2202    int32_t ret_val;
2203    uint16_t phy_data;
2204
2205    DEBUGFUNC("em_check_for_link");
2206
2207    ctrl = E1000_READ_REG(hw, CTRL);
2208    status = E1000_READ_REG(hw, STATUS);
2209
2210    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2211     * set when the optics detect a signal. On older adapters, it will be
2212     * cleared when there is a signal.  This applies to fiber media only.
2213     */
2214    if((hw->media_type == em_media_type_fiber) ||
2215       (hw->media_type == em_media_type_internal_serdes)) {
2216        rxcw = E1000_READ_REG(hw, RXCW);
2217
2218        if(hw->media_type == em_media_type_fiber) {
2219            signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
2220            if(status & E1000_STATUS_LU)
2221                hw->get_link_status = FALSE;
2222        }
2223    }
2224
2225    /* If we have a copper PHY then we only want to go out to the PHY
2226     * registers to see if Auto-Neg has completed and/or if our link
2227     * status has changed.  The get_link_status flag will be set if we
2228     * receive a Link Status Change interrupt or we have Rx Sequence
2229     * Errors.
2230     */
2231    if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
2232        /* First we want to see if the MII Status Register reports
2233         * link.  If so, then we want to get the current speed/duplex
2234         * of the PHY.
2235         * Read the register twice since the link bit is sticky.
2236         */
2237        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2238        if(ret_val)
2239            return ret_val;
2240        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2241        if(ret_val)
2242            return ret_val;
2243
2244        if(phy_data & MII_SR_LINK_STATUS) {
2245            hw->get_link_status = FALSE;
2246            /* Check if there was DownShift, must be checked immediately after
2247             * link-up */
2248            em_check_downshift(hw);
2249
2250            /* If we are on 82544 or 82543 silicon and speed/duplex
2251             * are forced to 10H or 10F, then we will implement the polarity
2252             * reversal workaround.  We disable interrupts first, and upon
2253             * returning, place the devices interrupt state to its previous
2254             * value except for the link status change interrupt which will
2255             * happen due to the execution of this workaround.
2256             */
2257
2258            if((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
2259               (!hw->autoneg) &&
2260               (hw->forced_speed_duplex == em_10_full ||
2261                hw->forced_speed_duplex == em_10_half)) {
2262                E1000_WRITE_REG(hw, IMC, 0xffffffff);
2263                ret_val = em_polarity_reversal_workaround(hw);
2264                icr = E1000_READ_REG(hw, ICR);
2265                E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2266                E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2267            }
2268
2269        } else {
2270            /* No link detected */
2271            em_config_dsp_after_link_change(hw, FALSE);
2272            return 0;
2273        }
2274
2275        /* If we are forcing speed/duplex, then we simply return since
2276         * we have already determined whether we have link or not.
2277         */
2278        if(!hw->autoneg) return -E1000_ERR_CONFIG;
2279
2280        /* optimize the dsp settings for the igp phy */
2281        em_config_dsp_after_link_change(hw, TRUE);
2282
2283        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
2284         * have Si on board that is 82544 or newer, Auto
2285         * Speed Detection takes care of MAC speed/duplex
2286         * configuration.  So we only need to configure Collision
2287         * Distance in the MAC.  Otherwise, we need to force
2288         * speed/duplex on the MAC to the current PHY speed/duplex
2289         * settings.
2290         */
2291        if(hw->mac_type >= em_82544)
2292            em_config_collision_dist(hw);
2293        else {
2294            ret_val = em_config_mac_to_phy(hw);
2295            if(ret_val) {
2296                DEBUGOUT("Error configuring MAC to PHY settings\n");
2297                return ret_val;
2298            }
2299        }
2300
2301        /* Configure Flow Control now that Auto-Neg has completed. First, we
2302         * need to restore the desired flow control settings because we may
2303         * have had to re-autoneg with a different link partner.
2304         */
2305        ret_val = em_config_fc_after_link_up(hw);
2306        if(ret_val) {
2307            DEBUGOUT("Error configuring flow control\n");
2308            return ret_val;
2309        }
2310
2311        /* At this point we know that we are on copper and we have
2312         * auto-negotiated link.  These are conditions for checking the link
2313         * partner capability register.  We use the link speed to determine if
2314         * TBI compatibility needs to be turned on or off.  If the link is not
2315         * at gigabit speed, then TBI compatibility is not needed.  If we are
2316         * at gigabit speed, we turn on TBI compatibility.
2317         */
2318        if(hw->tbi_compatibility_en) {
2319            uint16_t speed, duplex;
2320            em_get_speed_and_duplex(hw, &speed, &duplex);
2321            if(speed != SPEED_1000) {
2322                /* If link speed is not set to gigabit speed, we do not need
2323                 * to enable TBI compatibility.
2324                 */
2325                if(hw->tbi_compatibility_on) {
2326                    /* If we previously were in the mode, turn it off. */
2327                    rctl = E1000_READ_REG(hw, RCTL);
2328                    rctl &= ~E1000_RCTL_SBP;
2329                    E1000_WRITE_REG(hw, RCTL, rctl);
2330                    hw->tbi_compatibility_on = FALSE;
2331                }
2332            } else {
2333                /* If TBI compatibility is was previously off, turn it on. For
2334                 * compatibility with a TBI link partner, we will store bad
2335                 * packets. Some frames have an additional byte on the end and
2336                 * will look like CRC errors to to the hardware.
2337                 */
2338                if(!hw->tbi_compatibility_on) {
2339                    hw->tbi_compatibility_on = TRUE;
2340                    rctl = E1000_READ_REG(hw, RCTL);
2341                    rctl |= E1000_RCTL_SBP;
2342                    E1000_WRITE_REG(hw, RCTL, rctl);
2343                }
2344            }
2345        }
2346    }
2347    /* If we don't have link (auto-negotiation failed or link partner cannot
2348     * auto-negotiate), the cable is plugged in (we have signal), and our
2349     * link partner is not trying to auto-negotiate with us (we are receiving
2350     * idles or data), we need to force link up. We also need to give
2351     * auto-negotiation time to complete, in case the cable was just plugged
2352     * in. The autoneg_failed flag does this.
2353     */
2354    else if((((hw->media_type == em_media_type_fiber) &&
2355              ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2356             (hw->media_type == em_media_type_internal_serdes)) &&
2357            (!(status & E1000_STATUS_LU)) &&
2358            (!(rxcw & E1000_RXCW_C))) {
2359        if(hw->autoneg_failed == 0) {
2360            hw->autoneg_failed = 1;
2361            return 0;
2362        }
2363        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2364
2365        /* Disable auto-negotiation in the TXCW register */
2366        E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2367
2368        /* Force link-up and also force full-duplex. */
2369        ctrl = E1000_READ_REG(hw, CTRL);
2370        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2371        E1000_WRITE_REG(hw, CTRL, ctrl);
2372
2373        /* Configure Flow Control after forcing link up. */
2374        ret_val = em_config_fc_after_link_up(hw);
2375        if(ret_val) {
2376            DEBUGOUT("Error configuring flow control\n");
2377            return ret_val;
2378        }
2379    }
2380    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2381     * auto-negotiation in the TXCW register and disable forced link in the
2382     * Device Control register in an attempt to auto-negotiate with our link
2383     * partner.
2384     */
2385    else if(((hw->media_type == em_media_type_fiber) ||
2386             (hw->media_type == em_media_type_internal_serdes)) &&
2387            (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2388        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2389        E1000_WRITE_REG(hw, TXCW, hw->txcw);
2390        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2391
2392        hw->serdes_link_down = FALSE;
2393    }
2394    /* If we force link for non-auto-negotiation switch, check link status
2395     * based on MAC synchronization for internal serdes media type.
2396     */
2397    else if((hw->media_type == em_media_type_internal_serdes) &&
2398            !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2399        /* SYNCH bit and IV bit are sticky. */
2400        usec_delay(10);
2401        if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2402            if(!(rxcw & E1000_RXCW_IV)) {
2403                hw->serdes_link_down = FALSE;
2404                DEBUGOUT("SERDES: Link is up.\n");
2405            }
2406        } else {
2407            hw->serdes_link_down = TRUE;
2408            DEBUGOUT("SERDES: Link is down.\n");
2409        }
2410    }
2411    if((hw->media_type == em_media_type_internal_serdes) &&
2412       (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2413        hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2414    }
2415    return E1000_SUCCESS;
2416}
2417
2418/******************************************************************************
2419 * Detects the current speed and duplex settings of the hardware.
2420 *
2421 * hw - Struct containing variables accessed by shared code
2422 * speed - Speed of the connection
2423 * duplex - Duplex setting of the connection
2424 *****************************************************************************/
2425int32_t
2426em_get_speed_and_duplex(struct em_hw *hw,
2427                           uint16_t *speed,
2428                           uint16_t *duplex)
2429{
2430    uint32_t status;
2431    int32_t ret_val;
2432    uint16_t phy_data;
2433
2434    DEBUGFUNC("em_get_speed_and_duplex");
2435
2436    if(hw->mac_type >= em_82543) {
2437        status = E1000_READ_REG(hw, STATUS);
2438        if(status & E1000_STATUS_SPEED_1000) {
2439            *speed = SPEED_1000;
2440            DEBUGOUT("1000 Mbs, ");
2441        } else if(status & E1000_STATUS_SPEED_100) {
2442            *speed = SPEED_100;
2443            DEBUGOUT("100 Mbs, ");
2444        } else {
2445            *speed = SPEED_10;
2446            DEBUGOUT("10 Mbs, ");
2447        }
2448
2449        if(status & E1000_STATUS_FD) {
2450            *duplex = FULL_DUPLEX;
2451            DEBUGOUT("Full Duplex\r\n");
2452        } else {
2453            *duplex = HALF_DUPLEX;
2454            DEBUGOUT(" Half Duplex\r\n");
2455        }
2456    } else {
2457        DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2458        *speed = SPEED_1000;
2459        *duplex = FULL_DUPLEX;
2460    }
2461
2462    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2463     * if it is operating at half duplex.  Here we set the duplex settings to
2464     * match the duplex in the link partner's capabilities.
2465     */
2466    if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
2467        ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2468        if(ret_val)
2469            return ret_val;
2470
2471        if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2472            *duplex = HALF_DUPLEX;
2473        else {
2474            ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2475            if(ret_val)
2476                return ret_val;
2477            if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2478               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2479                *duplex = HALF_DUPLEX;
2480        }
2481    }
2482
2483    return E1000_SUCCESS;
2484}
2485
2486/******************************************************************************
2487* Blocks until autoneg completes or times out (~4.5 seconds)
2488*
2489* hw - Struct containing variables accessed by shared code
2490******************************************************************************/
2491int32_t
2492em_wait_autoneg(struct em_hw *hw)
2493{
2494    int32_t ret_val;
2495    uint16_t i;
2496    uint16_t phy_data;
2497
2498    DEBUGFUNC("em_wait_autoneg");
2499    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2500
2501    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2502    for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2503        /* Read the MII Status Register and wait for Auto-Neg
2504         * Complete bit to be set.
2505         */
2506        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2507        if(ret_val)
2508            return ret_val;
2509        ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2510        if(ret_val)
2511            return ret_val;
2512        if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2513            return E1000_SUCCESS;
2514        }
2515        msec_delay(100);
2516    }
2517    return E1000_SUCCESS;
2518}
2519
2520/******************************************************************************
2521* Raises the Management Data Clock
2522*
2523* hw - Struct containing variables accessed by shared code
2524* ctrl - Device control register's current value
2525******************************************************************************/
2526static void
2527em_raise_mdi_clk(struct em_hw *hw,
2528                    uint32_t *ctrl)
2529{
2530    /* Raise the clock input to the Management Data Clock (by setting the MDC
2531     * bit), and then delay 10 microseconds.
2532     */
2533    E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2534    E1000_WRITE_FLUSH(hw);
2535    usec_delay(10);
2536}
2537
2538/******************************************************************************
2539* Lowers the Management Data Clock
2540*
2541* hw - Struct containing variables accessed by shared code
2542* ctrl - Device control register's current value
2543******************************************************************************/
2544static void
2545em_lower_mdi_clk(struct em_hw *hw,
2546                    uint32_t *ctrl)
2547{
2548    /* Lower the clock input to the Management Data Clock (by clearing the MDC
2549     * bit), and then delay 10 microseconds.
2550     */
2551    E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2552    E1000_WRITE_FLUSH(hw);
2553    usec_delay(10);
2554}
2555
2556/******************************************************************************
2557* Shifts data bits out to the PHY
2558*
2559* hw - Struct containing variables accessed by shared code
2560* data - Data to send out to the PHY
2561* count - Number of bits to shift out
2562*
2563* Bits are shifted out in MSB to LSB order.
2564******************************************************************************/
2565static void
2566em_shift_out_mdi_bits(struct em_hw *hw,
2567                         uint32_t data,
2568                         uint16_t count)
2569{
2570    uint32_t ctrl;
2571    uint32_t mask;
2572
2573    /* We need to shift "count" number of bits out to the PHY. So, the value
2574     * in the "data" parameter will be shifted out to the PHY one bit at a
2575     * time. In order to do this, "data" must be broken down into bits.
2576     */
2577    mask = 0x01;
2578    mask <<= (count - 1);
2579
2580    ctrl = E1000_READ_REG(hw, CTRL);
2581
2582    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2583    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2584
2585    while(mask) {
2586        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2587         * then raising and lowering the Management Data Clock. A "0" is
2588         * shifted out to the PHY by setting the MDIO bit to "0" and then
2589         * raising and lowering the clock.
2590         */
2591        if(data & mask) ctrl |= E1000_CTRL_MDIO;
2592        else ctrl &= ~E1000_CTRL_MDIO;
2593
2594        E1000_WRITE_REG(hw, CTRL, ctrl);
2595        E1000_WRITE_FLUSH(hw);
2596
2597        usec_delay(10);
2598
2599        em_raise_mdi_clk(hw, &ctrl);
2600        em_lower_mdi_clk(hw, &ctrl);
2601
2602        mask = mask >> 1;
2603    }
2604}
2605
2606/******************************************************************************
2607* Shifts data bits in from the PHY
2608*
2609* hw - Struct containing variables accessed by shared code
2610*
2611* Bits are shifted in in MSB to LSB order.
2612******************************************************************************/
2613static uint16_t
2614em_shift_in_mdi_bits(struct em_hw *hw)
2615{
2616    uint32_t ctrl;
2617    uint16_t data = 0;
2618    uint8_t i;
2619
2620    /* In order to read a register from the PHY, we need to shift in a total
2621     * of 18 bits from the PHY. The first two bit (turnaround) times are used
2622     * to avoid contention on the MDIO pin when a read operation is performed.
2623     * These two bits are ignored by us and thrown away. Bits are "shifted in"
2624     * by raising the input to the Management Data Clock (setting the MDC bit),
2625     * and then reading the value of the MDIO bit.
2626     */
2627    ctrl = E1000_READ_REG(hw, CTRL);
2628
2629    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2630    ctrl &= ~E1000_CTRL_MDIO_DIR;
2631    ctrl &= ~E1000_CTRL_MDIO;
2632
2633    E1000_WRITE_REG(hw, CTRL, ctrl);
2634    E1000_WRITE_FLUSH(hw);
2635
2636    /* Raise and Lower the clock before reading in the data. This accounts for
2637     * the turnaround bits. The first clock occurred when we clocked out the
2638     * last bit of the Register Address.
2639     */
2640    em_raise_mdi_clk(hw, &ctrl);
2641    em_lower_mdi_clk(hw, &ctrl);
2642
2643    for(data = 0, i = 0; i < 16; i++) {
2644        data = data << 1;
2645        em_raise_mdi_clk(hw, &ctrl);
2646        ctrl = E1000_READ_REG(hw, CTRL);
2647        /* Check to see if we shifted in a "1". */
2648        if(ctrl & E1000_CTRL_MDIO) data |= 1;
2649        em_lower_mdi_clk(hw, &ctrl);
2650    }
2651
2652    em_raise_mdi_clk(hw, &ctrl);
2653    em_lower_mdi_clk(hw, &ctrl);
2654
2655    return data;
2656}
2657
2658/*****************************************************************************
2659* Reads the value from a PHY register, if the value is on a specific non zero
2660* page, sets the page first.
2661* hw - Struct containing variables accessed by shared code
2662* reg_addr - address of the PHY register to read
2663******************************************************************************/
2664int32_t
2665em_read_phy_reg(struct em_hw *hw,
2666                   uint32_t reg_addr,
2667                   uint16_t *phy_data)
2668{
2669    uint32_t ret_val;
2670
2671    DEBUGFUNC("em_read_phy_reg");
2672
2673    if((hw->phy_type == em_phy_igp || 
2674        hw->phy_type == em_phy_igp_2) &&
2675       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2676        ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2677                                         (uint16_t)reg_addr);
2678        if(ret_val) {
2679            return ret_val;
2680        }
2681    }
2682
2683    ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2684                                    phy_data);
2685
2686    return ret_val;
2687}
2688
2689int32_t
2690em_read_phy_reg_ex(struct em_hw *hw,
2691                      uint32_t reg_addr,
2692                      uint16_t *phy_data)
2693{
2694    uint32_t i;
2695    uint32_t mdic = 0;
2696    const uint32_t phy_addr = 1;
2697
2698    DEBUGFUNC("em_read_phy_reg_ex");
2699
2700    if(reg_addr > MAX_PHY_REG_ADDRESS) {
2701        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2702        return -E1000_ERR_PARAM;
2703    }
2704
2705    if(hw->mac_type > em_82543) {
2706        /* Set up Op-code, Phy Address, and register address in the MDI
2707         * Control register.  The MAC will take care of interfacing with the
2708         * PHY to retrieve the desired data.
2709         */
2710        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2711                (phy_addr << E1000_MDIC_PHY_SHIFT) |
2712                (E1000_MDIC_OP_READ));
2713
2714        E1000_WRITE_REG(hw, MDIC, mdic);
2715
2716        /* Poll the ready bit to see if the MDI read completed */
2717        for(i = 0; i < 64; i++) {
2718            usec_delay(50);
2719            mdic = E1000_READ_REG(hw, MDIC);
2720            if(mdic & E1000_MDIC_READY) break;
2721        }
2722        if(!(mdic & E1000_MDIC_READY)) {
2723            DEBUGOUT("MDI Read did not complete\n");
2724            return -E1000_ERR_PHY;
2725        }
2726        if(mdic & E1000_MDIC_ERROR) {
2727            DEBUGOUT("MDI Error\n");
2728            return -E1000_ERR_PHY;
2729        }
2730        *phy_data = (uint16_t) mdic;
2731    } else {
2732        /* We must first send a preamble through the MDIO pin to signal the
2733         * beginning of an MII instruction.  This is done by sending 32
2734         * consecutive "1" bits.
2735         */
2736        em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2737
2738        /* Now combine the next few fields that are required for a read
2739         * operation.  We use this method instead of calling the
2740         * em_shift_out_mdi_bits routine five different times. The format of
2741         * a MII read instruction consists of a shift out of 14 bits and is
2742         * defined as follows:
2743         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2744         * followed by a shift in of 18 bits.  This first two bits shifted in
2745         * are TurnAround bits used to avoid contention on the MDIO pin when a
2746         * READ operation is performed.  These two bits are thrown away
2747         * followed by a shift in of 16 bits which contains the desired data.
2748         */
2749        mdic = ((reg_addr) | (phy_addr << 5) |
2750                (PHY_OP_READ << 10) | (PHY_SOF << 12));
2751
2752        em_shift_out_mdi_bits(hw, mdic, 14);
2753
2754        /* Now that we've shifted out the read command to the MII, we need to
2755         * "shift in" the 16-bit value (18 total bits) of the requested PHY
2756         * register address.
2757         */
2758        *phy_data = em_shift_in_mdi_bits(hw);
2759    }
2760    return E1000_SUCCESS;
2761}
2762
2763/******************************************************************************
2764* Writes a value to a PHY register
2765*
2766* hw - Struct containing variables accessed by shared code
2767* reg_addr - address of the PHY register to write
2768* data - data to write to the PHY
2769******************************************************************************/
2770int32_t
2771em_write_phy_reg(struct em_hw *hw,
2772                    uint32_t reg_addr,
2773                    uint16_t phy_data)
2774{
2775    uint32_t ret_val;
2776
2777    DEBUGFUNC("em_write_phy_reg");
2778
2779    if((hw->phy_type == em_phy_igp || 
2780        hw->phy_type == em_phy_igp_2) &&
2781       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2782        ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2783                                         (uint16_t)reg_addr);
2784        if(ret_val) {
2785            return ret_val;
2786        }
2787    }
2788
2789    ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2790                                     phy_data);
2791
2792    return ret_val;
2793}
2794
2795int32_t
2796em_write_phy_reg_ex(struct em_hw *hw,
2797                    uint32_t reg_addr,
2798                    uint16_t phy_data)
2799{
2800    uint32_t i;
2801    uint32_t mdic = 0;
2802    const uint32_t phy_addr = 1;
2803
2804    DEBUGFUNC("em_write_phy_reg_ex");
2805
2806    if(reg_addr > MAX_PHY_REG_ADDRESS) {
2807        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2808        return -E1000_ERR_PARAM;
2809    }
2810
2811    if(hw->mac_type > em_82543) {
2812        /* Set up Op-code, Phy Address, register address, and data intended
2813         * for the PHY register in the MDI Control register.  The MAC will take
2814         * care of interfacing with the PHY to send the desired data.
2815         */
2816        mdic = (((uint32_t) phy_data) |
2817                (reg_addr << E1000_MDIC_REG_SHIFT) |
2818                (phy_addr << E1000_MDIC_PHY_SHIFT) |
2819                (E1000_MDIC_OP_WRITE));
2820
2821        E1000_WRITE_REG(hw, MDIC, mdic);
2822
2823        /* Poll the ready bit to see if the MDI read completed */
2824        for(i = 0; i < 640; i++) {
2825            usec_delay(5);
2826            mdic = E1000_READ_REG(hw, MDIC);
2827            if(mdic & E1000_MDIC_READY) break;
2828        }
2829        if(!(mdic & E1000_MDIC_READY)) {
2830            DEBUGOUT("MDI Write did not complete\n");
2831            return -E1000_ERR_PHY;
2832        }
2833    } else {
2834        /* We'll need to use the SW defined pins to shift the write command
2835         * out to the PHY. We first send a preamble to the PHY to signal the
2836         * beginning of the MII instruction.  This is done by sending 32
2837         * consecutive "1" bits.
2838         */
2839        em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2840
2841        /* Now combine the remaining required fields that will indicate a
2842         * write operation. We use this method instead of calling the
2843         * em_shift_out_mdi_bits routine for each field in the command. The
2844         * format of a MII write instruction is as follows:
2845         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2846         */
2847        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2848                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2849        mdic <<= 16;
2850        mdic |= (uint32_t) phy_data;
2851
2852        em_shift_out_mdi_bits(hw, mdic, 32);
2853    }
2854
2855    return E1000_SUCCESS;
2856}
2857
2858
2859/******************************************************************************
2860* Returns the PHY to the power-on reset state
2861*
2862* hw - Struct containing variables accessed by shared code
2863******************************************************************************/
2864int32_t
2865em_phy_hw_reset(struct em_hw *hw)
2866{
2867    uint32_t ctrl, ctrl_ext;
2868    uint32_t led_ctrl;
2869    int32_t ret_val;
2870
2871    DEBUGFUNC("em_phy_hw_reset");
2872
2873    /* In the case of the phy reset being blocked, it's not an error, we
2874     * simply return success without performing the reset. */
2875    ret_val = em_check_phy_reset_block(hw);
2876    if (ret_val)
2877        return E1000_SUCCESS;
2878
2879    DEBUGOUT("Resetting Phy...\n");
2880
2881    if(hw->mac_type > em_82543) {
2882        /* Read the device control register and assert the E1000_CTRL_PHY_RST
2883         * bit. Then, take it out of reset.
2884         */
2885        ctrl = E1000_READ_REG(hw, CTRL);
2886        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2887        E1000_WRITE_FLUSH(hw);
2888        msec_delay(10);
2889        E1000_WRITE_REG(hw, CTRL, ctrl);
2890        E1000_WRITE_FLUSH(hw);
2891    } else {
2892        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2893         * bit to put the PHY into reset. Then, take it out of reset.
2894         */
2895        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2896        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2897        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2898        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2899        E1000_WRITE_FLUSH(hw);
2900        msec_delay(10);
2901        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2902        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2903        E1000_WRITE_FLUSH(hw);
2904    }
2905    usec_delay(150);
2906
2907    if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2908        /* Configure activity LED after PHY reset */
2909        led_ctrl = E1000_READ_REG(hw, LEDCTL);
2910        led_ctrl &= IGP_ACTIVITY_LED_MASK;
2911        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2912        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2913    }
2914
2915    /* Wait for FW to finish PHY configuration. */
2916    ret_val = em_get_phy_cfg_done(hw);
2917
2918    return ret_val;
2919}
2920
2921/******************************************************************************
2922* Resets the PHY
2923*
2924* hw - Struct containing variables accessed by shared code
2925*
2926* Sets bit 15 of the MII Control regiser
2927******************************************************************************/
2928int32_t
2929em_phy_reset(struct em_hw *hw)
2930{
2931    int32_t ret_val;
2932    uint16_t phy_data;
2933
2934    DEBUGFUNC("em_phy_reset");
2935
2936    /* In the case of the phy reset being blocked, it's not an error, we
2937     * simply return success without performing the reset. */
2938    ret_val = em_check_phy_reset_block(hw);
2939    if (ret_val)
2940        return E1000_SUCCESS;
2941
2942    switch (hw->mac_type) {
2943    case em_82541_rev_2:
2944        ret_val = em_phy_hw_reset(hw);
2945        if(ret_val)
2946            return ret_val;
2947        break;
2948    default:
2949        ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
2950        if(ret_val)
2951            return ret_val;
2952
2953        phy_data |= MII_CR_RESET;
2954        ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
2955        if(ret_val)
2956            return ret_val;
2957
2958        usec_delay(1);
2959        break;
2960    }
2961
2962    if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
2963        em_phy_init_script(hw);
2964
2965    return E1000_SUCCESS;
2966}
2967
2968/******************************************************************************
2969* Probes the expected PHY address for known PHY IDs
2970*
2971* hw - Struct containing variables accessed by shared code
2972******************************************************************************/
2973int32_t
2974em_detect_gig_phy(struct em_hw *hw)
2975{
2976    int32_t phy_init_status, ret_val;
2977    uint16_t phy_id_high, phy_id_low;
2978    boolean_t match = FALSE;
2979
2980    DEBUGFUNC("em_detect_gig_phy");
2981
2982    /* Read the PHY ID Registers to identify which PHY is onboard. */
2983    ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2984    if(ret_val)
2985        return ret_val;
2986
2987    hw->phy_id = (uint32_t) (phy_id_high << 16);
2988    usec_delay(20);
2989    ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2990    if(ret_val)
2991        return ret_val;
2992
2993    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2994    hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2995
2996    switch(hw->mac_type) {
2997    case em_82543:
2998        if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2999        break;
3000    case em_82544:
3001        if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3002        break;
3003    case em_82540:
3004    case em_82545:
3005    case em_82545_rev_3:
3006    case em_82546:
3007    case em_82546_rev_3:
3008        if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3009        break;
3010    case em_82541:
3011    case em_82541_rev_2:
3012    case em_82547:
3013    case em_82547_rev_2:
3014        if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3015        break;
3016    case em_82573:
3017        if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3018        break;
3019    default:
3020        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3021        return -E1000_ERR_CONFIG;
3022    }
3023    phy_init_status = em_set_phy_type(hw);
3024
3025    if ((match) && (phy_init_status == E1000_SUCCESS)) {
3026        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3027        return E1000_SUCCESS;
3028    }
3029    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3030    return -E1000_ERR_PHY;
3031}
3032
3033/******************************************************************************
3034* Resets the PHY's DSP
3035*
3036* hw - Struct containing variables accessed by shared code
3037******************************************************************************/
3038static int32_t
3039em_phy_reset_dsp(struct em_hw *hw)
3040{
3041    int32_t ret_val;
3042    DEBUGFUNC("em_phy_reset_dsp");
3043
3044    do {
3045        ret_val = em_write_phy_reg(hw, 29, 0x001d);
3046        if(ret_val) break;
3047        ret_val = em_write_phy_reg(hw, 30, 0x00c1);
3048        if(ret_val) break;
3049        ret_val = em_write_phy_reg(hw, 30, 0x0000);
3050        if(ret_val) break;
3051        ret_val = E1000_SUCCESS;
3052    } while(0);
3053
3054    return ret_val;
3055}
3056
3057/******************************************************************************
3058* Get PHY information from various PHY registers for igp PHY only.
3059*
3060* hw - Struct containing variables accessed by shared code
3061* phy_info - PHY information structure
3062******************************************************************************/
3063int32_t
3064em_phy_igp_get_info(struct em_hw *hw,
3065                       struct em_phy_info *phy_info)
3066{
3067    int32_t ret_val;
3068    uint16_t phy_data, polarity, min_length, max_length, average;
3069
3070    DEBUGFUNC("em_phy_igp_get_info");
3071
3072    /* The downshift status is checked only once, after link is established,
3073     * and it stored in the hw->speed_downgraded parameter. */
3074    phy_info->downshift = (em_downshift)hw->speed_downgraded;
3075
3076    /* IGP01E1000 does not need to support it. */
3077    phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
3078
3079    /* IGP01E1000 always correct polarity reversal */
3080    phy_info->polarity_correction = em_polarity_reversal_enabled;
3081
3082    /* Check polarity status */
3083    ret_val = em_check_polarity(hw, &polarity);
3084    if(ret_val)
3085        return ret_val;
3086
3087    phy_info->cable_polarity = polarity;
3088
3089    ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3090    if(ret_val)
3091        return ret_val;
3092
3093    phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
3094                          IGP01E1000_PSSR_MDIX_SHIFT;
3095
3096    if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3097       IGP01E1000_PSSR_SPEED_1000MBPS) {
3098        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3099        ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3100        if(ret_val)
3101            return ret_val;
3102
3103        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3104                             SR_1000T_LOCAL_RX_STATUS_SHIFT;
3105        phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3106                              SR_1000T_REMOTE_RX_STATUS_SHIFT;
3107
3108        /* Get cable length */
3109        ret_val = em_get_cable_length(hw, &min_length, &max_length);
3110        if(ret_val)
3111            return ret_val;
3112
3113        /* Translate to old method */
3114        average = (max_length + min_length) / 2;
3115
3116        if(average <= em_igp_cable_length_50)
3117            phy_info->cable_length = em_cable_length_50;
3118        else if(average <= em_igp_cable_length_80)
3119            phy_info->cable_length = em_cable_length_50_80;
3120        else if(average <= em_igp_cable_length_110)
3121            phy_info->cable_length = em_cable_length_80_110;
3122        else if(average <= em_igp_cable_length_140)
3123            phy_info->cable_length = em_cable_length_110_140;
3124        else
3125            phy_info->cable_length = em_cable_length_140;
3126    }
3127
3128    return E1000_SUCCESS;
3129}
3130
3131/******************************************************************************
3132* Get PHY information from various PHY registers fot m88 PHY only.
3133*
3134* hw - Struct containing variables accessed by shared code
3135* phy_info - PHY information structure
3136******************************************************************************/
3137int32_t
3138em_phy_m88_get_info(struct em_hw *hw,
3139                       struct em_phy_info *phy_info)
3140{
3141    int32_t ret_val;
3142    uint16_t phy_data, polarity;
3143
3144    DEBUGFUNC("em_phy_m88_get_info");
3145
3146    /* The downshift status is checked only once, after link is established,
3147     * and it stored in the hw->speed_downgraded parameter. */
3148    phy_info->downshift = (em_downshift)hw->speed_downgraded;
3149
3150    ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3151    if(ret_val)
3152        return ret_val;
3153
3154    phy_info->extended_10bt_distance =
3155        (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3156        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
3157    phy_info->polarity_correction =
3158        (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3159        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
3160
3161    /* Check polarity status */
3162    ret_val = em_check_polarity(hw, &polarity);
3163    if(ret_val)
3164        return ret_val; 
3165    phy_info->cable_polarity = polarity;
3166
3167    ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3168    if(ret_val)
3169        return ret_val;
3170
3171    phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
3172                          M88E1000_PSSR_MDIX_SHIFT;
3173
3174    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3175        /* Cable Length Estimation and Local/Remote Receiver Information
3176         * are only valid at 1000 Mbps.
3177         */
3178        phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
3179                                  M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3180
3181        ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3182        if(ret_val)
3183            return ret_val;
3184
3185        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3186                             SR_1000T_LOCAL_RX_STATUS_SHIFT;
3187
3188        phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3189                              SR_1000T_REMOTE_RX_STATUS_SHIFT;
3190    }
3191
3192    return E1000_SUCCESS;
3193}
3194
3195/******************************************************************************
3196* Get PHY information from various PHY registers
3197*
3198* hw - Struct containing variables accessed by shared code
3199* phy_info - PHY information structure
3200******************************************************************************/
3201int32_t
3202em_phy_get_info(struct em_hw *hw,
3203                   struct em_phy_info *phy_info)
3204{
3205    int32_t ret_val;
3206    uint16_t phy_data;
3207
3208    DEBUGFUNC("em_phy_get_info");
3209
3210    phy_info->cable_length = em_cable_length_undefined;
3211    phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
3212    phy_info->cable_polarity = em_rev_polarity_undefined;
3213    phy_info->downshift = em_downshift_undefined;
3214    phy_info->polarity_correction = em_polarity_reversal_undefined;
3215    phy_info->mdix_mode = em_auto_x_mode_undefined;
3216    phy_info->local_rx = em_1000t_rx_status_undefined;
3217    phy_info->remote_rx = em_1000t_rx_status_undefined;
3218
3219    if(hw->media_type != em_media_type_copper) {
3220        DEBUGOUT("PHY info is only valid for copper media\n");
3221        return -E1000_ERR_CONFIG;
3222    }
3223
3224    ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3225    if(ret_val)
3226        return ret_val;
3227
3228    ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3229    if(ret_val)
3230        return ret_val;
3231
3232    if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3233        DEBUGOUT("PHY info is only valid if link is up\n");
3234        return -E1000_ERR_CONFIG;
3235    }
3236
3237    if(hw->phy_type == em_phy_igp ||
3238        hw->phy_type == em_phy_igp_2)
3239        return em_phy_igp_get_info(hw, phy_info);
3240    else
3241        return em_phy_m88_get_info(hw, phy_info);
3242}
3243
3244int32_t
3245em_validate_mdi_setting(struct em_hw *hw)
3246{
3247    DEBUGFUNC("em_validate_mdi_settings");
3248
3249    if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3250        DEBUGOUT("Invalid MDI setting detected\n");
3251        hw->mdix = 1;
3252        return -E1000_ERR_CONFIG;
3253    }
3254    return E1000_SUCCESS;
3255}
3256
3257
3258/******************************************************************************
3259 * Sets up eeprom variables in the hw struct.  Must be called after mac_type
3260 * is configured.
3261 *
3262 * hw - Struct containing variables accessed by shared code
3263 *****************************************************************************/
3264int32_t
3265em_init_eeprom_params(struct em_hw *hw)
3266{
3267    struct em_eeprom_info *eeprom = &hw->eeprom;
3268    uint32_t eecd = E1000_READ_REG(hw, EECD);
3269    int32_t ret_val = E1000_SUCCESS;
3270    uint16_t eeprom_size;
3271
3272    DEBUGFUNC("em_init_eeprom_params");
3273
3274    switch (hw->mac_type) {
3275    case em_82542_rev2_0:
3276    case em_82542_rev2_1:
3277    case em_82543:
3278    case em_82544:
3279        eeprom->type = em_eeprom_microwire;
3280        eeprom->word_size = 64;
3281        eeprom->opcode_bits = 3;
3282        eeprom->address_bits = 6;
3283        eeprom->delay_usec = 50;
3284        eeprom->use_eerd = FALSE;
3285        eeprom->use_eewr = FALSE;
3286        break;
3287    case em_82540:
3288    case em_82545:
3289    case em_82545_rev_3:
3290    case em_82546:
3291    case em_82546_rev_3:
3292        eeprom->type = em_eeprom_microwire;
3293        eeprom->opcode_bits = 3;
3294        eeprom->delay_usec = 50;
3295        if(eecd & E1000_EECD_SIZE) {
3296            eeprom->word_size = 256;
3297            eeprom->address_bits = 8;
3298        } else {
3299            eeprom->word_size = 64;
3300            eeprom->address_bits = 6;
3301        }
3302        eeprom->use_eerd = FALSE;
3303        eeprom->use_eewr = FALSE;
3304        break;
3305    case em_82541:
3306    case em_82541_rev_2:
3307    case em_82547:
3308    case em_82547_rev_2:
3309        if (eecd & E1000_EECD_TYPE) {
3310            eeprom->type = em_eeprom_spi;
3311            eeprom->opcode_bits = 8;
3312            eeprom->delay_usec = 1;
3313            if (eecd & E1000_EECD_ADDR_BITS) {
3314                eeprom->page_size = 32;
3315                eeprom->address_bits = 16;
3316            } else {
3317                eeprom->page_size = 8;
3318                eeprom->address_bits = 8;
3319            }
3320        } else {
3321            eeprom->type = em_eeprom_microwire;
3322            eeprom->opcode_bits = 3;
3323            eeprom->delay_usec = 50;
3324            if (eecd & E1000_EECD_ADDR_BITS) {
3325                eeprom->word_size = 256;
3326                eeprom->address_bits = 8;
3327            } else {
3328                eeprom->word_size = 64;
3329                eeprom->address_bits = 6;
3330            }
3331        }
3332        eeprom->use_eerd = FALSE;
3333        eeprom->use_eewr = FALSE;
3334        break;
3335    case em_82573:
3336        eeprom->type = em_eeprom_spi;
3337        eeprom->opcode_bits = 8;
3338        eeprom->delay_usec = 1;
3339        if (eecd & E1000_EECD_ADDR_BITS) {
3340            eeprom->page_size = 32;
3341            eeprom->address_bits = 16;
3342        } else {
3343            eeprom->page_size = 8;
3344            eeprom->address_bits = 8;
3345        }
3346        eeprom->use_eerd = TRUE;
3347        eeprom->use_eewr = TRUE;
3348        if(em_is_onboard_nvm_eeprom(hw) == FALSE) {
3349            eeprom->type = em_eeprom_flash;
3350            eeprom->word_size = 2048;
3351
3352            /* Ensure that the Autonomous FLASH update bit is cleared due to
3353             * Flash update issue on parts which use a FLASH for NVM. */
3354            eecd &= ~E1000_EECD_AUPDEN;
3355            E1000_WRITE_REG(hw, EECD, eecd);
3356        }
3357        break;
3358    default:
3359        break;
3360    }
3361
3362    if (eeprom->type == em_eeprom_spi) {
3363        /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3364         * 32KB (incremented by powers of 2).
3365         */
3366        if(hw->mac_type <= em_82547_rev_2) {
3367            /* Set to default value for initial eeprom read. */
3368            eeprom->word_size = 64;
3369            ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3370            if(ret_val)
3371                return ret_val;
3372            eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3373            /* 256B eeprom size was not supported in earlier hardware, so we
3374             * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3375             * is never the result used in the shifting logic below. */
3376            if(eeprom_size)
3377                eeprom_size++;
3378        } else {
3379            eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3380                          E1000_EECD_SIZE_EX_SHIFT);
3381        }
3382
3383        eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3384    }
3385    return ret_val;
3386}
3387
3388/******************************************************************************
3389 * Raises the EEPROM's clock input.
3390 *
3391 * hw - Struct containing variables accessed by shared code
3392 * eecd - EECD's current value
3393 *****************************************************************************/
3394static void
3395em_raise_ee_clk(struct em_hw *hw,
3396                   uint32_t *eecd)
3397{
3398    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3399     * wait <delay> microseconds.
3400     */
3401    *eecd = *eecd | E1000_EECD_SK;
3402    E1000_WRITE_REG(hw, EECD, *eecd);
3403    E1000_WRITE_FLUSH(hw);
3404    usec_delay(hw->eeprom.delay_usec);
3405}
3406
3407/******************************************************************************
3408 * Lowers the EEPROM's clock input.
3409 *
3410 * hw - Struct containing variables accessed by shared code
3411 * eecd - EECD's current value
3412 *****************************************************************************/
3413static void
3414em_lower_ee_clk(struct em_hw *hw,
3415                   uint32_t *eecd)
3416{
3417    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3418     * wait 50 microseconds.
3419     */
3420    *eecd = *eecd & ~E1000_EECD_SK;
3421    E1000_WRITE_REG(hw, EECD, *eecd);
3422    E1000_WRITE_FLUSH(hw);
3423    usec_delay(hw->eeprom.delay_usec);
3424}
3425
3426/******************************************************************************
3427 * Shift data bits out to the EEPROM.
3428 *
3429 * hw - Struct containing variables accessed by shared code
3430 * data - data to send to the EEPROM
3431 * count - number of bits to shift out
3432 *****************************************************************************/
3433static void
3434em_shift_out_ee_bits(struct em_hw *hw,
3435                        uint16_t data,
3436                        uint16_t count)
3437{
3438    struct em_eeprom_info *eeprom = &hw->eeprom;
3439    uint32_t eecd;
3440    uint32_t mask;
3441
3442    /* We need to shift "count" bits out to the EEPROM. So, value in the
3443     * "data" parameter will be shifted out to the EEPROM one bit at a time.
3444     * In order to do this, "data" must be broken down into bits.
3445     */
3446    mask = 0x01 << (count - 1);
3447    eecd = E1000_READ_REG(hw, EECD);
3448    if (eeprom->type == em_eeprom_microwire) {
3449        eecd &= ~E1000_EECD_DO;
3450    } else if (eeprom->type == em_eeprom_spi) {
3451        eecd |= E1000_EECD_DO;
3452    }
3453    do {
3454        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3455         * and then raising and then lowering the clock (the SK bit controls
3456         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
3457         * by setting "DI" to "0" and then raising and then lowering the clock.
3458         */
3459        eecd &= ~E1000_EECD_DI;
3460
3461        if(data & mask)
3462            eecd |= E1000_EECD_DI;
3463
3464        E1000_WRITE_REG(hw, EECD, eecd);
3465        E1000_WRITE_FLUSH(hw);
3466
3467        usec_delay(eeprom->delay_usec);
3468
3469        em_raise_ee_clk(hw, &eecd);
3470        em_lower_ee_clk(hw, &eecd);
3471
3472        mask = mask >> 1;
3473
3474    } while(mask);
3475
3476    /* We leave the "DI" bit set to "0" when we leave this routine. */
3477    eecd &= ~E1000_EECD_DI;
3478    E1000_WRITE_REG(hw, EECD, eecd);
3479}
3480
3481/******************************************************************************
3482 * Shift data bits in from the EEPROM
3483 *
3484 * hw - Struct containing variables accessed by shared code
3485 *****************************************************************************/
3486static uint16_t
3487em_shift_in_ee_bits(struct em_hw *hw,
3488                       uint16_t count)
3489{
3490    uint32_t eecd;
3491    uint32_t i;
3492    uint16_t data;
3493
3494    /* In order to read a register from the EEPROM, we need to shift 'count'
3495     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3496     * input to the EEPROM (setting the SK bit), and then reading the value of
3497     * the "DO" bit.  During this "shifting in" process the "DI" bit should
3498     * always be clear.
3499     */
3500
3501    eecd = E1000_READ_REG(hw, EECD);
3502
3503    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3504    data = 0;
3505
3506    for(i = 0; i < count; i++) {
3507        data = data << 1;
3508        em_raise_ee_clk(hw, &eecd);
3509
3510        eecd = E1000_READ_REG(hw, EECD);
3511
3512        eecd &= ~(E1000_EECD_DI);
3513        if(eecd & E1000_EECD_DO)
3514            data |= 1;
3515
3516        em_lower_ee_clk(hw, &eecd);
3517    }
3518
3519    return data;
3520}
3521
3522/******************************************************************************
3523 * Prepares EEPROM for access
3524 *
3525 * hw - Struct containing variables accessed by shared code
3526 *
3527 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3528 * function should be called before issuing a command to the EEPROM.
3529 *****************************************************************************/
3530static int32_t
3531em_acquire_eeprom(struct em_hw *hw)
3532{
3533    struct em_eeprom_info *eeprom = &hw->eeprom;
3534    uint32_t eecd, i=0;
3535
3536    DEBUGFUNC("em_acquire_eeprom");
3537
3538    if(em_get_hw_eeprom_semaphore(hw))
3539        return -E1000_ERR_EEPROM;
3540
3541    eecd = E1000_READ_REG(hw, EECD);
3542
3543    if (hw->mac_type != em_82573) {
3544    /* Request EEPROM Access */
3545    if(hw->mac_type > em_82544) {
3546        eecd |= E1000_EECD_REQ;
3547        E1000_WRITE_REG(hw, EECD, eecd);
3548        eecd = E1000_READ_REG(hw, EECD);
3549        while((!(eecd & E1000_EECD_GNT)) &&
3550              (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3551            i++;
3552            usec_delay(5);
3553            eecd = E1000_READ_REG(hw, EECD);
3554        }
3555        if(!(eecd & E1000_EECD_GNT)) {
3556            eecd &= ~E1000_EECD_REQ;
3557            E1000_WRITE_REG(hw, EECD, eecd);
3558            DEBUGOUT("Could not acquire EEPROM grant\n");
3559            return -E1000_ERR_EEPROM;
3560        }
3561    }
3562    }
3563
3564    /* Setup EEPROM for Read/Write */
3565
3566    if (eeprom->type == em_eeprom_microwire) {
3567        /* Clear SK and DI */
3568        eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3569        E1000_WRITE_REG(hw, EECD, eecd);
3570
3571        /* Set CS */
3572        eecd |= E1000_EECD_CS;
3573        E1000_WRITE_REG(hw, EECD, eecd);
3574    } else if (eeprom->type == em_eeprom_spi) {
3575        /* Clear SK and CS */
3576        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3577        E1000_WRITE_REG(hw, EECD, eecd);
3578        usec_delay(1);
3579    }
3580
3581    return E1000_SUCCESS;
3582}
3583
3584/******************************************************************************
3585 * Returns EEPROM to a "standby" state
3586 *
3587 * hw - Struct containing variables accessed by shared code
3588 *****************************************************************************/
3589static void
3590em_standby_eeprom(struct em_hw *hw)
3591{
3592    struct em_eeprom_info *eeprom = &hw->eeprom;
3593    uint32_t eecd;
3594
3595    eecd = E1000_READ_REG(hw, EECD);
3596
3597    if(eeprom->type == em_eeprom_microwire) {
3598        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3599        E1000_WRITE_REG(hw, EECD, eecd);
3600        E1000_WRITE_FLUSH(hw);
3601        usec_delay(eeprom->delay_usec);
3602
3603        /* Clock high */
3604        eecd |= E1000_EECD_SK;
3605        E1000_WRITE_REG(hw, EECD, eecd);
3606        E1000_WRITE_FLUSH(hw);
3607        usec_delay(eeprom->delay_usec);
3608
3609        /* Select EEPROM */
3610        eecd |= E1000_EECD_CS;
3611        E1000_WRITE_REG(hw, EECD, eecd);
3612        E1000_WRITE_FLUSH(hw);
3613        usec_delay(eeprom->delay_usec);
3614
3615        /* Clock low */
3616        eecd &= ~E1000_EECD_SK;
3617        E1000_WRITE_REG(hw, EECD, eecd);
3618        E1000_WRITE_FLUSH(hw);
3619        usec_delay(eeprom->delay_usec);
3620    } else if(eeprom->type == em_eeprom_spi) {
3621        /* Toggle CS to flush commands */
3622        eecd |= E1000_EECD_CS;
3623        E1000_WRITE_REG(hw, EECD, eecd);
3624        E1000_WRITE_FLUSH(hw);
3625        usec_delay(eeprom->delay_usec);
3626        eecd &= ~E1000_EECD_CS;
3627        E1000_WRITE_REG(hw, EECD, eecd);
3628        E1000_WRITE_FLUSH(hw);
3629        usec_delay(eeprom->delay_usec);
3630    }
3631}
3632
3633/******************************************************************************
3634 * Terminates a command by inverting the EEPROM's chip select pin
3635 *
3636 * hw - Struct containing variables accessed by shared code
3637 *****************************************************************************/
3638static void
3639em_release_eeprom(struct em_hw *hw)
3640{
3641    uint32_t eecd;
3642
3643    DEBUGFUNC("em_release_eeprom");
3644
3645    eecd = E1000_READ_REG(hw, EECD);
3646
3647    if (hw->eeprom.type == em_eeprom_spi) {
3648        eecd |= E1000_EECD_CS;  /* Pull CS high */
3649        eecd &= ~E1000_EECD_SK; /* Lower SCK */
3650
3651        E1000_WRITE_REG(hw, EECD, eecd);
3652
3653        usec_delay(hw->eeprom.delay_usec);
3654    } else if(hw->eeprom.type == em_eeprom_microwire) {
3655        /* cleanup eeprom */
3656
3657        /* CS on Microwire is active-high */
3658        eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3659
3660        E1000_WRITE_REG(hw, EECD, eecd);
3661
3662        /* Rising edge of clock */
3663        eecd |= E1000_EECD_SK;
3664        E1000_WRITE_REG(hw, EECD, eecd);
3665        E1000_WRITE_FLUSH(hw);
3666        usec_delay(hw->eeprom.delay_usec);
3667
3668        /* Falling edge of clock */
3669        eecd &= ~E1000_EECD_SK;
3670        E1000_WRITE_REG(hw, EECD, eecd);
3671        E1000_WRITE_FLUSH(hw);
3672        usec_delay(hw->eeprom.delay_usec);
3673    }
3674
3675    /* Stop requesting EEPROM access */
3676    if(hw->mac_type > em_82544) {
3677        eecd &= ~E1000_EECD_REQ;
3678        E1000_WRITE_REG(hw, EECD, eecd);
3679    }
3680
3681    em_put_hw_eeprom_semaphore(hw);
3682}
3683
3684/******************************************************************************
3685 * Reads a 16 bit word from the EEPROM.
3686 *
3687 * hw - Struct containing variables accessed by shared code
3688 *****************************************************************************/
3689int32_t
3690em_spi_eeprom_ready(struct em_hw *hw)
3691{
3692    uint16_t retry_count = 0;
3693    uint8_t spi_stat_reg;
3694
3695    DEBUGFUNC("em_spi_eeprom_ready");
3696
3697    /* Read "Status Register" repeatedly until the LSB is cleared.  The
3698     * EEPROM will signal that the command has been completed by clearing
3699     * bit 0 of the internal status register.  If it's not cleared within
3700     * 5 milliseconds, then error out.
3701     */
3702    retry_count = 0;
3703    do {
3704        em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3705                                hw->eeprom.opcode_bits);
3706        spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3707        if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3708            break;
3709
3710        usec_delay(5);
3711        retry_count += 5;
3712
3713        em_standby_eeprom(hw);
3714    } while(retry_count < EEPROM_MAX_RETRY_SPI);
3715
3716    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3717     * only 0-5mSec on 5V devices)
3718     */
3719    if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3720        DEBUGOUT("SPI EEPROM Status error\n");
3721        return -E1000_ERR_EEPROM;
3722    }
3723
3724    return E1000_SUCCESS;
3725}
3726
3727/******************************************************************************
3728 * Reads a 16 bit word from the EEPROM.
3729 *
3730 * hw - Struct containing variables accessed by shared code
3731 * offset - offset of  word in the EEPROM to read
3732 * data - word read from the EEPROM
3733 * words - number of words to read
3734 *****************************************************************************/
3735int32_t
3736em_read_eeprom(struct em_hw *hw,
3737                  uint16_t offset,
3738                  uint16_t words,
3739                  uint16_t *data)
3740{
3741    struct em_eeprom_info *eeprom = &hw->eeprom;
3742    uint32_t i = 0;
3743    int32_t ret_val;
3744
3745    DEBUGFUNC("em_read_eeprom");
3746
3747    /* A check for invalid values:  offset too large, too many words, and not
3748     * enough words.
3749     */
3750    if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3751       (words == 0)) {
3752        DEBUGOUT("\"words\" parameter out of bounds\n");
3753        return -E1000_ERR_EEPROM;
3754    }
3755
3756    /* FLASH reads without acquiring the semaphore are safe in 82573-based
3757     * controllers.
3758     */
3759    if ((em_is_onboard_nvm_eeprom(hw) == TRUE) ||
3760        (hw->mac_type != em_82573)) {
3761        /* Prepare the EEPROM for reading  */
3762        if(em_acquire_eeprom(hw) != E1000_SUCCESS)
3763            return -E1000_ERR_EEPROM;
3764    }
3765
3766    if(eeprom->use_eerd == TRUE) {
3767        ret_val = em_read_eeprom_eerd(hw, offset, words, data);
3768        if ((em_is_onboard_nvm_eeprom(hw) == TRUE) ||
3769            (hw->mac_type != em_82573))
3770            em_release_eeprom(hw);
3771        return ret_val;
3772    }
3773
3774    if(eeprom->type == em_eeprom_spi) {
3775        uint16_t word_in;
3776        uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3777
3778        if(em_spi_eeprom_ready(hw)) {
3779            em_release_eeprom(hw);
3780            return -E1000_ERR_EEPROM;
3781        }
3782
3783        em_standby_eeprom(hw);
3784
3785        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3786        if((eeprom->address_bits == 8) && (offset >= 128))
3787            read_opcode |= EEPROM_A8_OPCODE_SPI;
3788
3789        /* Send the READ command (opcode + addr)  */
3790        em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3791        em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3792
3793        /* Read the data.  The address of the eeprom internally increments with
3794         * each byte (spi) being read, saving on the overhead of eeprom setup
3795         * and tear-down.  The address counter will roll over if reading beyond
3796         * the size of the eeprom, thus allowing the entire memory to be read
3797         * starting from any offset. */
3798        for (i = 0; i < words; i++) {
3799            word_in = em_shift_in_ee_bits(hw, 16);
3800            data[i] = (word_in >> 8) | (word_in << 8);
3801        }
3802    } else if(eeprom->type == em_eeprom_microwire) {
3803        for (i = 0; i < words; i++) {
3804            /* Send the READ command (opcode + addr)  */
3805            em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3806                                    eeprom->opcode_bits);
3807            em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3808                                    eeprom->address_bits);
3809
3810            /* Read the data.  For microwire, each word requires the overhead
3811             * of eeprom setup and tear-down. */
3812            data[i] = em_shift_in_ee_bits(hw, 16);
3813            em_standby_eeprom(hw);
3814        }
3815    }
3816
3817    /* End this read operation */
3818    em_release_eeprom(hw);
3819
3820    return E1000_SUCCESS;
3821}
3822
3823/******************************************************************************
3824 * Reads a 16 bit word from the EEPROM using the EERD register.
3825 *
3826 * hw - Struct containing variables accessed by shared code
3827 * offset - offset of  word in the EEPROM to read
3828 * data - word read from the EEPROM
3829 * words - number of words to read
3830 *****************************************************************************/
3831int32_t
3832em_read_eeprom_eerd(struct em_hw *hw,
3833                  uint16_t offset,
3834                  uint16_t words,
3835                  uint16_t *data)
3836{
3837    uint32_t i, eerd = 0;
3838    int32_t error = 0;
3839
3840    for (i = 0; i < words; i++) {
3841        eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3842                         E1000_EEPROM_RW_REG_START;
3843
3844        E1000_WRITE_REG(hw, EERD, eerd);
3845        error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3846       
3847        if(error) {
3848            break;
3849        }
3850        data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3851     
3852    }
3853   
3854    return error;
3855}
3856
3857/******************************************************************************
3858 * Writes a 16 bit word from the EEPROM using the EEWR register.
3859 *
3860 * hw - Struct containing variables accessed by shared code
3861 * offset - offset of  word in the EEPROM to read
3862 * data - word read from the EEPROM
3863 * words - number of words to read
3864 *****************************************************************************/
3865int32_t
3866em_write_eeprom_eewr(struct em_hw *hw,
3867                   uint16_t offset,
3868                   uint16_t words,
3869                   uint16_t *data)
3870{
3871    uint32_t    register_value = 0;
3872    uint32_t    i              = 0;
3873    int32_t     error          = 0;
3874
3875    for (i = 0; i < words; i++) {
3876        register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 
3877                         ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | 
3878                         E1000_EEPROM_RW_REG_START;
3879
3880        error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3881        if(error) {
3882            break;
3883        }       
3884
3885        E1000_WRITE_REG(hw, EEWR, register_value);
3886       
3887        error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3888       
3889        if(error) {
3890            break;
3891        }       
3892    }
3893   
3894    return error;
3895}
3896
3897/******************************************************************************
3898 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3899 *
3900 * hw - Struct containing variables accessed by shared code
3901 *****************************************************************************/
3902int32_t
3903em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
3904{
3905    uint32_t attempts = 100000;
3906    uint32_t i, reg = 0;
3907    int32_t done = E1000_ERR_EEPROM;
3908
3909    for(i = 0; i < attempts; i++) {
3910        if(eerd == E1000_EEPROM_POLL_READ)
3911            reg = E1000_READ_REG(hw, EERD);
3912        else 
3913            reg = E1000_READ_REG(hw, EEWR);
3914
3915        if(reg & E1000_EEPROM_RW_REG_DONE) {
3916            done = E1000_SUCCESS;
3917            break;
3918        }
3919        usec_delay(5);
3920    }
3921
3922    return done;
3923}
3924
3925/***************************************************************************
3926* Description:     Determines if the onboard NVM is FLASH or EEPROM.
3927*
3928* hw - Struct containing variables accessed by shared code
3929****************************************************************************/
3930boolean_t
3931em_is_onboard_nvm_eeprom(struct em_hw *hw)
3932{
3933    uint32_t eecd = 0;
3934
3935    if(hw->mac_type == em_82573) {
3936        eecd = E1000_READ_REG(hw, EECD);
3937
3938        /* Isolate bits 15 & 16 */
3939        eecd = ((eecd >> 15) & 0x03);
3940
3941        /* If both bits are set, device is Flash type */
3942        if(eecd == 0x03) {
3943            return FALSE;
3944        }
3945    }
3946    return TRUE;
3947}
3948
3949/******************************************************************************
3950 * Verifies that the EEPROM has a valid checksum
3951 *
3952 * hw - Struct containing variables accessed by shared code
3953 *
3954 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3955 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3956 * valid.
3957 *****************************************************************************/
3958int32_t
3959em_validate_eeprom_checksum(struct em_hw *hw)
3960{
3961    uint16_t checksum = 0;
3962    uint16_t i, eeprom_data;
3963
3964    DEBUGFUNC("em_validate_eeprom_checksum");
3965
3966    if ((hw->mac_type == em_82573) &&
3967        (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
3968        /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
3969         * 10h-12h.  Checksum may need to be fixed. */
3970        em_read_eeprom(hw, 0x10, 1, &eeprom_data);
3971        if ((eeprom_data & 0x10) == 0) {
3972            /* Read 0x23 and check bit 15.  This bit is a 1 when the checksum
3973             * has already been fixed.  If the checksum is still wrong and this
3974             * bit is a 1, we need to return bad checksum.  Otherwise, we need
3975             * to set this bit to a 1 and update the checksum. */
3976            em_read_eeprom(hw, 0x23, 1, &eeprom_data);
3977            if ((eeprom_data & 0x8000) == 0) {
3978                eeprom_data |= 0x8000;
3979                em_write_eeprom(hw, 0x23, 1, &eeprom_data);
3980                em_update_eeprom_checksum(hw);
3981            }
3982        }
3983    }
3984
3985    for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3986        if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3987            DEBUGOUT("EEPROM Read Error\n");
3988            return -E1000_ERR_EEPROM;
3989        }
3990        checksum += eeprom_data;
3991    }
3992
3993    if(checksum == (uint16_t) EEPROM_SUM)
3994        return E1000_SUCCESS;
3995    else {
3996        DEBUGOUT("EEPROM Checksum Invalid\n");
3997        return -E1000_ERR_EEPROM;
3998    }
3999}
4000
4001/******************************************************************************
4002 * Calculates the EEPROM checksum and writes it to the EEPROM
4003 *
4004 * hw - Struct containing variables accessed by shared code
4005 *
4006 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4007 * Writes the difference to word offset 63 of the EEPROM.
4008 *****************************************************************************/
4009int32_t
4010em_update_eeprom_checksum(struct em_hw *hw)
4011{
4012    uint16_t checksum = 0;
4013    uint16_t i, eeprom_data;
4014
4015    DEBUGFUNC("em_update_eeprom_checksum");
4016
4017    for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4018        if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4019            DEBUGOUT("EEPROM Read Error\n");
4020            return -E1000_ERR_EEPROM;
4021        }
4022        checksum += eeprom_data;
4023    }
4024    checksum = (uint16_t) EEPROM_SUM - checksum;
4025    if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4026        DEBUGOUT("EEPROM Write Error\n");
4027        return -E1000_ERR_EEPROM;
4028    } else if (hw->eeprom.type == em_eeprom_flash) {
4029        em_commit_shadow_ram(hw);
4030    }
4031    return E1000_SUCCESS;
4032}
4033
4034/******************************************************************************
4035 * Parent function for writing words to the different EEPROM types.
4036 *
4037 * hw - Struct containing variables accessed by shared code
4038 * offset - offset within the EEPROM to be written to
4039 * words - number of words to write
4040 * data - 16 bit word to be written to the EEPROM
4041 *
4042 * If em_update_eeprom_checksum is not called after this function, the
4043 * EEPROM will most likely contain an invalid checksum.
4044 *****************************************************************************/
4045int32_t
4046em_write_eeprom(struct em_hw *hw,
4047                   uint16_t offset,
4048                   uint16_t words,
4049                   uint16_t *data)
4050{
4051    struct em_eeprom_info *eeprom = &hw->eeprom;
4052    int32_t status = 0;
4053
4054    DEBUGFUNC("em_write_eeprom");
4055
4056    /* A check for invalid values:  offset too large, too many words, and not
4057     * enough words.
4058     */
4059    if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4060       (words == 0)) {
4061        DEBUGOUT("\"words\" parameter out of bounds\n");
4062        return -E1000_ERR_EEPROM;
4063    }
4064
4065    /* 82573 reads only through eerd */
4066    if(eeprom->use_eewr == TRUE)
4067        return em_write_eeprom_eewr(hw, offset, words, data);
4068
4069    /* Prepare the EEPROM for writing  */
4070    if (em_acquire_eeprom(hw) != E1000_SUCCESS)
4071        return -E1000_ERR_EEPROM;
4072
4073    if(eeprom->type == em_eeprom_microwire) {
4074        status = em_write_eeprom_microwire(hw, offset, words, data);
4075    } else {
4076        status = em_write_eeprom_spi(hw, offset, words, data);
4077        msec_delay(10);
4078    }
4079
4080    /* Done with writing */
4081    em_release_eeprom(hw);
4082
4083    return status;
4084}
4085
4086/******************************************************************************
4087 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4088 *
4089 * hw - Struct containing variables accessed by shared code
4090 * offset - offset within the EEPROM to be written to
4091 * words - number of words to write
4092 * data - pointer to array of 8 bit words to be written to the EEPROM
4093 *
4094 *****************************************************************************/
4095int32_t
4096em_write_eeprom_spi(struct em_hw *hw,
4097                       uint16_t offset,
4098                       uint16_t words,
4099                       uint16_t *data)
4100{
4101    struct em_eeprom_info *eeprom = &hw->eeprom;
4102    uint16_t widx = 0;
4103
4104    DEBUGFUNC("em_write_eeprom_spi");
4105
4106    while (widx < words) {
4107        uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
4108
4109        if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
4110
4111        em_standby_eeprom(hw);
4112
4113        /*  Send the WRITE ENABLE command (8 bit opcode )  */
4114        em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4115                                    eeprom->opcode_bits);
4116
4117        em_standby_eeprom(hw);
4118
4119        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4120        if((eeprom->address_bits == 8) && (offset >= 128))
4121            write_opcode |= EEPROM_A8_OPCODE_SPI;
4122
4123        /* Send the Write command (8-bit opcode + addr) */
4124        em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4125
4126        em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
4127                                eeprom->address_bits);
4128
4129        /* Send the data */
4130
4131        /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4132        while (widx < words) {
4133            uint16_t word_out = data[widx];
4134            word_out = (word_out >> 8) | (word_out << 8);
4135            em_shift_out_ee_bits(hw, word_out, 16);
4136            widx++;
4137
4138            /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4139             * operation, while the smaller eeproms are capable of an 8-byte
4140             * PAGE WRITE operation.  Break the inner loop to pass new address
4141             */
4142            if((((offset + widx)*2) % eeprom->page_size) == 0) {
4143                em_standby_eeprom(hw);
4144                break;
4145            }
4146        }
4147    }
4148
4149    return E1000_SUCCESS;
4150}
4151
4152/******************************************************************************
4153 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4154 *
4155 * hw - Struct containing variables accessed by shared code
4156 * offset - offset within the EEPROM to be written to
4157 * words - number of words to write
4158 * data - pointer to array of 16 bit words to be written to the EEPROM
4159 *
4160 *****************************************************************************/
4161int32_t
4162em_write_eeprom_microwire(struct em_hw *hw,
4163                             uint16_t offset,
4164                             uint16_t words,
4165                             uint16_t *data)
4166{
4167    struct em_eeprom_info *eeprom = &hw->eeprom;
4168    uint32_t eecd;
4169    uint16_t words_written = 0;
4170    uint16_t i = 0;
4171
4172    DEBUGFUNC("em_write_eeprom_microwire");
4173
4174    /* Send the write enable command to the EEPROM (3-bit opcode plus
4175     * 6/8-bit dummy address beginning with 11).  It's less work to include
4176     * the 11 of the dummy address as part of the opcode than it is to shift
4177     * it over the correct number of bits for the address.  This puts the
4178     * EEPROM into write/erase mode.
4179     */
4180    em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4181                            (uint16_t)(eeprom->opcode_bits + 2));
4182
4183    em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4184
4185    /* Prepare the EEPROM */
4186    em_standby_eeprom(hw);
4187
4188    while (words_written < words) {
4189        /* Send the Write command (3-bit opcode + addr) */
4190        em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4191                                eeprom->opcode_bits);
4192
4193        em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
4194                                eeprom->address_bits);
4195
4196        /* Send the data */
4197        em_shift_out_ee_bits(hw, data[words_written], 16);
4198
4199        /* Toggle the CS line.  This in effect tells the EEPROM to execute
4200         * the previous command.
4201         */
4202        em_standby_eeprom(hw);
4203
4204        /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
4205         * signal that the command has been completed by raising the DO signal.
4206         * If DO does not go high in 10 milliseconds, then error out.
4207         */
4208        for(i = 0; i < 200; i++) {
4209            eecd = E1000_READ_REG(hw, EECD);
4210            if(eecd & E1000_EECD_DO) break;
4211            usec_delay(50);
4212        }
4213        if(i == 200) {
4214            DEBUGOUT("EEPROM Write did not complete\n");
4215            return -E1000_ERR_EEPROM;
4216        }
4217
4218        /* Recover from write */
4219        em_standby_eeprom(hw);
4220
4221        words_written++;
4222    }
4223
4224    /* Send the write disable command to the EEPROM (3-bit opcode plus
4225     * 6/8-bit dummy address beginning with 10).  It's less work to include
4226     * the 10 of the dummy address as part of the opcode than it is to shift
4227     * it over the correct number of bits for the address.  This takes the
4228     * EEPROM out of write/erase mode.
4229     */
4230    em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4231                            (uint16_t)(eeprom->opcode_bits + 2));
4232
4233    em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4234
4235    return E1000_SUCCESS;
4236}
4237
4238/******************************************************************************
4239 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4240 * in the eeprom cache and the non modified values in the currently active bank
4241 * to the new bank.
4242 *
4243 * hw - Struct containing variables accessed by shared code
4244 * offset - offset of  word in the EEPROM to read
4245 * data - word read from the EEPROM
4246 * words - number of words to read
4247 *****************************************************************************/
4248int32_t
4249em_commit_shadow_ram(struct em_hw *hw)
4250{
4251    uint32_t attempts = 100000;
4252    uint32_t eecd = 0;
4253    uint32_t flop = 0;
4254    uint32_t i = 0;
4255    int32_t error = E1000_SUCCESS;
4256
4257    /* The flop register will be used to determine if flash type is STM */
4258    flop = E1000_READ_REG(hw, FLOP);
4259
4260    if (hw->mac_type == em_82573) {
4261        for (i=0; i < attempts; i++) {
4262            eecd = E1000_READ_REG(hw, EECD);
4263            if ((eecd & E1000_EECD_FLUPD) == 0) {
4264                break;
4265            }
4266            usec_delay(5);
4267        }
4268
4269        if (i == attempts) {
4270            return -E1000_ERR_EEPROM;
4271        }
4272
4273        /* If STM opcode located in bits 15:8 of flop, reset firmware */
4274        if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4275            E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4276        }
4277
4278        /* Perform the flash update */
4279        E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4280
4281        for (i=0; i < attempts; i++) {
4282            eecd = E1000_READ_REG(hw, EECD);
4283            if ((eecd & E1000_EECD_FLUPD) == 0) {
4284                break;
4285            }
4286            usec_delay(5);
4287        }
4288
4289        if (i == attempts) {
4290            return -E1000_ERR_EEPROM;
4291        }
4292    }
4293
4294    return error;
4295}
4296
4297/******************************************************************************
4298 * Reads the adapter's part number from the EEPROM
4299 *
4300 * hw - Struct containing variables accessed by shared code
4301 * part_num - Adapter's part number
4302 *****************************************************************************/
4303int32_t
4304em_read_part_num(struct em_hw *hw,
4305                    uint32_t *part_num)
4306{
4307    uint16_t offset = EEPROM_PBA_BYTE_1;
4308    uint16_t eeprom_data;
4309
4310    DEBUGFUNC("em_read_part_num");
4311
4312    /* Get word 0 from EEPROM */
4313    if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4314        DEBUGOUT("EEPROM Read Error\n");
4315        return -E1000_ERR_EEPROM;
4316    }
4317    /* Save word 0 in upper half of part_num */
4318    *part_num = (uint32_t) (eeprom_data << 16);
4319
4320    /* Get word 1 from EEPROM */
4321    if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
4322        DEBUGOUT("EEPROM Read Error\n");
4323        return -E1000_ERR_EEPROM;
4324    }
4325    /* Save word 1 in lower half of part_num */
4326    *part_num |= eeprom_data;
4327
4328    return E1000_SUCCESS;
4329}
4330
4331/******************************************************************************
4332 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4333 * second function of dual function devices
4334 *
4335 * hw - Struct containing variables accessed by shared code
4336 *****************************************************************************/
4337int32_t
4338em_read_mac_addr(struct em_hw * hw)
4339{
4340    uint16_t offset;
4341    uint16_t eeprom_data, i;
4342
4343    DEBUGFUNC("em_read_mac_addr");
4344
4345    for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4346        offset = i >> 1;
4347        if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4348            DEBUGOUT("EEPROM Read Error\n");
4349            return -E1000_ERR_EEPROM;
4350        }
4351        hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
4352        hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
4353    }
4354    if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) &&
4355       (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
4356            hw->perm_mac_addr[5] ^= 0x01;
4357
4358    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
4359        hw->mac_addr[i] = hw->perm_mac_addr[i];
4360    return E1000_SUCCESS;
4361}
4362
4363/******************************************************************************
4364 * Initializes receive address filters.
4365 *
4366 * hw - Struct containing variables accessed by shared code
4367 *
4368 * Places the MAC address in receive address register 0 and clears the rest
4369 * of the receive addresss registers. Clears the multicast table. Assumes
4370 * the receiver is in reset when the routine is called.
4371 *****************************************************************************/
4372void
4373em_init_rx_addrs(struct em_hw *hw)
4374{
4375    uint32_t i;
4376    uint32_t rar_num;
4377
4378    DEBUGFUNC("em_init_rx_addrs");
4379
4380    /* Setup the receive address. */
4381    DEBUGOUT("Programming MAC Address into RAR[0]\n");
4382
4383    em_rar_set(hw, hw->mac_addr, 0);
4384
4385    rar_num = E1000_RAR_ENTRIES;
4386    /* Zero out the other 15 receive addresses. */
4387    DEBUGOUT("Clearing RAR[1-15]\n");
4388    for(i = 1; i < rar_num; i++) {
4389        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4390        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4391    }
4392}
4393
4394/******************************************************************************
4395 * Updates the MAC's list of multicast addresses.
4396 *
4397 * hw - Struct containing variables accessed by shared code
4398 * mc_addr_list - the list of new multicast addresses
4399 * mc_addr_count - number of addresses
4400 * pad - number of bytes between addresses in the list
4401 * rar_used_count - offset where to start adding mc addresses into the RAR's
4402 *
4403 * The given list replaces any existing list. Clears the last 15 receive
4404 * address registers and the multicast table. Uses receive address registers
4405 * for the first 15 multicast addresses, and hashes the rest into the
4406 * multicast table.
4407 *****************************************************************************/
4408void
4409em_mc_addr_list_update(struct em_hw *hw,
4410                          uint8_t *mc_addr_list,
4411                          uint32_t mc_addr_count,
4412                          uint32_t pad,
4413                          uint32_t rar_used_count)
4414{
4415    uint32_t hash_value;
4416    uint32_t i;
4417    uint32_t num_rar_entry;
4418    uint32_t num_mta_entry;
4419   
4420    DEBUGFUNC("em_mc_addr_list_update");
4421
4422    /* Set the new number of MC addresses that we are being requested to use. */
4423    hw->num_mc_addrs = mc_addr_count;
4424
4425    /* Clear RAR[1-15] */
4426    DEBUGOUT(" Clearing RAR[1-15]\n");
4427    num_rar_entry = E1000_RAR_ENTRIES;
4428    for(i = rar_used_count; i < num_rar_entry; i++) {
4429        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4430        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4431    }
4432
4433    /* Clear the MTA */
4434    DEBUGOUT(" Clearing MTA\n");
4435    num_mta_entry = E1000_NUM_MTA_REGISTERS;
4436    for(i = 0; i < num_mta_entry; i++) {
4437        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4438    }
4439
4440    /* Add the new addresses */
4441    for(i = 0; i < mc_addr_count; i++) {
4442        DEBUGOUT(" Adding the multicast addresses:\n");
4443        DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
4444                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
4445                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
4446                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
4447                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
4448                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
4449                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
4450
4451        hash_value = em_hash_mc_addr(hw,
4452                                        mc_addr_list +
4453                                        (i * (ETH_LENGTH_OF_ADDRESS + pad)));
4454
4455        DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
4456
4457        /* Place this multicast address in the RAR if there is room, *
4458         * else put it in the MTA
4459         */
4460        if (rar_used_count < num_rar_entry) {
4461            em_rar_set(hw,
4462                          mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
4463                          rar_used_count);
4464            rar_used_count++;
4465        } else {
4466            em_mta_set(hw, hash_value);
4467        }
4468    }
4469    DEBUGOUT("MC Update Complete\n");
4470}
4471
4472/******************************************************************************
4473 * Hashes an address to determine its location in the multicast table
4474 *
4475 * hw - Struct containing variables accessed by shared code
4476 * mc_addr - the multicast address to hash
4477 *****************************************************************************/
4478uint32_t
4479em_hash_mc_addr(struct em_hw *hw,
4480                   uint8_t *mc_addr)
4481{
4482    uint32_t hash_value = 0;
4483
4484    /* The portion of the address that is used for the hash table is
4485     * determined by the mc_filter_type setting.
4486     */
4487    switch (hw->mc_filter_type) {
4488    /* [0] [1] [2] [3] [4] [5]
4489     * 01  AA  00  12  34  56
4490     * LSB                 MSB
4491     */
4492    case 0:
4493        /* [47:36] i.e. 0x563 for above example address */
4494        hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
4495        break;
4496    case 1:
4497        /* [46:35] i.e. 0xAC6 for above example address */
4498        hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
4499        break;
4500    case 2:
4501        /* [45:34] i.e. 0x5D8 for above example address */
4502        hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
4503        break;
4504    case 3:
4505        /* [43:32] i.e. 0x634 for above example address */
4506        hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
4507        break;
4508    }
4509
4510    hash_value &= 0xFFF;
4511
4512    return hash_value;
4513}
4514
4515/******************************************************************************
4516 * Sets the bit in the multicast table corresponding to the hash value.
4517 *
4518 * hw - Struct containing variables accessed by shared code
4519 * hash_value - Multicast address hash value
4520 *****************************************************************************/
4521void
4522em_mta_set(struct em_hw *hw,
4523              uint32_t hash_value)
4524{
4525    uint32_t hash_bit, hash_reg;
4526    uint32_t mta;
4527    uint32_t temp;
4528
4529    /* The MTA is a register array of 128 32-bit registers.
4530     * It is treated like an array of 4096 bits.  We want to set
4531     * bit BitArray[hash_value]. So we figure out what register
4532     * the bit is in, read it, OR in the new bit, then write
4533     * back the new value.  The register is determined by the
4534     * upper 7 bits of the hash value and the bit within that
4535     * register are determined by the lower 5 bits of the value.
4536     */
4537    hash_reg = (hash_value >> 5) & 0x7F;
4538    hash_bit = hash_value & 0x1F;
4539
4540    mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4541
4542    mta |= (1 << hash_bit);
4543
4544    /* If we are on an 82544 and we are trying to write an odd offset
4545     * in the MTA, save off the previous entry before writing and
4546     * restore the old value after writing.
4547     */
4548    if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
4549        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4550        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4551        E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4552    } else {
4553        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4554    }
4555}
4556
4557/******************************************************************************
4558 * Puts an ethernet address into a receive address register.
4559 *
4560 * hw - Struct containing variables accessed by shared code
4561 * addr - Address to put into receive address register
4562 * index - Receive address register to write
4563 *****************************************************************************/
4564void
4565em_rar_set(struct em_hw *hw,
4566              uint8_t *addr,
4567              uint32_t index)
4568{
4569    uint32_t rar_low, rar_high;
4570
4571    /* HW expects these in little endian so we reverse the byte order
4572     * from network order (big endian) to little endian
4573     */
4574    rar_low = ((uint32_t) addr[0] |
4575               ((uint32_t) addr[1] << 8) |
4576               ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4577
4578    rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4579
4580    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4581    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4582}
4583
4584/******************************************************************************
4585 * Writes a value to the specified offset in the VLAN filter table.
4586 *
4587 * hw - Struct containing variables accessed by shared code
4588 * offset - Offset in VLAN filer table to write
4589 * value - Value to write into VLAN filter table
4590 *****************************************************************************/
4591void
4592em_write_vfta(struct em_hw *hw,
4593                 uint32_t offset,
4594                 uint32_t value)
4595{
4596    uint32_t temp;
4597
4598    if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
4599        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4600        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4601        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4602    } else {
4603        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4604    }
4605}
4606
4607/******************************************************************************
4608 * Clears the VLAN filer table
4609 *
4610 * hw - Struct containing variables accessed by shared code
4611 *****************************************************************************/
4612void
4613em_clear_vfta(struct em_hw *hw)
4614{
4615    uint32_t offset;
4616    uint32_t vfta_value = 0;
4617    uint32_t vfta_offset = 0;
4618    uint32_t vfta_bit_in_reg = 0;
4619
4620    if (hw->mac_type == em_82573) {
4621        if (hw->mng_cookie.vlan_id != 0) {
4622            /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4623             * ID.  The following operations determine which 32b entry
4624             * (i.e. offset) into the array we want to set the VLAN ID
4625             * (i.e. bit) of the manageability unit. */
4626            vfta_offset = (hw->mng_cookie.vlan_id >>
4627                           E1000_VFTA_ENTRY_SHIFT) &
4628                          E1000_VFTA_ENTRY_MASK;
4629            vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4630                                    E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4631        }
4632    }
4633    for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4634        /* If the offset we want to clear is the same offset of the
4635         * manageability VLAN ID, then clear all bits except that of the
4636         * manageability unit */
4637        vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4638        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4639    }
4640}
4641
4642int32_t
4643em_id_led_init(struct em_hw * hw)
4644{
4645    uint32_t ledctl;
4646    const uint32_t ledctl_mask = 0x000000FF;
4647    const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4648    const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4649    uint16_t eeprom_data, i, temp;
4650    const uint16_t led_mask = 0x0F;
4651
4652    DEBUGFUNC("em_id_led_init");
4653
4654    if(hw->mac_type < em_82540) {
4655        /* Nothing to do */
4656        return E1000_SUCCESS;
4657    }
4658
4659    ledctl = E1000_READ_REG(hw, LEDCTL);
4660    hw->ledctl_default = ledctl;
4661    hw->ledctl_mode1 = hw->ledctl_default;
4662    hw->ledctl_mode2 = hw->ledctl_default;
4663
4664    if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4665        DEBUGOUT("EEPROM Read Error\n");
4666        return -E1000_ERR_EEPROM;
4667    }
4668    if((eeprom_data== ID_LED_RESERVED_0000) ||
4669       (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4670    for(i = 0; i < 4; i++) {
4671        temp = (eeprom_data >> (i << 2)) & led_mask;
4672        switch(temp) {
4673        case ID_LED_ON1_DEF2:
4674        case ID_LED_ON1_ON2:
4675        case ID_LED_ON1_OFF2:
4676            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4677            hw->ledctl_mode1 |= ledctl_on << (i << 3);
4678            break;
4679        case ID_LED_OFF1_DEF2:
4680        case ID_LED_OFF1_ON2:
4681        case ID_LED_OFF1_OFF2:
4682            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4683            hw->ledctl_mode1 |= ledctl_off << (i << 3);
4684            break;
4685        default:
4686            /* Do nothing */
4687            break;
4688        }
4689        switch(temp) {
4690        case ID_LED_DEF1_ON2:
4691        case ID_LED_ON1_ON2:
4692        case ID_LED_OFF1_ON2:
4693            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4694            hw->ledctl_mode2 |= ledctl_on << (i << 3);
4695            break;
4696        case ID_LED_DEF1_OFF2:
4697        case ID_LED_ON1_OFF2:
4698        case ID_LED_OFF1_OFF2:
4699            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4700            hw->ledctl_mode2 |= ledctl_off << (i << 3);
4701            break;
4702        default:
4703            /* Do nothing */
4704            break;
4705        }
4706    }
4707    return E1000_SUCCESS;
4708}
4709
4710/******************************************************************************
4711 * Prepares SW controlable LED for use and saves the current state of the LED.
4712 *
4713 * hw - Struct containing variables accessed by shared code
4714 *****************************************************************************/
4715int32_t
4716em_setup_led(struct em_hw *hw)
4717{
4718    uint32_t ledctl;
4719    int32_t ret_val = E1000_SUCCESS;
4720
4721    DEBUGFUNC("em_setup_led");
4722
4723    switch(hw->mac_type) {
4724    case em_82542_rev2_0:
4725    case em_82542_rev2_1:
4726    case em_82543:
4727    case em_82544:
4728        /* No setup necessary */
4729        break;
4730    case em_82541:
4731    case em_82547:
4732    case em_82541_rev_2:
4733    case em_82547_rev_2:
4734        /* Turn off PHY Smart Power Down (if enabled) */
4735        ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4736                                     &hw->phy_spd_default);
4737        if(ret_val)
4738            return ret_val;
4739        ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4740                                      (uint16_t)(hw->phy_spd_default &
4741                                      ~IGP01E1000_GMII_SPD));
4742        if(ret_val)
4743            return ret_val;
4744        /* Fall Through */
4745    default:
4746        if(hw->media_type == em_media_type_fiber) {
4747            ledctl = E1000_READ_REG(hw, LEDCTL);
4748            /* Save current LEDCTL settings */
4749            hw->ledctl_default = ledctl;
4750            /* Turn off LED0 */
4751            ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4752                        E1000_LEDCTL_LED0_BLINK |
4753                        E1000_LEDCTL_LED0_MODE_MASK);
4754            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4755                       E1000_LEDCTL_LED0_MODE_SHIFT);
4756            E1000_WRITE_REG(hw, LEDCTL, ledctl);
4757        } else if(hw->media_type == em_media_type_copper)
4758            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4759        break;
4760    }
4761
4762    return E1000_SUCCESS;
4763}
4764
4765/******************************************************************************
4766 * Restores the saved state of the SW controlable LED.
4767 *
4768 * hw - Struct containing variables accessed by shared code
4769 *****************************************************************************/
4770int32_t
4771em_cleanup_led(struct em_hw *hw)
4772{
4773    int32_t ret_val = E1000_SUCCESS;
4774
4775    DEBUGFUNC("em_cleanup_led");
4776
4777    switch(hw->mac_type) {
4778    case em_82542_rev2_0:
4779    case em_82542_rev2_1:
4780    case em_82543:
4781    case em_82544:
4782        /* No cleanup necessary */
4783        break;
4784    case em_82541:
4785    case em_82547:
4786    case em_82541_rev_2:
4787    case em_82547_rev_2:
4788        /* Turn on PHY Smart Power Down (if previously enabled) */
4789        ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4790                                      hw->phy_spd_default);
4791        if(ret_val)
4792            return ret_val;
4793        /* Fall Through */
4794    default:
4795        /* Restore LEDCTL settings */
4796        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4797        break;
4798    }
4799
4800    return E1000_SUCCESS;
4801}
4802
4803/******************************************************************************
4804 * Turns on the software controllable LED
4805 *
4806 * hw - Struct containing variables accessed by shared code
4807 *****************************************************************************/
4808int32_t
4809em_led_on(struct em_hw *hw)
4810{
4811    uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4812
4813    DEBUGFUNC("em_led_on");
4814
4815    switch(hw->mac_type) {
4816    case em_82542_rev2_0:
4817    case em_82542_rev2_1:
4818    case em_82543:
4819        /* Set SW Defineable Pin 0 to turn on the LED */
4820        ctrl |= E1000_CTRL_SWDPIN0;
4821        ctrl |= E1000_CTRL_SWDPIO0;
4822        break;
4823    case em_82544:
4824        if(hw->media_type == em_media_type_fiber) {
4825            /* Set SW Defineable Pin 0 to turn on the LED */
4826            ctrl |= E1000_CTRL_SWDPIN0;
4827            ctrl |= E1000_CTRL_SWDPIO0;
4828        } else {
4829            /* Clear SW Defineable Pin 0 to turn on the LED */
4830            ctrl &= ~E1000_CTRL_SWDPIN0;
4831            ctrl |= E1000_CTRL_SWDPIO0;
4832        }
4833        break;
4834    default:
4835        if(hw->media_type == em_media_type_fiber) {
4836            /* Clear SW Defineable Pin 0 to turn on the LED */
4837            ctrl &= ~E1000_CTRL_SWDPIN0;
4838            ctrl |= E1000_CTRL_SWDPIO0;
4839        } else if(hw->media_type == em_media_type_copper) {
4840            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4841            return E1000_SUCCESS;
4842        }
4843        break;
4844    }
4845
4846    E1000_WRITE_REG(hw, CTRL, ctrl);
4847
4848    return E1000_SUCCESS;
4849}
4850
4851/******************************************************************************
4852 * Turns off the software controllable LED
4853 *
4854 * hw - Struct containing variables accessed by shared code
4855 *****************************************************************************/
4856int32_t
4857em_led_off(struct em_hw *hw)
4858{
4859    uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4860
4861    DEBUGFUNC("em_led_off");
4862
4863    switch(hw->mac_type) {
4864    case em_82542_rev2_0:
4865    case em_82542_rev2_1:
4866    case em_82543:
4867        /* Clear SW Defineable Pin 0 to turn off the LED */
4868        ctrl &= ~E1000_CTRL_SWDPIN0;
4869        ctrl |= E1000_CTRL_SWDPIO0;
4870        break;
4871    case em_82544:
4872        if(hw->media_type == em_media_type_fiber) {
4873            /* Clear SW Defineable Pin 0 to turn off the LED */
4874            ctrl &= ~E1000_CTRL_SWDPIN0;
4875            ctrl |= E1000_CTRL_SWDPIO0;
4876        } else {
4877            /* Set SW Defineable Pin 0 to turn off the LED */
4878            ctrl |= E1000_CTRL_SWDPIN0;
4879            ctrl |= E1000_CTRL_SWDPIO0;
4880        }
4881        break;
4882    default:
4883        if(hw->media_type == em_media_type_fiber) {
4884            /* Set SW Defineable Pin 0 to turn off the LED */
4885            ctrl |= E1000_CTRL_SWDPIN0;
4886            ctrl |= E1000_CTRL_SWDPIO0;
4887        } else if(hw->media_type == em_media_type_copper) {
4888            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4889            return E1000_SUCCESS;
4890        }
4891        break;
4892    }
4893
4894    E1000_WRITE_REG(hw, CTRL, ctrl);
4895
4896    return E1000_SUCCESS;
4897}
4898
4899/******************************************************************************
4900 * Clears all hardware statistics counters.
4901 *
4902 * hw - Struct containing variables accessed by shared code
4903 *****************************************************************************/
4904void
4905em_clear_hw_cntrs(struct em_hw *hw)
4906{
4907    E1000_READ_REG(hw, CRCERRS);
4908    E1000_READ_REG(hw, SYMERRS);
4909    E1000_READ_REG(hw, MPC);
4910    E1000_READ_REG(hw, SCC);
4911    E1000_READ_REG(hw, ECOL);
4912    E1000_READ_REG(hw, MCC);
4913    E1000_READ_REG(hw, LATECOL);
4914    E1000_READ_REG(hw, COLC);
4915    E1000_READ_REG(hw, DC);
4916    E1000_READ_REG(hw, SEC);
4917    E1000_READ_REG(hw, RLEC);
4918    E1000_READ_REG(hw, XONRXC);
4919    E1000_READ_REG(hw, XONTXC);
4920    E1000_READ_REG(hw, XOFFRXC);
4921    E1000_READ_REG(hw, XOFFTXC);
4922    E1000_READ_REG(hw, FCRUC);
4923    E1000_READ_REG(hw, PRC64);
4924    E1000_READ_REG(hw, PRC127);
4925    E1000_READ_REG(hw, PRC255);
4926    E1000_READ_REG(hw, PRC511);
4927    E1000_READ_REG(hw, PRC1023);
4928    E1000_READ_REG(hw, PRC1522);
4929    E1000_READ_REG(hw, GPRC);
4930    E1000_READ_REG(hw, BPRC);
4931    E1000_READ_REG(hw, MPRC);
4932    E1000_READ_REG(hw, GPTC);
4933    E1000_READ_REG(hw, GORCL);
4934    E1000_READ_REG(hw, GORCH);
4935    E1000_READ_REG(hw, GOTCL);
4936    E1000_READ_REG(hw, GOTCH);
4937    E1000_READ_REG(hw, RNBC);
4938    E1000_READ_REG(hw, RUC);
4939    E1000_READ_REG(hw, RFC);
4940    E1000_READ_REG(hw, ROC);
4941    E1000_READ_REG(hw, RJC);
4942    E1000_READ_REG(hw, TORL);
4943    E1000_READ_REG(hw, TORH);
4944    E1000_READ_REG(hw, TOTL);
4945    E1000_READ_REG(hw, TOTH);
4946    E1000_READ_REG(hw, TPR);
4947    E1000_READ_REG(hw, TPT);
4948    E1000_READ_REG(hw, PTC64);
4949    E1000_READ_REG(hw, PTC127);
4950    E1000_READ_REG(hw, PTC255);
4951    E1000_READ_REG(hw, PTC511);
4952    E1000_READ_REG(hw, PTC1023);
4953    E1000_READ_REG(hw, PTC1522);
4954    E1000_READ_REG(hw, MPTC);
4955    E1000_READ_REG(hw, BPTC);
4956
4957    if(hw->mac_type < em_82543) return;
4958
4959    E1000_READ_REG(hw, ALGNERRC);
4960    E1000_READ_REG(hw, RXERRC);
4961    E1000_READ_REG(hw, TNCRS);
4962    E1000_READ_REG(hw, CEXTERR);
4963    E1000_READ_REG(hw, TSCTC);
4964    E1000_READ_REG(hw, TSCTFC);
4965
4966    if(hw->mac_type <= em_82544) return;
4967
4968    E1000_READ_REG(hw, MGTPRC);
4969    E1000_READ_REG(hw, MGTPDC);
4970    E1000_READ_REG(hw, MGTPTC);
4971
4972    if(hw->mac_type <= em_82547_rev_2) return;
4973
4974    E1000_READ_REG(hw, IAC);
4975    E1000_READ_REG(hw, ICRXOC);
4976    E1000_READ_REG(hw, ICRXPTC);
4977    E1000_READ_REG(hw, ICRXATC);
4978    E1000_READ_REG(hw, ICTXPTC);
4979    E1000_READ_REG(hw, ICTXATC);
4980    E1000_READ_REG(hw, ICTXQEC);
4981    E1000_READ_REG(hw, ICTXQMTC);
4982    E1000_READ_REG(hw, ICRXDMTC);
4983
4984}
4985
4986/******************************************************************************
4987 * Resets Adaptive IFS to its default state.
4988 *
4989 * hw - Struct containing variables accessed by shared code
4990 *
4991 * Call this after em_init_hw. You may override the IFS defaults by setting
4992 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4993 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4994 * before calling this function.
4995 *****************************************************************************/
4996void
4997em_reset_adaptive(struct em_hw *hw)
4998{
4999    DEBUGFUNC("em_reset_adaptive");
5000
5001    if(hw->adaptive_ifs) {
5002        if(!hw->ifs_params_forced) {
5003            hw->current_ifs_val = 0;
5004            hw->ifs_min_val = IFS_MIN;
5005            hw->ifs_max_val = IFS_MAX;
5006            hw->ifs_step_size = IFS_STEP;
5007            hw->ifs_ratio = IFS_RATIO;
5008        }
5009        hw->in_ifs_mode = FALSE;
5010        E1000_WRITE_REG(hw, AIT, 0);
5011    } else {
5012        DEBUGOUT("Not in Adaptive IFS mode!\n");
5013    }
5014}
5015
5016/******************************************************************************
5017 * Called during the callback/watchdog routine to update IFS value based on
5018 * the ratio of transmits to collisions.
5019 *
5020 * hw - Struct containing variables accessed by shared code
5021 * tx_packets - Number of transmits since last callback
5022 * total_collisions - Number of collisions since last callback
5023 *****************************************************************************/
5024void
5025em_update_adaptive(struct em_hw *hw)
5026{
5027    DEBUGFUNC("em_update_adaptive");
5028
5029    if(hw->adaptive_ifs) {
5030        if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
5031            if(hw->tx_packet_delta > MIN_NUM_XMITS) {
5032                hw->in_ifs_mode = TRUE;
5033                if(hw->current_ifs_val < hw->ifs_max_val) {
5034                    if(hw->current_ifs_val == 0)
5035                        hw->current_ifs_val = hw->ifs_min_val;
5036                    else
5037                        hw->current_ifs_val += hw->ifs_step_size;
5038                    E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
5039                }
5040            }
5041        } else {
5042            if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
5043                hw->current_ifs_val = 0;
5044                hw->in_ifs_mode = FALSE;
5045                E1000_WRITE_REG(hw, AIT, 0);
5046            }
5047        }
5048    } else {
5049        DEBUGOUT("Not in Adaptive IFS mode!\n");
5050    }
5051}
5052
5053/******************************************************************************
5054 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5055 *
5056 * hw - Struct containing variables accessed by shared code
5057 * frame_len - The length of the frame in question
5058 * mac_addr - The Ethernet destination address of the frame in question
5059 *****************************************************************************/
5060void
5061em_tbi_adjust_stats(struct em_hw *hw,
5062                       struct em_hw_stats *stats,
5063                       uint32_t frame_len,
5064                       uint8_t *mac_addr)
5065{
5066    uint64_t carry_bit;
5067
5068    /* First adjust the frame length. */
5069    frame_len--;
5070    /* We need to adjust the statistics counters, since the hardware
5071     * counters overcount this packet as a CRC error and undercount
5072     * the packet as a good packet
5073     */
5074    /* This packet should not be counted as a CRC error.    */
5075    stats->crcerrs--;
5076    /* This packet does count as a Good Packet Received.    */
5077    stats->gprc++;
5078
5079    /* Adjust the Good Octets received counters             */
5080    carry_bit = 0x80000000 & stats->gorcl;
5081    stats->gorcl += frame_len;
5082    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5083     * Received Count) was one before the addition,
5084     * AND it is zero after, then we lost the carry out,
5085     * need to add one to Gorch (Good Octets Received Count High).
5086     * This could be simplified if all environments supported
5087     * 64-bit integers.
5088     */
5089    if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
5090        stats->gorch++;
5091    /* Is this a broadcast or multicast?  Check broadcast first,
5092     * since the test for a multicast frame will test positive on
5093     * a broadcast frame.
5094     */
5095    if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
5096        /* Broadcast packet */
5097        stats->bprc++;
5098    else if(*mac_addr & 0x01)
5099        /* Multicast packet */
5100        stats->mprc++;
5101
5102    if(frame_len == hw->max_frame_size) {
5103        /* In this case, the hardware has overcounted the number of
5104         * oversize frames.
5105         */
5106        if(stats->roc > 0)
5107            stats->roc--;
5108    }
5109
5110    /* Adjust the bin counters when the extra byte put the frame in the
5111     * wrong bin. Remember that the frame_len was adjusted above.
5112     */
5113    if(frame_len == 64) {
5114        stats->prc64++;
5115        stats->prc127--;
5116    } else if(frame_len == 127) {
5117        stats->prc127++;
5118        stats->prc255--;
5119    } else if(frame_len == 255) {
5120        stats->prc255++;
5121        stats->prc511--;
5122    } else if(frame_len == 511) {
5123        stats->prc511++;
5124        stats->prc1023--;
5125    } else if(frame_len == 1023) {
5126        stats->prc1023++;
5127        stats->prc1522--;
5128    } else if(frame_len == 1522) {
5129        stats->prc1522++;
5130    }
5131}
5132
5133/******************************************************************************
5134 * Gets the current PCI bus type, speed, and width of the hardware
5135 *
5136 * hw - Struct containing variables accessed by shared code
5137 *****************************************************************************/
5138void
5139em_get_bus_info(struct em_hw *hw)
5140{
5141    uint32_t status;
5142
5143    switch (hw->mac_type) {
5144    case em_82542_rev2_0:
5145    case em_82542_rev2_1:
5146        hw->bus_type = em_bus_type_unknown;
5147        hw->bus_speed = em_bus_speed_unknown;
5148        hw->bus_width = em_bus_width_unknown;
5149        break;
5150    case em_82573:
5151        hw->bus_type = em_bus_type_pci_express;
5152        hw->bus_speed = em_bus_speed_2500;
5153        hw->bus_width = em_bus_width_pciex_4;
5154        break;
5155    default:
5156        status = E1000_READ_REG(hw, STATUS);
5157        hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5158                       em_bus_type_pcix : em_bus_type_pci;
5159
5160        if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
5161            hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
5162                            em_bus_speed_66 : em_bus_speed_120;
5163        } else if(hw->bus_type == em_bus_type_pci) {
5164            hw->bus_speed = (status & E1000_STATUS_PCI66) ?
5165                            em_bus_speed_66 : em_bus_speed_33;
5166        } else {
5167            switch (status & E1000_STATUS_PCIX_SPEED) {
5168            case E1000_STATUS_PCIX_SPEED_66:
5169                hw->bus_speed = em_bus_speed_66;
5170                break;
5171            case E1000_STATUS_PCIX_SPEED_100:
5172                hw->bus_speed = em_bus_speed_100;
5173                break;
5174            case E1000_STATUS_PCIX_SPEED_133:
5175                hw->bus_speed = em_bus_speed_133;
5176                break;
5177            default:
5178                hw->bus_speed = em_bus_speed_reserved;
5179                break;
5180            }
5181        }
5182        hw->bus_width = (status & E1000_STATUS_BUS64) ?
5183                        em_bus_width_64 : em_bus_width_32;
5184        break;
5185    }
5186}
5187/******************************************************************************
5188 * Reads a value from one of the devices registers using port I/O (as opposed
5189 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5190 *
5191 * hw - Struct containing variables accessed by shared code
5192 * offset - offset to read from
5193 *****************************************************************************/
5194uint32_t
5195em_read_reg_io(struct em_hw *hw,
5196                  uint32_t offset)
5197{
5198    unsigned long io_addr = hw->io_base;
5199    unsigned long io_data = hw->io_base + 4;
5200
5201    em_io_write(hw, io_addr, offset);
5202    return em_io_read(hw, io_data);
5203}
5204
5205/******************************************************************************
5206 * Writes a value to one of the devices registers using port I/O (as opposed to
5207 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5208 *
5209 * hw - Struct containing variables accessed by shared code
5210 * offset - offset to write to
5211 * value - value to write
5212 *****************************************************************************/
5213void
5214em_write_reg_io(struct em_hw *hw,
5215                   uint32_t offset,
5216                   uint32_t value)
5217{
5218    unsigned long io_addr = hw->io_base;
5219    unsigned long io_data = hw->io_base + 4;
5220
5221    em_io_write(hw, io_addr, offset);
5222    em_io_write(hw, io_data, value);
5223}
5224
5225
5226/******************************************************************************
5227 * Estimates the cable length.
5228 *
5229 * hw - Struct containing variables accessed by shared code
5230 * min_length - The estimated minimum length
5231 * max_length - The estimated maximum length
5232 *
5233 * returns: - E1000_ERR_XXX
5234 *            E1000_SUCCESS
5235 *
5236 * This function always returns a ranged length (minimum & maximum).
5237 * So for M88 phy's, this function interprets the one value returned from the
5238 * register to the minimum and maximum range.
5239 * For IGP phy's, the function calculates the range by the AGC registers.
5240 *****************************************************************************/
5241int32_t
5242em_get_cable_length(struct em_hw *hw,
5243                       uint16_t *min_length,
5244                       uint16_t *max_length)
5245{
5246    int32_t ret_val;
5247    uint16_t agc_value = 0;
5248    uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5249    uint16_t i, phy_data;
5250    uint16_t cable_length;
5251
5252    DEBUGFUNC("em_get_cable_length");
5253
5254    *min_length = *max_length = 0;
5255
5256    /* Use old method for Phy older than IGP */
5257    if(hw->phy_type == em_phy_m88) {
5258
5259        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5260                                     &phy_data);
5261        if(ret_val)
5262            return ret_val;
5263        cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5264                       M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5265
5266        /* Convert the enum value to ranged values */
5267        switch (cable_length) {
5268        case em_cable_length_50:
5269            *min_length = 0;
5270            *max_length = em_igp_cable_length_50;
5271            break;
5272        case em_cable_length_50_80:
5273            *min_length = em_igp_cable_length_50;
5274            *max_length = em_igp_cable_length_80;
5275            break;
5276        case em_cable_length_80_110:
5277            *min_length = em_igp_cable_length_80;
5278            *max_length = em_igp_cable_length_110;
5279            break;
5280        case em_cable_length_110_140:
5281            *min_length = em_igp_cable_length_110;
5282            *max_length = em_igp_cable_length_140;
5283            break;
5284        case em_cable_length_140:
5285            *min_length = em_igp_cable_length_140;
5286            *max_length = em_igp_cable_length_170;
5287            break;
5288        default:
5289            return -E1000_ERR_PHY;
5290            break;
5291        }
5292    } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
5293        uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5294                                                         {IGP01E1000_PHY_AGC_A,
5295                                                          IGP01E1000_PHY_AGC_B,
5296                                                          IGP01E1000_PHY_AGC_C,
5297                                                          IGP01E1000_PHY_AGC_D};
5298        /* Read the AGC registers for all channels */
5299        for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5300
5301            ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5302            if(ret_val)
5303                return ret_val;
5304
5305            cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5306
5307            /* Array bound check. */
5308            if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
5309               (cur_agc == 0))
5310                return -E1000_ERR_PHY;
5311
5312            agc_value += cur_agc;
5313
5314            /* Update minimal AGC value. */
5315            if(min_agc > cur_agc)
5316                min_agc = cur_agc;
5317        }
5318
5319        /* Remove the minimal AGC result for length < 50m */
5320        if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
5321            agc_value -= min_agc;
5322
5323            /* Get the average length of the remaining 3 channels */
5324            agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5325        } else {
5326            /* Get the average length of all the 4 channels. */
5327            agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5328        }
5329
5330        /* Set the range of the calculated length. */
5331        *min_length = ((em_igp_cable_length_table[agc_value] -
5332                       IGP01E1000_AGC_RANGE) > 0) ?
5333                       (em_igp_cable_length_table[agc_value] -
5334                       IGP01E1000_AGC_RANGE) : 0;
5335        *max_length = em_igp_cable_length_table[agc_value] +
5336                      IGP01E1000_AGC_RANGE;
5337    }
5338
5339    return E1000_SUCCESS;
5340}
5341
5342/******************************************************************************
5343 * Check the cable polarity
5344 *
5345 * hw - Struct containing variables accessed by shared code
5346 * polarity - output parameter : 0 - Polarity is not reversed
5347 *                               1 - Polarity is reversed.
5348 *
5349 * returns: - E1000_ERR_XXX
5350 *            E1000_SUCCESS
5351 *
5352 * For phy's older then IGP, this function simply reads the polarity bit in the
5353 * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
5354 * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
5355 * return 0.  If the link speed is 1000 Mbps the polarity status is in the
5356 * IGP01E1000_PHY_PCS_INIT_REG.
5357 *****************************************************************************/
5358int32_t
5359em_check_polarity(struct em_hw *hw,
5360                     uint16_t *polarity)
5361{
5362    int32_t ret_val;
5363    uint16_t phy_data;
5364#ifdef __rtems__
5365        *polarity = 0; /* keep compiler happy */
5366#endif
5367
5368    DEBUGFUNC("em_check_polarity");
5369
5370    if(hw->phy_type == em_phy_m88) {
5371        /* return the Polarity bit in the Status register. */
5372        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5373                                     &phy_data);
5374        if(ret_val)
5375            return ret_val;
5376        *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
5377                    M88E1000_PSSR_REV_POLARITY_SHIFT;
5378    } else if(hw->phy_type == em_phy_igp ||
5379              hw->phy_type == em_phy_igp_2) {
5380        /* Read the Status register to check the speed */
5381        ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5382                                     &phy_data);
5383        if(ret_val)
5384            return ret_val;
5385
5386        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5387         * find the polarity status */
5388        if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5389           IGP01E1000_PSSR_SPEED_1000MBPS) {
5390
5391            /* Read the GIG initialization PCS register (0x00B4) */
5392            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5393                                         &phy_data);
5394            if(ret_val)
5395                return ret_val;
5396
5397            /* Check the polarity bits */
5398            *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
5399        } else {
5400            /* For 10 Mbps, read the polarity bit in the status register. (for
5401             * 100 Mbps this bit is always 0) */
5402            *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
5403        }
5404    }
5405    return E1000_SUCCESS;
5406}
5407
5408/******************************************************************************
5409 * Check if Downshift occured
5410 *
5411 * hw - Struct containing variables accessed by shared code
5412 * downshift - output parameter : 0 - No Downshift ocured.
5413 *                                1 - Downshift ocured.
5414 *
5415 * returns: - E1000_ERR_XXX
5416 *            E1000_SUCCESS
5417 *
5418 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5419 * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
5420 * Link Health register.  In IGP this bit is latched high, so the driver must
5421 * read it immediately after link is established.
5422 *****************************************************************************/
5423int32_t
5424em_check_downshift(struct em_hw *hw)
5425{
5426    int32_t ret_val;
5427    uint16_t phy_data;
5428
5429    DEBUGFUNC("em_check_downshift");
5430
5431    if(hw->phy_type == em_phy_igp || 
5432        hw->phy_type == em_phy_igp_2) {
5433        ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5434                                     &phy_data);
5435        if(ret_val)
5436            return ret_val;
5437
5438        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5439    } else if(hw->phy_type == em_phy_m88) {
5440        ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5441                                     &phy_data);
5442        if(ret_val)
5443            return ret_val;
5444
5445        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5446                               M88E1000_PSSR_DOWNSHIFT_SHIFT;
5447    }
5448
5449    return E1000_SUCCESS;
5450}
5451
5452/*****************************************************************************
5453 *
5454 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5455 * gigabit link is achieved to improve link quality.
5456 *
5457 * hw: Struct containing variables accessed by shared code
5458 *
5459 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5460 *            E1000_SUCCESS at any other case.
5461 *
5462 ****************************************************************************/
5463
5464int32_t
5465em_config_dsp_after_link_change(struct em_hw *hw,
5466                                   boolean_t link_up)
5467{
5468    int32_t ret_val;
5469    uint16_t phy_data, phy_saved_data, speed, duplex, i;
5470    uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5471                                        {IGP01E1000_PHY_AGC_PARAM_A,
5472                                        IGP01E1000_PHY_AGC_PARAM_B,
5473                                        IGP01E1000_PHY_AGC_PARAM_C,
5474                                        IGP01E1000_PHY_AGC_PARAM_D};
5475    uint16_t min_length, max_length;
5476
5477    DEBUGFUNC("em_config_dsp_after_link_change");
5478
5479    if(hw->phy_type != em_phy_igp)
5480        return E1000_SUCCESS;
5481
5482    if(link_up) {
5483        ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
5484        if(ret_val) {
5485            DEBUGOUT("Error getting link speed and duplex\n");
5486            return ret_val;
5487        }
5488
5489        if(speed == SPEED_1000) {
5490
5491            em_get_cable_length(hw, &min_length, &max_length);
5492
5493            if((hw->dsp_config_state == em_dsp_config_enabled) &&
5494                min_length >= em_igp_cable_length_50) {
5495
5496                for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5497                    ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
5498                                                 &phy_data);
5499                    if(ret_val)
5500                        return ret_val;
5501
5502                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5503
5504                    ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
5505                                                  phy_data);
5506                    if(ret_val)
5507                        return ret_val;
5508                }
5509                hw->dsp_config_state = em_dsp_config_activated;
5510            }
5511
5512            if((hw->ffe_config_state == em_ffe_config_enabled) &&
5513               (min_length < em_igp_cable_length_50)) {
5514
5515                uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5516                uint32_t idle_errs = 0;
5517
5518                /* clear previous idle error counts */
5519                ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
5520                                             &phy_data);
5521                if(ret_val)
5522                    return ret_val;
5523
5524                for(i = 0; i < ffe_idle_err_timeout; i++) {
5525                    usec_delay(1000);
5526                    ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
5527                                                 &phy_data);
5528                    if(ret_val)
5529                        return ret_val;
5530
5531                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5532                    if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5533                        hw->ffe_config_state = em_ffe_config_active;
5534
5535                        ret_val = em_write_phy_reg(hw,
5536                                    IGP01E1000_PHY_DSP_FFE,
5537                                    IGP01E1000_PHY_DSP_FFE_CM_CP);
5538                        if(ret_val)
5539                            return ret_val;
5540                        break;
5541                    }
5542
5543                    if(idle_errs)
5544                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5545                }
5546            }
5547        }
5548    } else {
5549        if(hw->dsp_config_state == em_dsp_config_activated) {
5550            /* Save off the current value of register 0x2F5B to be restored at
5551             * the end of the routines. */
5552            ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5553
5554            if(ret_val)
5555                return ret_val;
5556
5557            /* Disable the PHY transmitter */
5558            ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
5559
5560            if(ret_val)
5561                return ret_val;
5562
5563            msec_delay_irq(20);
5564
5565            ret_val = em_write_phy_reg(hw, 0x0000,
5566                                          IGP01E1000_IEEE_FORCE_GIGA);
5567            if(ret_val)
5568                return ret_val;
5569            for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5570                ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
5571                if(ret_val)
5572                    return ret_val;
5573
5574                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5575                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5576
5577                ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
5578                if(ret_val)
5579                    return ret_val;
5580            }
5581
5582            ret_val = em_write_phy_reg(hw, 0x0000,
5583                                          IGP01E1000_IEEE_RESTART_AUTONEG);
5584            if(ret_val)
5585                return ret_val;
5586
5587            msec_delay_irq(20);
5588
5589            /* Now enable the transmitter */
5590            ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5591
5592            if(ret_val)
5593                return ret_val;
5594
5595            hw->dsp_config_state = em_dsp_config_enabled;
5596        }
5597
5598        if(hw->ffe_config_state == em_ffe_config_active) {
5599            /* Save off the current value of register 0x2F5B to be restored at
5600             * the end of the routines. */
5601            ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5602
5603            if(ret_val)
5604                return ret_val;
5605
5606            /* Disable the PHY transmitter */
5607            ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
5608
5609            if(ret_val)
5610                return ret_val;
5611
5612            msec_delay_irq(20);
5613
5614            ret_val = em_write_phy_reg(hw, 0x0000,
5615                                          IGP01E1000_IEEE_FORCE_GIGA);
5616            if(ret_val)
5617                return ret_val;
5618            ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5619                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
5620            if(ret_val)
5621                return ret_val;
5622
5623            ret_val = em_write_phy_reg(hw, 0x0000,
5624                                          IGP01E1000_IEEE_RESTART_AUTONEG);
5625            if(ret_val)
5626                return ret_val;
5627
5628            msec_delay_irq(20);
5629
5630            /* Now enable the transmitter */
5631            ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5632
5633            if(ret_val)
5634                return ret_val;
5635
5636            hw->ffe_config_state = em_ffe_config_enabled;
5637        }
5638    }
5639    return E1000_SUCCESS;
5640}
5641
5642/*****************************************************************************
5643 * Set PHY to class A mode
5644 * Assumes the following operations will follow to enable the new class mode.
5645 *  1. Do a PHY soft reset
5646 *  2. Restart auto-negotiation or force link.
5647 *
5648 * hw - Struct containing variables accessed by shared code
5649 ****************************************************************************/
5650static int32_t
5651em_set_phy_mode(struct em_hw *hw)
5652{
5653    int32_t ret_val;
5654    uint16_t eeprom_data;
5655
5656    DEBUGFUNC("em_set_phy_mode");
5657
5658    if((hw->mac_type == em_82545_rev_3) &&
5659       (hw->media_type == em_media_type_copper)) {
5660        ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5661        if(ret_val) {
5662            return ret_val;
5663        }
5664
5665        if((eeprom_data != EEPROM_RESERVED_WORD) &&
5666           (eeprom_data & EEPROM_PHY_CLASS_A)) {
5667            ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5668            if(ret_val)
5669                return ret_val;
5670            ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5671            if(ret_val)
5672                return ret_val;
5673
5674            hw->phy_reset_disable = FALSE;
5675        }
5676    }
5677
5678    return E1000_SUCCESS;
5679}
5680
5681/*****************************************************************************
5682 *
5683 * This function sets the lplu state according to the active flag.  When
5684 * activating lplu this function also disables smart speed and vise versa.
5685 * lplu will not be activated unless the device autonegotiation advertisment
5686 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5687 * hw: Struct containing variables accessed by shared code
5688 * active - true to enable lplu false to disable lplu.
5689 *
5690 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5691 *            E1000_SUCCESS at any other case.
5692 *
5693 ****************************************************************************/
5694
5695int32_t
5696em_set_d3_lplu_state(struct em_hw *hw,
5697                        boolean_t active)
5698{
5699    int32_t ret_val;
5700    uint16_t phy_data;
5701    DEBUGFUNC("em_set_d3_lplu_state");
5702
5703    if(hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2)
5704        return E1000_SUCCESS;
5705
5706    /* During driver activity LPLU should not be used or it will attain link
5707     * from the lowest speeds starting from 10Mbps. The capability is used for
5708     * Dx transitions and states */
5709    if(hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
5710        ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5711        if(ret_val)
5712            return ret_val;
5713    } else {
5714        ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5715        if(ret_val)
5716            return ret_val;
5717    }
5718
5719    if(!active) {
5720        if(hw->mac_type == em_82541_rev_2 ||
5721           hw->mac_type == em_82547_rev_2) {
5722            phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5723            ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5724            if(ret_val)
5725                return ret_val;
5726        } else {
5727                phy_data &= ~IGP02E1000_PM_D3_LPLU;
5728                ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5729                                              phy_data);
5730                if (ret_val)
5731                    return ret_val;
5732        }
5733
5734        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
5735         * Dx states where the power conservation is most important.  During
5736         * driver activity we should enable SmartSpeed, so performance is
5737         * maintained. */
5738        if (hw->smart_speed == em_smart_speed_on) {
5739            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5740                                         &phy_data);
5741            if(ret_val)
5742                return ret_val;
5743
5744            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5745            ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5746                                          phy_data);
5747            if(ret_val)
5748                return ret_val;
5749        } else if (hw->smart_speed == em_smart_speed_off) {
5750            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5751                                         &phy_data);
5752            if (ret_val)
5753                return ret_val;
5754
5755            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5756            ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5757                                          phy_data);
5758            if(ret_val)
5759                return ret_val;
5760        }
5761
5762    } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5763              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5764              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5765
5766        if(hw->mac_type == em_82541_rev_2 ||
5767           hw->mac_type == em_82547_rev_2) {
5768            phy_data |= IGP01E1000_GMII_FLEX_SPD;
5769            ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5770            if(ret_val)
5771                return ret_val;
5772        } else {
5773                phy_data |= IGP02E1000_PM_D3_LPLU;
5774                ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5775                                              phy_data);
5776                if (ret_val)
5777                    return ret_val;
5778        }
5779
5780        /* When LPLU is enabled we should disable SmartSpeed */
5781        ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5782        if(ret_val)
5783            return ret_val;
5784
5785        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5786        ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5787        if(ret_val)
5788            return ret_val;
5789
5790    }
5791    return E1000_SUCCESS;
5792}
5793
5794/*****************************************************************************
5795 *
5796 * This function sets the lplu d0 state according to the active flag.  When
5797 * activating lplu this function also disables smart speed and vise versa.
5798 * lplu will not be activated unless the device autonegotiation advertisment
5799 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5800 * hw: Struct containing variables accessed by shared code
5801 * active - true to enable lplu false to disable lplu.
5802 *
5803 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5804 *            E1000_SUCCESS at any other case.
5805 *
5806 ****************************************************************************/
5807
5808int32_t
5809em_set_d0_lplu_state(struct em_hw *hw,
5810                        boolean_t active)
5811{
5812    int32_t ret_val;
5813    uint16_t phy_data;
5814    DEBUGFUNC("em_set_d0_lplu_state");
5815
5816    if(hw->mac_type <= em_82547_rev_2)
5817        return E1000_SUCCESS;
5818
5819    ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5820    if(ret_val)
5821        return ret_val;
5822
5823    if (!active) {
5824            phy_data &= ~IGP02E1000_PM_D0_LPLU;
5825            ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5826            if (ret_val)
5827                return ret_val;
5828
5829        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
5830         * Dx states where the power conservation is most important.  During
5831         * driver activity we should enable SmartSpeed, so performance is
5832         * maintained. */
5833        if (hw->smart_speed == em_smart_speed_on) {
5834            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5835                                         &phy_data);
5836            if(ret_val)
5837                return ret_val;
5838
5839            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5840            ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5841                                          phy_data);
5842            if(ret_val)
5843                return ret_val;
5844        } else if (hw->smart_speed == em_smart_speed_off) {
5845            ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5846                                         &phy_data);
5847            if (ret_val)
5848                return ret_val;
5849
5850            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5851            ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5852                                          phy_data);
5853            if(ret_val)
5854                return ret_val;
5855        }
5856
5857
5858    } else {
5859 
5860            phy_data |= IGP02E1000_PM_D0_LPLU;   
5861            ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5862            if (ret_val)
5863                return ret_val;
5864
5865        /* When LPLU is enabled we should disable SmartSpeed */
5866        ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5867        if(ret_val)
5868            return ret_val;
5869
5870        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5871        ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5872        if(ret_val)
5873            return ret_val;
5874
5875    }
5876    return E1000_SUCCESS;
5877}
5878
5879/******************************************************************************
5880 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5881 *
5882 * hw - Struct containing variables accessed by shared code
5883 *****************************************************************************/
5884static int32_t
5885em_set_vco_speed(struct em_hw *hw)
5886{
5887    int32_t  ret_val;
5888    uint16_t default_page = 0;
5889    uint16_t phy_data;
5890
5891    DEBUGFUNC("em_set_vco_speed");
5892
5893    switch(hw->mac_type) {
5894    case em_82545_rev_3:
5895    case em_82546_rev_3:
5896       break;
5897    default:
5898        return E1000_SUCCESS;
5899    }
5900
5901    /* Set PHY register 30, page 5, bit 8 to 0 */
5902
5903    ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5904    if(ret_val)
5905        return ret_val;
5906
5907    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5908    if(ret_val)
5909        return ret_val;
5910
5911    ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5912    if(ret_val)
5913        return ret_val;
5914
5915    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5916    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5917    if(ret_val)
5918        return ret_val;
5919
5920    /* Set PHY register 30, page 4, bit 11 to 1 */
5921
5922    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5923    if(ret_val)
5924        return ret_val;
5925
5926    ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5927    if(ret_val)
5928        return ret_val;
5929
5930    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5931    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5932    if(ret_val)
5933        return ret_val;
5934
5935    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5936    if(ret_val)
5937        return ret_val;
5938
5939    return E1000_SUCCESS;
5940}
5941
5942
5943/*****************************************************************************
5944 * This function reads the cookie from ARC ram.
5945 *
5946 * returns: - E1000_SUCCESS .
5947 ****************************************************************************/
5948int32_t
5949em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer)
5950{
5951    uint8_t i;
5952    uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 
5953    uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
5954
5955    length = (length >> 2);
5956    offset = (offset >> 2);
5957
5958    for (i = 0; i < length; i++) {
5959        *((uint32_t *) buffer + i) =
5960            E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
5961    }
5962    return E1000_SUCCESS;
5963}
5964
5965
5966/*****************************************************************************
5967 * This function checks whether the HOST IF is enabled for command operaton
5968 * and also checks whether the previous command is completed.
5969 * It busy waits in case of previous command is not completed.
5970 *
5971 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5972 *            timeout
5973 *          - E1000_SUCCESS for success.
5974 ****************************************************************************/
5975int32_t
5976em_mng_enable_host_if(struct em_hw * hw)
5977{
5978    uint32_t hicr;
5979    uint8_t i;
5980
5981    /* Check that the host interface is enabled. */
5982    hicr = E1000_READ_REG(hw, HICR);
5983    if ((hicr & E1000_HICR_EN) == 0) {
5984        DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5985        return -E1000_ERR_HOST_INTERFACE_COMMAND;
5986    }
5987    /* check the previous command is completed */
5988    for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
5989        hicr = E1000_READ_REG(hw, HICR);
5990        if (!(hicr & E1000_HICR_C))
5991            break;
5992        msec_delay_irq(1);
5993    }
5994
5995    if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 
5996        DEBUGOUT("Previous command timeout failed .\n");
5997        return -E1000_ERR_HOST_INTERFACE_COMMAND;
5998    }
5999    return E1000_SUCCESS;
6000}
6001
6002/*****************************************************************************
6003 * This function writes the buffer content at the offset given on the host if.
6004 * It also does alignment considerations to do the writes in most efficient way.
6005 * Also fills up the sum of the buffer in *buffer parameter.
6006 *
6007 * returns  - E1000_SUCCESS for success.
6008 ****************************************************************************/
6009int32_t
6010em_mng_host_if_write(struct em_hw * hw, uint8_t *buffer,
6011                        uint16_t length, uint16_t offset, uint8_t *sum)
6012{
6013    uint8_t *tmp;
6014    uint8_t *bufptr = buffer;
6015    uint32_t data;
6016    uint16_t remaining, i, j, prev_bytes;
6017
6018    /* sum = only sum of the data and it is not checksum */
6019
6020    if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6021        return -E1000_ERR_PARAM;
6022    }
6023
6024    tmp = (uint8_t *)&data;
6025    prev_bytes = offset & 0x3;
6026    offset &= 0xFFFC;
6027    offset >>= 2;
6028
6029    if (prev_bytes) {
6030        data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6031        for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6032            *(tmp + j) = *bufptr++;
6033            *sum += *(tmp + j);
6034        }
6035        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6036        length -= j - prev_bytes;
6037        offset++;
6038    }
6039
6040    remaining = length & 0x3;
6041    length -= remaining;
6042
6043    /* Calculate length in DWORDs */
6044    length >>= 2;
6045
6046    /* The device driver writes the relevant command block into the
6047     * ram area. */
6048    for (i = 0; i < length; i++) {
6049        for (j = 0; j < sizeof(uint32_t); j++) {
6050            *(tmp + j) = *bufptr++;
6051            *sum += *(tmp + j);
6052        }
6053
6054        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6055    }
6056    if (remaining) {
6057        for (j = 0; j < sizeof(uint32_t); j++) {
6058            if (j < remaining)
6059                *(tmp + j) = *bufptr++;
6060            else
6061                *(tmp + j) = 0;
6062
6063            *sum += *(tmp + j);
6064        }
6065        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6066    }
6067
6068    return E1000_SUCCESS;
6069}
6070
6071
6072/*****************************************************************************
6073 * This function writes the command header after does the checksum calculation.
6074 *
6075 * returns  - E1000_SUCCESS for success.
6076 ****************************************************************************/
6077int32_t
6078em_mng_write_cmd_header(struct em_hw * hw,
6079                           struct em_host_mng_command_header * hdr)
6080{
6081    uint16_t i;
6082    uint8_t sum;
6083    uint8_t *buffer;
6084
6085    /* Write the whole command header structure which includes sum of
6086     * the buffer */
6087
6088    uint16_t length = sizeof(struct em_host_mng_command_header);
6089
6090    sum = hdr->checksum;
6091    hdr->checksum = 0;
6092
6093    buffer = (uint8_t *) hdr;
6094    i = length;
6095    while(i--)
6096        sum += buffer[i];
6097
6098    hdr->checksum = 0 - sum;
6099
6100    length >>= 2;
6101    /* The device driver writes the relevant command block into the ram area. */
6102    for (i = 0; i < length; i++)
6103        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6104
6105    return E1000_SUCCESS;
6106}
6107
6108
6109/*****************************************************************************
6110 * This function indicates to ARC that a new command is pending which completes
6111 * one write operation by the driver.
6112 *
6113 * returns  - E1000_SUCCESS for success.
6114 ****************************************************************************/
6115int32_t
6116em_mng_write_commit(
6117    struct em_hw * hw)
6118{
6119    uint32_t hicr;
6120
6121    hicr = E1000_READ_REG(hw, HICR);
6122    /* Setting this bit tells the ARC that a new command is pending. */
6123    E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6124
6125    return E1000_SUCCESS;
6126}
6127
6128
6129/*****************************************************************************
6130 * This function checks the mode of the firmware.
6131 *
6132 * returns  - TRUE when the mode is IAMT or FALSE.
6133 ****************************************************************************/
6134boolean_t
6135em_check_mng_mode(
6136    struct em_hw *hw)
6137{
6138    uint32_t fwsm;
6139
6140    fwsm = E1000_READ_REG(hw, FWSM);
6141
6142    if((fwsm & E1000_FWSM_MODE_MASK) ==
6143        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6144        return TRUE;
6145
6146    return FALSE;
6147}
6148
6149
6150/*****************************************************************************
6151 * This function writes the dhcp info .
6152 ****************************************************************************/
6153int32_t
6154em_mng_write_dhcp_info(struct em_hw * hw, uint8_t *buffer,
6155                          uint16_t length)
6156{
6157    int32_t ret_val;
6158    struct em_host_mng_command_header hdr;
6159
6160    hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6161    hdr.command_length = length;
6162    hdr.reserved1 = 0;
6163    hdr.reserved2 = 0;
6164    hdr.checksum = 0;
6165
6166    ret_val = em_mng_enable_host_if(hw);
6167    if (ret_val == E1000_SUCCESS) {
6168        ret_val = em_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6169                                          &(hdr.checksum));
6170        if (ret_val == E1000_SUCCESS) {
6171            ret_val = em_mng_write_cmd_header(hw, &hdr);
6172            if (ret_val == E1000_SUCCESS)
6173                ret_val = em_mng_write_commit(hw);
6174        }
6175    }
6176    return ret_val;
6177}
6178
6179
6180/*****************************************************************************
6181 * This function calculates the checksum.
6182 *
6183 * returns  - checksum of buffer contents.
6184 ****************************************************************************/
6185uint8_t
6186em_calculate_mng_checksum(char *buffer, uint32_t length)
6187{
6188    uint8_t sum = 0;
6189    uint32_t i;
6190
6191    if (!buffer)
6192        return 0;
6193
6194    for (i=0; i < length; i++)
6195        sum += buffer[i];
6196
6197    return (uint8_t) (0 - sum);
6198}
6199
6200/*****************************************************************************
6201 * This function checks whether tx pkt filtering needs to be enabled or not.
6202 *
6203 * returns  - TRUE for packet filtering or FALSE.
6204 ****************************************************************************/
6205boolean_t
6206em_enable_tx_pkt_filtering(struct em_hw *hw)
6207{
6208    /* called in init as well as watchdog timer functions */
6209
6210    int32_t ret_val, checksum;
6211    boolean_t tx_filter = FALSE;
6212    struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6213    uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6214
6215    if (em_check_mng_mode(hw)) {
6216        ret_val = em_mng_enable_host_if(hw);
6217        if (ret_val == E1000_SUCCESS) {
6218            ret_val = em_host_if_read_cookie(hw, buffer);
6219            if (ret_val == E1000_SUCCESS) {
6220                checksum = hdr->checksum;
6221                hdr->checksum = 0;
6222                if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6223                    checksum == em_calculate_mng_checksum((char *)buffer,
6224                                               E1000_MNG_DHCP_COOKIE_LENGTH)) {
6225                    if (hdr->status &
6226                        E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6227                        tx_filter = TRUE;
6228                } else
6229                    tx_filter = TRUE;
6230            } else
6231                tx_filter = TRUE;
6232        }
6233    }
6234
6235    hw->tx_pkt_filtering = tx_filter;
6236    return tx_filter;
6237}
6238
6239/******************************************************************************
6240 * Verifies the hardware needs to allow ARPs to be processed by the host
6241 *
6242 * hw - Struct containing variables accessed by shared code
6243 *
6244 * returns: - TRUE/FALSE
6245 *
6246 *****************************************************************************/
6247uint32_t
6248em_enable_mng_pass_thru(struct em_hw *hw)
6249{
6250    uint32_t manc;
6251    uint32_t fwsm, factps;
6252
6253    if (hw->asf_firmware_present) {
6254        manc = E1000_READ_REG(hw, MANC);
6255
6256        if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6257            !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6258            return FALSE;
6259        if (em_arc_subsystem_valid(hw) == TRUE) {
6260            fwsm = E1000_READ_REG(hw, FWSM);
6261            factps = E1000_READ_REG(hw, FACTPS);
6262
6263            if (((fwsm & E1000_FWSM_MODE_MASK) ==
6264                (em_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6265                (factps & E1000_FACTPS_MNGCG))
6266                return TRUE;
6267        } else
6268            if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6269                return TRUE;
6270    }
6271    return FALSE;
6272}
6273
6274static int32_t
6275em_polarity_reversal_workaround(struct em_hw *hw)
6276{
6277    int32_t ret_val;
6278    uint16_t mii_status_reg;
6279    uint16_t i;
6280
6281    /* Polarity reversal workaround for forced 10F/10H links. */
6282
6283    /* Disable the transmitter on the PHY */
6284
6285    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6286    if(ret_val)
6287        return ret_val;
6288    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
6289    if(ret_val)
6290        return ret_val;
6291
6292    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6293    if(ret_val)
6294        return ret_val;
6295
6296    /* This loop will early-out if the NO link condition has been met. */
6297    for(i = PHY_FORCE_TIME; i > 0; i--) {
6298        /* Read the MII Status Register and wait for Link Status bit
6299         * to be clear.
6300         */
6301
6302        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6303        if(ret_val)
6304            return ret_val;
6305
6306        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6307        if(ret_val)
6308            return ret_val;
6309
6310        if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
6311        msec_delay_irq(100);
6312    }
6313
6314    /* Recommended delay time after link has been lost */
6315    msec_delay_irq(1000);
6316
6317    /* Now we will re-enable th transmitter on the PHY */
6318
6319    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6320    if(ret_val)
6321        return ret_val;
6322    msec_delay_irq(50);
6323    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
6324    if(ret_val)
6325        return ret_val;
6326    msec_delay_irq(50);
6327    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
6328    if(ret_val)
6329        return ret_val;
6330    msec_delay_irq(50);
6331    ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
6332    if(ret_val)
6333        return ret_val;
6334
6335    ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6336    if(ret_val)
6337        return ret_val;
6338
6339    /* This loop will early-out if the link condition has been met. */
6340    for(i = PHY_FORCE_TIME; i > 0; i--) {
6341        /* Read the MII Status Register and wait for Link Status bit
6342         * to be set.
6343         */
6344
6345        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6346        if(ret_val)
6347            return ret_val;
6348
6349        ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6350        if(ret_val)
6351            return ret_val;
6352
6353        if(mii_status_reg & MII_SR_LINK_STATUS) break;
6354        msec_delay_irq(100);
6355    }
6356    return E1000_SUCCESS;
6357}
6358
6359/***************************************************************************
6360 *
6361 * Disables PCI-Express master access.
6362 *
6363 * hw: Struct containing variables accessed by shared code
6364 *
6365 * returns: - none.
6366 *
6367 ***************************************************************************/
6368void
6369em_set_pci_express_master_disable(struct em_hw *hw)
6370{
6371    uint32_t ctrl;
6372
6373    DEBUGFUNC("em_set_pci_express_master_disable");
6374
6375    if (hw->bus_type != em_bus_type_pci_express)
6376        return;
6377
6378    ctrl = E1000_READ_REG(hw, CTRL);
6379    ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6380    E1000_WRITE_REG(hw, CTRL, ctrl);
6381}
6382
6383/***************************************************************************
6384 *
6385 * Enables PCI-Express master access.
6386 *
6387 * hw: Struct containing variables accessed by shared code
6388 *
6389 * returns: - none.
6390 *
6391 ***************************************************************************/
6392void
6393em_enable_pciex_master(struct em_hw *hw)
6394{
6395    uint32_t ctrl;
6396
6397    DEBUGFUNC("em_enable_pciex_master");
6398
6399    if (hw->bus_type != em_bus_type_pci_express)
6400        return;
6401
6402    ctrl = E1000_READ_REG(hw, CTRL);
6403    ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6404    E1000_WRITE_REG(hw, CTRL, ctrl);
6405}
6406
6407/*******************************************************************************
6408 *
6409 * Disables PCI-Express master access and verifies there are no pending requests
6410 *
6411 * hw: Struct containing variables accessed by shared code
6412 *
6413 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6414 *            caused the master requests to be disabled.
6415 *            E1000_SUCCESS master requests disabled.
6416 *
6417 ******************************************************************************/
6418int32_t
6419em_disable_pciex_master(struct em_hw *hw)
6420{
6421    int32_t timeout = MASTER_DISABLE_TIMEOUT;   /* 80ms */
6422
6423    DEBUGFUNC("em_disable_pciex_master");
6424
6425    if (hw->bus_type != em_bus_type_pci_express)
6426        return E1000_SUCCESS;
6427
6428    em_set_pci_express_master_disable(hw);
6429
6430    while(timeout) {
6431        if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6432            break;
6433        else
6434            usec_delay(100);
6435        timeout--;
6436    }
6437
6438    if(!timeout) {
6439        DEBUGOUT("Master requests are pending.\n");
6440        return -E1000_ERR_MASTER_REQUESTS_PENDING;
6441    }
6442
6443    return E1000_SUCCESS;
6444}
6445
6446/*******************************************************************************
6447 *
6448 * Check for EEPROM Auto Read bit done.
6449 *
6450 * hw: Struct containing variables accessed by shared code
6451 *
6452 * returns: - E1000_ERR_RESET if fail to reset MAC
6453 *            E1000_SUCCESS at any other case.
6454 *
6455 ******************************************************************************/
6456int32_t
6457em_get_auto_rd_done(struct em_hw *hw)
6458{
6459    int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6460
6461    DEBUGFUNC("em_get_auto_rd_done");
6462
6463    switch (hw->mac_type) {
6464    default:
6465        msec_delay(5);
6466        break;
6467    case em_82573:
6468        while(timeout) {
6469            if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6470            else msec_delay(1);
6471            timeout--;
6472        }
6473
6474        if(!timeout) {
6475            DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6476            return -E1000_ERR_RESET;
6477        }
6478        break;
6479    }
6480
6481    return E1000_SUCCESS;
6482}
6483
6484/***************************************************************************
6485 * Checks if the PHY configuration is done
6486 *
6487 * hw: Struct containing variables accessed by shared code
6488 *
6489 * returns: - E1000_ERR_RESET if fail to reset MAC
6490 *            E1000_SUCCESS at any other case.
6491 *
6492 ***************************************************************************/
6493int32_t
6494em_get_phy_cfg_done(struct em_hw *hw)
6495{
6496    DEBUGFUNC("em_get_phy_cfg_done");
6497
6498    /* Simply wait for 10ms */
6499    msec_delay(10);
6500
6501    return E1000_SUCCESS;
6502}
6503
6504/***************************************************************************
6505 *
6506 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6507 * adapter or Eeprom access.
6508 *
6509 * hw: Struct containing variables accessed by shared code
6510 *
6511 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6512 *            E1000_SUCCESS at any other case.
6513 *
6514 ***************************************************************************/
6515int32_t
6516em_get_hw_eeprom_semaphore(struct em_hw *hw)
6517{
6518    int32_t timeout;
6519    uint32_t swsm;
6520
6521    DEBUGFUNC("em_get_hw_eeprom_semaphore");
6522
6523    if(!hw->eeprom_semaphore_present)
6524        return E1000_SUCCESS;
6525
6526
6527    /* Get the FW semaphore. */
6528    timeout = hw->eeprom.word_size + 1;
6529    while(timeout) {
6530        swsm = E1000_READ_REG(hw, SWSM);
6531        swsm |= E1000_SWSM_SWESMBI;
6532        E1000_WRITE_REG(hw, SWSM, swsm);
6533        /* if we managed to set the bit we got the semaphore. */
6534        swsm = E1000_READ_REG(hw, SWSM);
6535        if(swsm & E1000_SWSM_SWESMBI)
6536            break;
6537
6538        usec_delay(50);
6539        timeout--;
6540    }
6541
6542    if(!timeout) {
6543        /* Release semaphores */
6544        em_put_hw_eeprom_semaphore(hw);
6545        DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6546        return -E1000_ERR_EEPROM;
6547    }
6548
6549    return E1000_SUCCESS;
6550}
6551
6552/***************************************************************************
6553 * This function clears HW semaphore bits.
6554 *
6555 * hw: Struct containing variables accessed by shared code
6556 *
6557 * returns: - None.
6558 *
6559 ***************************************************************************/
6560void
6561em_put_hw_eeprom_semaphore(struct em_hw *hw)
6562{
6563    uint32_t swsm;
6564
6565    DEBUGFUNC("em_put_hw_eeprom_semaphore");
6566
6567    if(!hw->eeprom_semaphore_present)
6568        return;
6569
6570    swsm = E1000_READ_REG(hw, SWSM);
6571    /* Release both semaphores. */
6572    swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6573    E1000_WRITE_REG(hw, SWSM, swsm);
6574}
6575
6576/******************************************************************************
6577 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6578 * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
6579 * the caller to figure out how to deal with it.
6580 *
6581 * hw - Struct containing variables accessed by shared code
6582 *
6583 * returns: - E1000_BLK_PHY_RESET
6584 *            E1000_SUCCESS
6585 *
6586 *****************************************************************************/
6587int32_t
6588em_check_phy_reset_block(struct em_hw *hw)
6589{
6590    uint32_t manc = 0;
6591    if(hw->mac_type > em_82547_rev_2)
6592        manc = E1000_READ_REG(hw, MANC);
6593    return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6594            E1000_BLK_PHY_RESET : E1000_SUCCESS;
6595}
6596
6597uint8_t
6598em_arc_subsystem_valid(struct em_hw *hw)
6599{
6600    uint32_t fwsm;
6601
6602    /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6603     * may not be provided a DMA clock when no manageability features are
6604     * enabled.  We do not want to perform any reads/writes to these registers
6605     * if this is the case.  We read FWSM to determine the manageability mode.
6606     */
6607    switch (hw->mac_type) {
6608    case em_82573:
6609        fwsm = E1000_READ_REG(hw, FWSM);
6610        if((fwsm & E1000_FWSM_MODE_MASK) != 0)
6611            return TRUE;
6612        break;
6613    default:
6614        break;
6615    }
6616    return FALSE;
6617}
6618
6619
6620
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