1 | /******************************************************************************* |
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2 | |
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3 | Copyright (c) 2001-2005, Intel Corporation |
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4 | All rights reserved. |
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5 | |
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6 | Redistribution and use in source and binary forms, with or without |
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7 | modification, are permitted provided that the following conditions are met: |
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8 | |
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9 | 1. Redistributions of source code must retain the above copyright notice, |
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10 | this list of conditions and the following disclaimer. |
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11 | |
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12 | 2. Redistributions in binary form must reproduce the above copyright |
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13 | notice, this list of conditions and the following disclaimer in the |
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14 | documentation and/or other materials provided with the distribution. |
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15 | |
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16 | 3. Neither the name of the Intel Corporation nor the names of its |
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17 | contributors may be used to endorse or promote products derived from |
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18 | this software without specific prior written permission. |
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19 | |
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20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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30 | POSSIBILITY OF SUCH DAMAGE. |
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31 | |
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32 | *******************************************************************************/ |
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33 | |
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34 | /* if_em_hw.c |
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35 | * Shared functions for accessing and configuring the MAC |
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36 | */ |
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37 | |
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38 | #include <sys/cdefs.h> |
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39 | #ifdef __rtems__ |
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40 | #include "rtemscompat_defs.h" |
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41 | #include "../porting/rtemscompat.h" |
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42 | #include "if_em_hw.h" |
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43 | #else |
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44 | __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/em/if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $"); |
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45 | |
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46 | #include <dev/em/if_em_hw.h> |
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47 | #endif |
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48 | |
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49 | static int32_t em_set_phy_type(struct em_hw *hw); |
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50 | static void em_phy_init_script(struct em_hw *hw); |
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51 | static int32_t em_setup_copper_link(struct em_hw *hw); |
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52 | static int32_t em_setup_fiber_serdes_link(struct em_hw *hw); |
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53 | static int32_t em_adjust_serdes_amplitude(struct em_hw *hw); |
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54 | static int32_t em_phy_force_speed_duplex(struct em_hw *hw); |
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55 | static int32_t em_config_mac_to_phy(struct em_hw *hw); |
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56 | static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl); |
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57 | static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl); |
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58 | static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, |
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59 | uint16_t count); |
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60 | static uint16_t em_shift_in_mdi_bits(struct em_hw *hw); |
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61 | static int32_t em_phy_reset_dsp(struct em_hw *hw); |
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62 | static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, |
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63 | uint16_t words, uint16_t *data); |
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64 | static int32_t em_write_eeprom_microwire(struct em_hw *hw, |
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65 | uint16_t offset, uint16_t words, |
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66 | uint16_t *data); |
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67 | static int32_t em_spi_eeprom_ready(struct em_hw *hw); |
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68 | static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd); |
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69 | static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd); |
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70 | static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, |
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71 | uint16_t count); |
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72 | static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, |
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73 | uint16_t phy_data); |
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74 | static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr, |
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75 | uint16_t *phy_data); |
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76 | static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count); |
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77 | static int32_t em_acquire_eeprom(struct em_hw *hw); |
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78 | static void em_release_eeprom(struct em_hw *hw); |
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79 | static void em_standby_eeprom(struct em_hw *hw); |
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80 | static int32_t em_set_vco_speed(struct em_hw *hw); |
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81 | static int32_t em_polarity_reversal_workaround(struct em_hw *hw); |
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82 | static int32_t em_set_phy_mode(struct em_hw *hw); |
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83 | static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer); |
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84 | static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length); |
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85 | |
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86 | /* IGP cable length table */ |
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87 | static const |
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88 | uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
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89 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
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90 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
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91 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
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92 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
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93 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
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94 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
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95 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
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96 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
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97 | |
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98 | static const |
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99 | uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
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100 | { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, |
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101 | 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58, |
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102 | 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74, |
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103 | 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90, |
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104 | 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108, |
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105 | 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124, |
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106 | 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128, |
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107 | 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128}; |
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108 | |
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109 | |
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110 | /****************************************************************************** |
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111 | * Set the phy type member in the hw struct. |
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112 | * |
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113 | * hw - Struct containing variables accessed by shared code |
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114 | *****************************************************************************/ |
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115 | int32_t |
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116 | em_set_phy_type(struct em_hw *hw) |
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117 | { |
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118 | DEBUGFUNC("em_set_phy_type"); |
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119 | |
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120 | if(hw->mac_type == em_undefined) |
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121 | return -E1000_ERR_PHY_TYPE; |
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122 | |
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123 | switch(hw->phy_id) { |
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124 | case M88E1000_E_PHY_ID: |
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125 | case M88E1000_I_PHY_ID: |
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126 | case M88E1011_I_PHY_ID: |
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127 | case M88E1111_I_PHY_ID: |
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128 | hw->phy_type = em_phy_m88; |
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129 | break; |
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130 | case IGP01E1000_I_PHY_ID: |
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131 | if(hw->mac_type == em_82541 || |
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132 | hw->mac_type == em_82541_rev_2 || |
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133 | hw->mac_type == em_82547 || |
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134 | hw->mac_type == em_82547_rev_2) { |
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135 | hw->phy_type = em_phy_igp; |
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136 | break; |
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137 | } |
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138 | /* Fall Through */ |
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139 | default: |
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140 | /* Should never have loaded on this device */ |
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141 | hw->phy_type = em_phy_undefined; |
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142 | return -E1000_ERR_PHY_TYPE; |
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143 | } |
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144 | |
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145 | return E1000_SUCCESS; |
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146 | } |
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147 | |
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148 | /****************************************************************************** |
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149 | * IGP phy init script - initializes the GbE PHY |
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150 | * |
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151 | * hw - Struct containing variables accessed by shared code |
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152 | *****************************************************************************/ |
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153 | static void |
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154 | em_phy_init_script(struct em_hw *hw) |
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155 | { |
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156 | uint32_t ret_val; |
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157 | uint16_t phy_saved_data; |
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158 | |
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159 | DEBUGFUNC("em_phy_init_script"); |
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160 | |
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161 | if(hw->phy_init_script) { |
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162 | msec_delay(20); |
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163 | |
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164 | /* Save off the current value of register 0x2F5B to be restored at |
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165 | * the end of this routine. */ |
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166 | ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
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167 | |
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168 | /* Disabled the PHY transmitter */ |
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169 | em_write_phy_reg(hw, 0x2F5B, 0x0003); |
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170 | |
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171 | msec_delay(20); |
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172 | |
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173 | em_write_phy_reg(hw,0x0000,0x0140); |
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174 | |
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175 | msec_delay(5); |
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176 | |
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177 | switch(hw->mac_type) { |
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178 | case em_82541: |
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179 | case em_82547: |
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180 | em_write_phy_reg(hw, 0x1F95, 0x0001); |
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181 | |
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182 | em_write_phy_reg(hw, 0x1F71, 0xBD21); |
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183 | |
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184 | em_write_phy_reg(hw, 0x1F79, 0x0018); |
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185 | |
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186 | em_write_phy_reg(hw, 0x1F30, 0x1600); |
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187 | |
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188 | em_write_phy_reg(hw, 0x1F31, 0x0014); |
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189 | |
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190 | em_write_phy_reg(hw, 0x1F32, 0x161C); |
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191 | |
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192 | em_write_phy_reg(hw, 0x1F94, 0x0003); |
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193 | |
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194 | em_write_phy_reg(hw, 0x1F96, 0x003F); |
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195 | |
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196 | em_write_phy_reg(hw, 0x2010, 0x0008); |
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197 | break; |
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198 | |
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199 | case em_82541_rev_2: |
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200 | case em_82547_rev_2: |
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201 | em_write_phy_reg(hw, 0x1F73, 0x0099); |
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202 | break; |
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203 | default: |
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204 | break; |
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205 | } |
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206 | |
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207 | em_write_phy_reg(hw, 0x0000, 0x3300); |
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208 | |
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209 | msec_delay(20); |
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210 | |
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211 | /* Now enable the transmitter */ |
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212 | em_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
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213 | |
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214 | if(hw->mac_type == em_82547) { |
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215 | uint16_t fused, fine, coarse; |
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216 | |
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217 | /* Move to analog registers page */ |
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218 | em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
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219 | |
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220 | if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
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221 | em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
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222 | |
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223 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
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224 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
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225 | |
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226 | if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
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227 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
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228 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
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229 | } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
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230 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
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231 | |
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232 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
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233 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
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234 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
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235 | |
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236 | em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
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237 | em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, |
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238 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
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239 | } |
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240 | } |
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241 | } |
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242 | } |
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243 | |
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244 | /****************************************************************************** |
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245 | * Set the mac type member in the hw struct. |
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246 | * |
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247 | * hw - Struct containing variables accessed by shared code |
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248 | *****************************************************************************/ |
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249 | int32_t |
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250 | em_set_mac_type(struct em_hw *hw) |
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251 | { |
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252 | DEBUGFUNC("em_set_mac_type"); |
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253 | |
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254 | switch (hw->device_id) { |
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255 | case E1000_DEV_ID_82542: |
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256 | switch (hw->revision_id) { |
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257 | case E1000_82542_2_0_REV_ID: |
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258 | hw->mac_type = em_82542_rev2_0; |
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259 | break; |
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260 | case E1000_82542_2_1_REV_ID: |
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261 | hw->mac_type = em_82542_rev2_1; |
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262 | break; |
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263 | default: |
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264 | /* Invalid 82542 revision ID */ |
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265 | return -E1000_ERR_MAC_TYPE; |
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266 | } |
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267 | break; |
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268 | case E1000_DEV_ID_82543GC_FIBER: |
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269 | case E1000_DEV_ID_82543GC_COPPER: |
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270 | hw->mac_type = em_82543; |
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271 | break; |
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272 | case E1000_DEV_ID_82544EI_COPPER: |
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273 | case E1000_DEV_ID_82544EI_FIBER: |
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274 | case E1000_DEV_ID_82544GC_COPPER: |
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275 | case E1000_DEV_ID_82544GC_LOM: |
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276 | hw->mac_type = em_82544; |
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277 | break; |
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278 | case E1000_DEV_ID_82540EM: |
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279 | case E1000_DEV_ID_82540EM_LOM: |
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280 | case E1000_DEV_ID_82540EP: |
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281 | case E1000_DEV_ID_82540EP_LOM: |
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282 | case E1000_DEV_ID_82540EP_LP: |
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283 | hw->mac_type = em_82540; |
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284 | break; |
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285 | case E1000_DEV_ID_82545EM_COPPER: |
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286 | case E1000_DEV_ID_82545EM_FIBER: |
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287 | hw->mac_type = em_82545; |
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288 | break; |
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289 | case E1000_DEV_ID_82545GM_COPPER: |
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290 | case E1000_DEV_ID_82545GM_FIBER: |
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291 | case E1000_DEV_ID_82545GM_SERDES: |
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292 | hw->mac_type = em_82545_rev_3; |
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293 | break; |
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294 | case E1000_DEV_ID_82546EB_COPPER: |
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295 | case E1000_DEV_ID_82546EB_FIBER: |
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296 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
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297 | hw->mac_type = em_82546; |
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298 | break; |
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299 | case E1000_DEV_ID_82546GB_COPPER: |
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300 | case E1000_DEV_ID_82546GB_FIBER: |
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301 | case E1000_DEV_ID_82546GB_SERDES: |
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302 | case E1000_DEV_ID_82546GB_PCIE: |
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303 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
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304 | hw->mac_type = em_82546_rev_3; |
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305 | break; |
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306 | case E1000_DEV_ID_82541EI: |
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307 | case E1000_DEV_ID_82541ER_LOM: |
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308 | case E1000_DEV_ID_82541EI_MOBILE: |
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309 | hw->mac_type = em_82541; |
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310 | break; |
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311 | case E1000_DEV_ID_82541ER: |
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312 | case E1000_DEV_ID_82541GI: |
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313 | case E1000_DEV_ID_82541GI_LF: |
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314 | case E1000_DEV_ID_82541GI_MOBILE: |
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315 | hw->mac_type = em_82541_rev_2; |
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316 | break; |
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317 | case E1000_DEV_ID_82547EI: |
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318 | case E1000_DEV_ID_82547EI_MOBILE: |
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319 | hw->mac_type = em_82547; |
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320 | break; |
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321 | case E1000_DEV_ID_82547GI: |
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322 | hw->mac_type = em_82547_rev_2; |
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323 | break; |
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324 | case E1000_DEV_ID_82573E: |
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325 | case E1000_DEV_ID_82573E_IAMT: |
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326 | hw->mac_type = em_82573; |
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327 | break; |
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328 | default: |
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329 | /* Should never have loaded on this device */ |
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330 | return -E1000_ERR_MAC_TYPE; |
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331 | } |
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332 | |
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333 | switch(hw->mac_type) { |
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334 | case em_82573: |
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335 | hw->eeprom_semaphore_present = TRUE; |
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336 | /* fall through */ |
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337 | case em_82541: |
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338 | case em_82547: |
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339 | case em_82541_rev_2: |
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340 | case em_82547_rev_2: |
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341 | hw->asf_firmware_present = TRUE; |
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342 | break; |
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343 | default: |
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344 | break; |
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345 | } |
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346 | |
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347 | return E1000_SUCCESS; |
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348 | } |
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349 | |
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350 | /***************************************************************************** |
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351 | * Set media type and TBI compatibility. |
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352 | * |
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353 | * hw - Struct containing variables accessed by shared code |
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354 | * **************************************************************************/ |
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355 | void |
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356 | em_set_media_type(struct em_hw *hw) |
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357 | { |
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358 | uint32_t status; |
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359 | |
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360 | DEBUGFUNC("em_set_media_type"); |
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361 | |
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362 | if(hw->mac_type != em_82543) { |
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363 | /* tbi_compatibility is only valid on 82543 */ |
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364 | hw->tbi_compatibility_en = FALSE; |
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365 | } |
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366 | |
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367 | switch (hw->device_id) { |
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368 | case E1000_DEV_ID_82545GM_SERDES: |
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369 | case E1000_DEV_ID_82546GB_SERDES: |
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370 | hw->media_type = em_media_type_internal_serdes; |
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371 | break; |
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372 | default: |
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373 | if(hw->mac_type >= em_82543) { |
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374 | status = E1000_READ_REG(hw, STATUS); |
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375 | if(status & E1000_STATUS_TBIMODE) { |
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376 | hw->media_type = em_media_type_fiber; |
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377 | /* tbi_compatibility not valid on fiber */ |
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378 | hw->tbi_compatibility_en = FALSE; |
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379 | } else { |
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380 | hw->media_type = em_media_type_copper; |
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381 | } |
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382 | } else { |
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383 | /* This is an 82542 (fiber only) */ |
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384 | hw->media_type = em_media_type_fiber; |
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385 | } |
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386 | } |
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387 | } |
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388 | |
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389 | /****************************************************************************** |
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390 | * Reset the transmit and receive units; mask and clear all interrupts. |
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391 | * |
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392 | * hw - Struct containing variables accessed by shared code |
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393 | *****************************************************************************/ |
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394 | int32_t |
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395 | em_reset_hw(struct em_hw *hw) |
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396 | { |
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397 | uint32_t ctrl; |
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398 | uint32_t ctrl_ext; |
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399 | uint32_t icr; |
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400 | uint32_t manc; |
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401 | uint32_t led_ctrl; |
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402 | uint32_t timeout; |
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403 | uint32_t extcnf_ctrl; |
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404 | int32_t ret_val; |
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405 | |
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406 | DEBUGFUNC("em_reset_hw"); |
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407 | |
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408 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
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409 | if(hw->mac_type == em_82542_rev2_0) { |
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410 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
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411 | em_pci_clear_mwi(hw); |
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412 | } |
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413 | |
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414 | if(hw->bus_type == em_bus_type_pci_express) { |
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415 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
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416 | * on the last TLP read/write transaction when MAC is reset. |
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417 | */ |
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418 | if(em_disable_pciex_master(hw) != E1000_SUCCESS) { |
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419 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
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420 | } |
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421 | } |
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422 | |
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423 | /* Clear interrupt mask to stop board from generating interrupts */ |
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424 | DEBUGOUT("Masking off all interrupts\n"); |
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425 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
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426 | |
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427 | /* Disable the Transmit and Receive units. Then delay to allow |
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428 | * any pending transactions to complete before we hit the MAC with |
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429 | * the global reset. |
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430 | */ |
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431 | E1000_WRITE_REG(hw, RCTL, 0); |
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432 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
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433 | E1000_WRITE_FLUSH(hw); |
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434 | |
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435 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
---|
436 | hw->tbi_compatibility_on = FALSE; |
---|
437 | |
---|
438 | /* Delay to allow any outstanding PCI transactions to complete before |
---|
439 | * resetting the device |
---|
440 | */ |
---|
441 | msec_delay(10); |
---|
442 | |
---|
443 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
444 | |
---|
445 | /* Must reset the PHY before resetting the MAC */ |
---|
446 | if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
---|
447 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
---|
448 | msec_delay(5); |
---|
449 | } |
---|
450 | |
---|
451 | /* Must acquire the MDIO ownership before MAC reset. |
---|
452 | * Ownership defaults to firmware after a reset. */ |
---|
453 | if(hw->mac_type == em_82573) { |
---|
454 | timeout = 10; |
---|
455 | |
---|
456 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
---|
457 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
---|
458 | |
---|
459 | do { |
---|
460 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
---|
461 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
---|
462 | |
---|
463 | if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
---|
464 | break; |
---|
465 | else |
---|
466 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
---|
467 | |
---|
468 | msec_delay(2); |
---|
469 | timeout--; |
---|
470 | } while(timeout); |
---|
471 | } |
---|
472 | |
---|
473 | /* Issue a global reset to the MAC. This will reset the chip's |
---|
474 | * transmit, receive, DMA, and link units. It will not effect |
---|
475 | * the current PCI configuration. The global reset bit is self- |
---|
476 | * clearing, and should clear within a microsecond. |
---|
477 | */ |
---|
478 | DEBUGOUT("Issuing a global reset to MAC\n"); |
---|
479 | |
---|
480 | switch(hw->mac_type) { |
---|
481 | case em_82544: |
---|
482 | case em_82540: |
---|
483 | case em_82545: |
---|
484 | #ifndef __arm__ |
---|
485 | case em_82546: |
---|
486 | #endif |
---|
487 | case em_82541: |
---|
488 | case em_82541_rev_2: |
---|
489 | /* These controllers can't ack the 64-bit write when issuing the |
---|
490 | * reset, so use IO-mapping as a workaround to issue the reset */ |
---|
491 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
---|
492 | break; |
---|
493 | case em_82545_rev_3: |
---|
494 | case em_82546_rev_3: |
---|
495 | /* Reset is performed on a shadow of the control register */ |
---|
496 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
---|
497 | break; |
---|
498 | default: |
---|
499 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
---|
500 | break; |
---|
501 | } |
---|
502 | |
---|
503 | /* After MAC reset, force reload of EEPROM to restore power-on settings to |
---|
504 | * device. Later controllers reload the EEPROM automatically, so just wait |
---|
505 | * for reload to complete. |
---|
506 | */ |
---|
507 | switch(hw->mac_type) { |
---|
508 | case em_82542_rev2_0: |
---|
509 | case em_82542_rev2_1: |
---|
510 | case em_82543: |
---|
511 | case em_82544: |
---|
512 | /* Wait for reset to complete */ |
---|
513 | usec_delay(10); |
---|
514 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
---|
515 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
---|
516 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
---|
517 | E1000_WRITE_FLUSH(hw); |
---|
518 | /* Wait for EEPROM reload */ |
---|
519 | msec_delay(2); |
---|
520 | break; |
---|
521 | case em_82541: |
---|
522 | case em_82541_rev_2: |
---|
523 | case em_82547: |
---|
524 | case em_82547_rev_2: |
---|
525 | /* Wait for EEPROM reload */ |
---|
526 | msec_delay(20); |
---|
527 | break; |
---|
528 | case em_82573: |
---|
529 | usec_delay(10); |
---|
530 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
---|
531 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
---|
532 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
---|
533 | E1000_WRITE_FLUSH(hw); |
---|
534 | /* fall through */ |
---|
535 | ret_val = em_get_auto_rd_done(hw); |
---|
536 | if(ret_val) |
---|
537 | /* We don't want to continue accessing MAC registers. */ |
---|
538 | return ret_val; |
---|
539 | break; |
---|
540 | default: |
---|
541 | /* Wait for EEPROM reload (it happens automatically) */ |
---|
542 | msec_delay(5); |
---|
543 | break; |
---|
544 | } |
---|
545 | |
---|
546 | /* Disable HW ARPs on ASF enabled adapters */ |
---|
547 | if(hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) { |
---|
548 | manc = E1000_READ_REG(hw, MANC); |
---|
549 | manc &= ~(E1000_MANC_ARP_EN); |
---|
550 | E1000_WRITE_REG(hw, MANC, manc); |
---|
551 | } |
---|
552 | |
---|
553 | if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
---|
554 | em_phy_init_script(hw); |
---|
555 | |
---|
556 | /* Configure activity LED after PHY reset */ |
---|
557 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
---|
558 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
---|
559 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
---|
560 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
---|
561 | } |
---|
562 | |
---|
563 | /* Clear interrupt mask to stop board from generating interrupts */ |
---|
564 | DEBUGOUT("Masking off all interrupts\n"); |
---|
565 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
---|
566 | |
---|
567 | /* Clear any pending interrupt events. */ |
---|
568 | icr = E1000_READ_REG(hw, ICR); |
---|
569 | |
---|
570 | /* If MWI was previously enabled, reenable it. */ |
---|
571 | if(hw->mac_type == em_82542_rev2_0) { |
---|
572 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
---|
573 | em_pci_set_mwi(hw); |
---|
574 | } |
---|
575 | #ifdef __rtems__ |
---|
576 | msec_delay(100); |
---|
577 | #endif |
---|
578 | |
---|
579 | return E1000_SUCCESS; |
---|
580 | } |
---|
581 | |
---|
582 | /****************************************************************************** |
---|
583 | * Performs basic configuration of the adapter. |
---|
584 | * |
---|
585 | * hw - Struct containing variables accessed by shared code |
---|
586 | * |
---|
587 | * Assumes that the controller has previously been reset and is in a |
---|
588 | * post-reset uninitialized state. Initializes the receive address registers, |
---|
589 | * multicast table, and VLAN filter table. Calls routines to setup link |
---|
590 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
---|
591 | * the transmit and receive units disabled and uninitialized. |
---|
592 | *****************************************************************************/ |
---|
593 | int32_t |
---|
594 | em_init_hw(struct em_hw *hw) |
---|
595 | { |
---|
596 | uint32_t ctrl; |
---|
597 | uint32_t i; |
---|
598 | int32_t ret_val; |
---|
599 | uint16_t pcix_cmd_word; |
---|
600 | uint16_t pcix_stat_hi_word; |
---|
601 | uint16_t cmd_mmrbc; |
---|
602 | uint16_t stat_mmrbc; |
---|
603 | uint32_t mta_size; |
---|
604 | |
---|
605 | DEBUGFUNC("em_init_hw"); |
---|
606 | |
---|
607 | /* Initialize Identification LED */ |
---|
608 | ret_val = em_id_led_init(hw); |
---|
609 | if(ret_val) { |
---|
610 | DEBUGOUT("Error Initializing Identification LED\n"); |
---|
611 | return ret_val; |
---|
612 | } |
---|
613 | |
---|
614 | /* Set the media type and TBI compatibility */ |
---|
615 | em_set_media_type(hw); |
---|
616 | |
---|
617 | /* Disabling VLAN filtering. */ |
---|
618 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
---|
619 | if (hw->mac_type < em_82545_rev_3) |
---|
620 | E1000_WRITE_REG(hw, VET, 0); |
---|
621 | em_clear_vfta(hw); |
---|
622 | |
---|
623 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
---|
624 | if(hw->mac_type == em_82542_rev2_0) { |
---|
625 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
---|
626 | em_pci_clear_mwi(hw); |
---|
627 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
---|
628 | E1000_WRITE_FLUSH(hw); |
---|
629 | msec_delay(5); |
---|
630 | } |
---|
631 | |
---|
632 | /* Setup the receive address. This involves initializing all of the Receive |
---|
633 | * Address Registers (RARs 0 - 15). |
---|
634 | */ |
---|
635 | em_init_rx_addrs(hw); |
---|
636 | |
---|
637 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
---|
638 | if(hw->mac_type == em_82542_rev2_0) { |
---|
639 | E1000_WRITE_REG(hw, RCTL, 0); |
---|
640 | E1000_WRITE_FLUSH(hw); |
---|
641 | msec_delay(1); |
---|
642 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
---|
643 | em_pci_set_mwi(hw); |
---|
644 | } |
---|
645 | |
---|
646 | /* Zero out the Multicast HASH table */ |
---|
647 | DEBUGOUT("Zeroing the MTA\n"); |
---|
648 | mta_size = E1000_MC_TBL_SIZE; |
---|
649 | for(i = 0; i < mta_size; i++) |
---|
650 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
---|
651 | |
---|
652 | /* Set the PCI priority bit correctly in the CTRL register. This |
---|
653 | * determines if the adapter gives priority to receives, or if it |
---|
654 | * gives equal priority to transmits and receives. Valid only on |
---|
655 | * 82542 and 82543 silicon. |
---|
656 | */ |
---|
657 | if(hw->dma_fairness && hw->mac_type <= em_82543) { |
---|
658 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
659 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
---|
660 | } |
---|
661 | |
---|
662 | switch(hw->mac_type) { |
---|
663 | case em_82545_rev_3: |
---|
664 | case em_82546_rev_3: |
---|
665 | break; |
---|
666 | default: |
---|
667 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
---|
668 | if(hw->bus_type == em_bus_type_pcix) { |
---|
669 | em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); |
---|
670 | em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, |
---|
671 | &pcix_stat_hi_word); |
---|
672 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> |
---|
673 | PCIX_COMMAND_MMRBC_SHIFT; |
---|
674 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> |
---|
675 | PCIX_STATUS_HI_MMRBC_SHIFT; |
---|
676 | if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
---|
677 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
---|
678 | if(cmd_mmrbc > stat_mmrbc) { |
---|
679 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
---|
680 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; |
---|
681 | em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, |
---|
682 | &pcix_cmd_word); |
---|
683 | } |
---|
684 | } |
---|
685 | break; |
---|
686 | } |
---|
687 | |
---|
688 | /* Call a subroutine to configure the link and setup flow control. */ |
---|
689 | ret_val = em_setup_link(hw); |
---|
690 | |
---|
691 | /* Set the transmit descriptor write-back policy */ |
---|
692 | if(hw->mac_type > em_82544) { |
---|
693 | ctrl = E1000_READ_REG(hw, TXDCTL); |
---|
694 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
---|
695 | switch (hw->mac_type) { |
---|
696 | default: |
---|
697 | break; |
---|
698 | case em_82573: |
---|
699 | ctrl |= E1000_TXDCTL_COUNT_DESC; |
---|
700 | break; |
---|
701 | } |
---|
702 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
---|
703 | } |
---|
704 | |
---|
705 | if (hw->mac_type == em_82573) { |
---|
706 | em_enable_tx_pkt_filtering(hw); |
---|
707 | } |
---|
708 | |
---|
709 | |
---|
710 | /* Clear all of the statistics registers (clear on read). It is |
---|
711 | * important that we do this after we have tried to establish link |
---|
712 | * because the symbol error count will increment wildly if there |
---|
713 | * is no link. |
---|
714 | */ |
---|
715 | em_clear_hw_cntrs(hw); |
---|
716 | |
---|
717 | return ret_val; |
---|
718 | } |
---|
719 | |
---|
720 | /****************************************************************************** |
---|
721 | * Adjust SERDES output amplitude based on EEPROM setting. |
---|
722 | * |
---|
723 | * hw - Struct containing variables accessed by shared code. |
---|
724 | *****************************************************************************/ |
---|
725 | static int32_t |
---|
726 | em_adjust_serdes_amplitude(struct em_hw *hw) |
---|
727 | { |
---|
728 | uint16_t eeprom_data; |
---|
729 | int32_t ret_val; |
---|
730 | |
---|
731 | DEBUGFUNC("em_adjust_serdes_amplitude"); |
---|
732 | |
---|
733 | if(hw->media_type != em_media_type_internal_serdes) |
---|
734 | return E1000_SUCCESS; |
---|
735 | |
---|
736 | switch(hw->mac_type) { |
---|
737 | case em_82545_rev_3: |
---|
738 | case em_82546_rev_3: |
---|
739 | break; |
---|
740 | default: |
---|
741 | return E1000_SUCCESS; |
---|
742 | } |
---|
743 | |
---|
744 | ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); |
---|
745 | if (ret_val) { |
---|
746 | return ret_val; |
---|
747 | } |
---|
748 | |
---|
749 | if(eeprom_data != EEPROM_RESERVED_WORD) { |
---|
750 | /* Adjust SERDES output amplitude only. */ |
---|
751 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
---|
752 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
---|
753 | if(ret_val) |
---|
754 | return ret_val; |
---|
755 | } |
---|
756 | |
---|
757 | return E1000_SUCCESS; |
---|
758 | } |
---|
759 | |
---|
760 | /****************************************************************************** |
---|
761 | * Configures flow control and link settings. |
---|
762 | * |
---|
763 | * hw - Struct containing variables accessed by shared code |
---|
764 | * |
---|
765 | * Determines which flow control settings to use. Calls the apropriate media- |
---|
766 | * specific link configuration function. Configures the flow control settings. |
---|
767 | * Assuming the adapter has a valid link partner, a valid link should be |
---|
768 | * established. Assumes the hardware has previously been reset and the |
---|
769 | * transmitter and receiver are not enabled. |
---|
770 | *****************************************************************************/ |
---|
771 | int32_t |
---|
772 | em_setup_link(struct em_hw *hw) |
---|
773 | { |
---|
774 | uint32_t ctrl_ext; |
---|
775 | int32_t ret_val; |
---|
776 | uint16_t eeprom_data; |
---|
777 | |
---|
778 | DEBUGFUNC("em_setup_link"); |
---|
779 | |
---|
780 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
---|
781 | * that determine the hardware's default PAUSE (flow control) mode, |
---|
782 | * a bit that determines whether the HW defaults to enabling or |
---|
783 | * disabling auto-negotiation, and the direction of the |
---|
784 | * SW defined pins. If there is no SW over-ride of the flow |
---|
785 | * control setting, then the variable hw->fc will |
---|
786 | * be initialized based on a value in the EEPROM. |
---|
787 | */ |
---|
788 | if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) { |
---|
789 | DEBUGOUT("EEPROM Read Error\n"); |
---|
790 | return -E1000_ERR_EEPROM; |
---|
791 | } |
---|
792 | |
---|
793 | if(hw->fc == em_fc_default) { |
---|
794 | if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
---|
795 | hw->fc = em_fc_none; |
---|
796 | else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
---|
797 | EEPROM_WORD0F_ASM_DIR) |
---|
798 | hw->fc = em_fc_tx_pause; |
---|
799 | else |
---|
800 | hw->fc = em_fc_full; |
---|
801 | } |
---|
802 | |
---|
803 | /* We want to save off the original Flow Control configuration just |
---|
804 | * in case we get disconnected and then reconnected into a different |
---|
805 | * hub or switch with different Flow Control capabilities. |
---|
806 | */ |
---|
807 | if(hw->mac_type == em_82542_rev2_0) |
---|
808 | hw->fc &= (~em_fc_tx_pause); |
---|
809 | |
---|
810 | if((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) |
---|
811 | hw->fc &= (~em_fc_rx_pause); |
---|
812 | |
---|
813 | hw->original_fc = hw->fc; |
---|
814 | |
---|
815 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
---|
816 | |
---|
817 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
---|
818 | * polarity value for the SW controlled pins, and setup the |
---|
819 | * Extended Device Control reg with that info. |
---|
820 | * This is needed because one of the SW controlled pins is used for |
---|
821 | * signal detection. So this should be done before em_setup_pcs_link() |
---|
822 | * or em_phy_setup() is called. |
---|
823 | */ |
---|
824 | if(hw->mac_type == em_82543) { |
---|
825 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
---|
826 | SWDPIO__EXT_SHIFT); |
---|
827 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
---|
828 | } |
---|
829 | |
---|
830 | /* Call the necessary subroutine to configure the link. */ |
---|
831 | ret_val = (hw->media_type == em_media_type_copper) ? |
---|
832 | em_setup_copper_link(hw) : |
---|
833 | em_setup_fiber_serdes_link(hw); |
---|
834 | |
---|
835 | /* Initialize the flow control address, type, and PAUSE timer |
---|
836 | * registers to their default values. This is done even if flow |
---|
837 | * control is disabled, because it does not hurt anything to |
---|
838 | * initialize these registers. |
---|
839 | */ |
---|
840 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); |
---|
841 | |
---|
842 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
---|
843 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
---|
844 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
---|
845 | |
---|
846 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
---|
847 | |
---|
848 | /* Set the flow control receive threshold registers. Normally, |
---|
849 | * these registers will be set to a default threshold that may be |
---|
850 | * adjusted later by the driver's runtime code. However, if the |
---|
851 | * ability to transmit pause frames in not enabled, then these |
---|
852 | * registers will be set to 0. |
---|
853 | */ |
---|
854 | if(!(hw->fc & em_fc_tx_pause)) { |
---|
855 | E1000_WRITE_REG(hw, FCRTL, 0); |
---|
856 | E1000_WRITE_REG(hw, FCRTH, 0); |
---|
857 | } else { |
---|
858 | /* We need to set up the Receive Threshold high and low water marks |
---|
859 | * as well as (optionally) enabling the transmission of XON frames. |
---|
860 | */ |
---|
861 | if(hw->fc_send_xon) { |
---|
862 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
---|
863 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
---|
864 | } else { |
---|
865 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
---|
866 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
---|
867 | } |
---|
868 | } |
---|
869 | return ret_val; |
---|
870 | } |
---|
871 | |
---|
872 | /****************************************************************************** |
---|
873 | * Sets up link for a fiber based or serdes based adapter |
---|
874 | * |
---|
875 | * hw - Struct containing variables accessed by shared code |
---|
876 | * |
---|
877 | * Manipulates Physical Coding Sublayer functions in order to configure |
---|
878 | * link. Assumes the hardware has been previously reset and the transmitter |
---|
879 | * and receiver are not enabled. |
---|
880 | *****************************************************************************/ |
---|
881 | static int32_t |
---|
882 | em_setup_fiber_serdes_link(struct em_hw *hw) |
---|
883 | { |
---|
884 | uint32_t ctrl; |
---|
885 | uint32_t status; |
---|
886 | uint32_t txcw = 0; |
---|
887 | uint32_t i; |
---|
888 | uint32_t signal = 0; |
---|
889 | int32_t ret_val; |
---|
890 | |
---|
891 | DEBUGFUNC("em_setup_fiber_serdes_link"); |
---|
892 | |
---|
893 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
---|
894 | * set when the optics detect a signal. On older adapters, it will be |
---|
895 | * cleared when there is a signal. This applies to fiber media only. |
---|
896 | * If we're on serdes media, adjust the output amplitude to value set in |
---|
897 | * the EEPROM. |
---|
898 | */ |
---|
899 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
900 | if(hw->media_type == em_media_type_fiber) |
---|
901 | signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; |
---|
902 | |
---|
903 | ret_val = em_adjust_serdes_amplitude(hw); |
---|
904 | if(ret_val) |
---|
905 | return ret_val; |
---|
906 | |
---|
907 | /* Take the link out of reset */ |
---|
908 | ctrl &= ~(E1000_CTRL_LRST); |
---|
909 | |
---|
910 | /* Adjust VCO speed to improve BER performance */ |
---|
911 | ret_val = em_set_vco_speed(hw); |
---|
912 | if(ret_val) |
---|
913 | return ret_val; |
---|
914 | |
---|
915 | em_config_collision_dist(hw); |
---|
916 | |
---|
917 | /* Check for a software override of the flow control settings, and setup |
---|
918 | * the device accordingly. If auto-negotiation is enabled, then software |
---|
919 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
---|
920 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
---|
921 | * auto-negotiation is disabled, then software will have to manually |
---|
922 | * configure the two flow control enable bits in the CTRL register. |
---|
923 | * |
---|
924 | * The possible values of the "fc" parameter are: |
---|
925 | * 0: Flow control is completely disabled |
---|
926 | * 1: Rx flow control is enabled (we can receive pause frames, but |
---|
927 | * not send pause frames). |
---|
928 | * 2: Tx flow control is enabled (we can send pause frames but we do |
---|
929 | * not support receiving pause frames). |
---|
930 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
---|
931 | */ |
---|
932 | switch (hw->fc) { |
---|
933 | case em_fc_none: |
---|
934 | /* Flow control is completely disabled by a software over-ride. */ |
---|
935 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
---|
936 | break; |
---|
937 | case em_fc_rx_pause: |
---|
938 | /* RX Flow control is enabled and TX Flow control is disabled by a |
---|
939 | * software over-ride. Since there really isn't a way to advertise |
---|
940 | * that we are capable of RX Pause ONLY, we will advertise that we |
---|
941 | * support both symmetric and asymmetric RX PAUSE. Later, we will |
---|
942 | * disable the adapter's ability to send PAUSE frames. |
---|
943 | */ |
---|
944 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
---|
945 | break; |
---|
946 | case em_fc_tx_pause: |
---|
947 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
---|
948 | * software over-ride. |
---|
949 | */ |
---|
950 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
---|
951 | break; |
---|
952 | case em_fc_full: |
---|
953 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
---|
954 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
---|
955 | break; |
---|
956 | default: |
---|
957 | DEBUGOUT("Flow control param set incorrectly\n"); |
---|
958 | return -E1000_ERR_CONFIG; |
---|
959 | break; |
---|
960 | } |
---|
961 | |
---|
962 | /* Since auto-negotiation is enabled, take the link out of reset (the link |
---|
963 | * will be in reset, because we previously reset the chip). This will |
---|
964 | * restart auto-negotiation. If auto-neogtiation is successful then the |
---|
965 | * link-up status bit will be set and the flow control enable bits (RFCE |
---|
966 | * and TFCE) will be set according to their negotiated value. |
---|
967 | */ |
---|
968 | DEBUGOUT("Auto-negotiation enabled\n"); |
---|
969 | |
---|
970 | E1000_WRITE_REG(hw, TXCW, txcw); |
---|
971 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
972 | E1000_WRITE_FLUSH(hw); |
---|
973 | |
---|
974 | hw->txcw = txcw; |
---|
975 | msec_delay(1); |
---|
976 | |
---|
977 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
---|
978 | * indication in the Device Status Register. Time-out if a link isn't |
---|
979 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
---|
980 | * less than 500 milliseconds even if the other end is doing it in SW). |
---|
981 | * For internal serdes, we just assume a signal is present, then poll. |
---|
982 | */ |
---|
983 | if(hw->media_type == em_media_type_internal_serdes || |
---|
984 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
---|
985 | DEBUGOUT("Looking for Link\n"); |
---|
986 | for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
---|
987 | msec_delay(10); |
---|
988 | status = E1000_READ_REG(hw, STATUS); |
---|
989 | if(status & E1000_STATUS_LU) break; |
---|
990 | } |
---|
991 | if(i == (LINK_UP_TIMEOUT / 10)) { |
---|
992 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
---|
993 | hw->autoneg_failed = 1; |
---|
994 | /* AutoNeg failed to achieve a link, so we'll call |
---|
995 | * em_check_for_link. This routine will force the link up if |
---|
996 | * we detect a signal. This will allow us to communicate with |
---|
997 | * non-autonegotiating link partners. |
---|
998 | */ |
---|
999 | ret_val = em_check_for_link(hw); |
---|
1000 | if(ret_val) { |
---|
1001 | DEBUGOUT("Error while checking for link\n"); |
---|
1002 | return ret_val; |
---|
1003 | } |
---|
1004 | hw->autoneg_failed = 0; |
---|
1005 | } else { |
---|
1006 | hw->autoneg_failed = 0; |
---|
1007 | DEBUGOUT("Valid Link Found\n"); |
---|
1008 | } |
---|
1009 | } else { |
---|
1010 | DEBUGOUT("No Signal Detected\n"); |
---|
1011 | } |
---|
1012 | return E1000_SUCCESS; |
---|
1013 | } |
---|
1014 | |
---|
1015 | /****************************************************************************** |
---|
1016 | * Make sure we have a valid PHY and change PHY mode before link setup. |
---|
1017 | * |
---|
1018 | * hw - Struct containing variables accessed by shared code |
---|
1019 | ******************************************************************************/ |
---|
1020 | static int32_t |
---|
1021 | em_copper_link_preconfig(struct em_hw *hw) |
---|
1022 | { |
---|
1023 | uint32_t ctrl; |
---|
1024 | int32_t ret_val; |
---|
1025 | uint16_t phy_data; |
---|
1026 | |
---|
1027 | DEBUGFUNC("em_copper_link_preconfig"); |
---|
1028 | |
---|
1029 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
1030 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
---|
1031 | * the PHY speed and duplex configuration is. In addition, we need to |
---|
1032 | * perform a hardware reset on the PHY to take it out of reset. |
---|
1033 | */ |
---|
1034 | if(hw->mac_type > em_82543) { |
---|
1035 | ctrl |= E1000_CTRL_SLU; |
---|
1036 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
---|
1037 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
1038 | } else { |
---|
1039 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
---|
1040 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
1041 | ret_val = em_phy_hw_reset(hw); |
---|
1042 | if(ret_val) |
---|
1043 | return ret_val; |
---|
1044 | } |
---|
1045 | |
---|
1046 | /* Make sure we have a valid PHY */ |
---|
1047 | ret_val = em_detect_gig_phy(hw); |
---|
1048 | if(ret_val) { |
---|
1049 | DEBUGOUT("Error, did not detect valid phy.\n"); |
---|
1050 | return ret_val; |
---|
1051 | } |
---|
1052 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
---|
1053 | |
---|
1054 | /* Set PHY to class A mode (if necessary) */ |
---|
1055 | ret_val = em_set_phy_mode(hw); |
---|
1056 | if(ret_val) |
---|
1057 | return ret_val; |
---|
1058 | |
---|
1059 | if((hw->mac_type == em_82545_rev_3) || |
---|
1060 | (hw->mac_type == em_82546_rev_3)) { |
---|
1061 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
---|
1062 | phy_data |= 0x00000008; |
---|
1063 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
---|
1064 | } |
---|
1065 | |
---|
1066 | if(hw->mac_type <= em_82543 || |
---|
1067 | hw->mac_type == em_82541 || hw->mac_type == em_82547 || |
---|
1068 | hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) |
---|
1069 | hw->phy_reset_disable = FALSE; |
---|
1070 | |
---|
1071 | return E1000_SUCCESS; |
---|
1072 | } |
---|
1073 | |
---|
1074 | |
---|
1075 | /******************************************************************** |
---|
1076 | * Copper link setup for em_phy_igp series. |
---|
1077 | * |
---|
1078 | * hw - Struct containing variables accessed by shared code |
---|
1079 | *********************************************************************/ |
---|
1080 | static int32_t |
---|
1081 | em_copper_link_igp_setup(struct em_hw *hw) |
---|
1082 | { |
---|
1083 | uint32_t led_ctrl; |
---|
1084 | int32_t ret_val; |
---|
1085 | uint16_t phy_data; |
---|
1086 | |
---|
1087 | DEBUGFUNC("em_copper_link_igp_setup"); |
---|
1088 | |
---|
1089 | if (hw->phy_reset_disable) |
---|
1090 | return E1000_SUCCESS; |
---|
1091 | |
---|
1092 | ret_val = em_phy_reset(hw); |
---|
1093 | if (ret_val) { |
---|
1094 | DEBUGOUT("Error Resetting the PHY\n"); |
---|
1095 | return ret_val; |
---|
1096 | } |
---|
1097 | |
---|
1098 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
---|
1099 | msec_delay(15); |
---|
1100 | |
---|
1101 | /* Configure activity LED after PHY reset */ |
---|
1102 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
---|
1103 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
---|
1104 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
---|
1105 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
---|
1106 | |
---|
1107 | /* disable lplu d3 during driver init */ |
---|
1108 | ret_val = em_set_d3_lplu_state(hw, FALSE); |
---|
1109 | if (ret_val) { |
---|
1110 | DEBUGOUT("Error Disabling LPLU D3\n"); |
---|
1111 | return ret_val; |
---|
1112 | } |
---|
1113 | |
---|
1114 | /* disable lplu d0 during driver init */ |
---|
1115 | ret_val = em_set_d0_lplu_state(hw, FALSE); |
---|
1116 | if (ret_val) { |
---|
1117 | DEBUGOUT("Error Disabling LPLU D0\n"); |
---|
1118 | return ret_val; |
---|
1119 | } |
---|
1120 | /* Configure mdi-mdix settings */ |
---|
1121 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
---|
1122 | if (ret_val) |
---|
1123 | return ret_val; |
---|
1124 | |
---|
1125 | if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
---|
1126 | hw->dsp_config_state = em_dsp_config_disabled; |
---|
1127 | /* Force MDI for earlier revs of the IGP PHY */ |
---|
1128 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
---|
1129 | hw->mdix = 1; |
---|
1130 | |
---|
1131 | } else { |
---|
1132 | hw->dsp_config_state = em_dsp_config_enabled; |
---|
1133 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
---|
1134 | |
---|
1135 | switch (hw->mdix) { |
---|
1136 | case 1: |
---|
1137 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
---|
1138 | break; |
---|
1139 | case 2: |
---|
1140 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
---|
1141 | break; |
---|
1142 | case 0: |
---|
1143 | default: |
---|
1144 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
---|
1145 | break; |
---|
1146 | } |
---|
1147 | } |
---|
1148 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
---|
1149 | if(ret_val) |
---|
1150 | return ret_val; |
---|
1151 | |
---|
1152 | /* set auto-master slave resolution settings */ |
---|
1153 | if(hw->autoneg) { |
---|
1154 | em_ms_type phy_ms_setting = hw->master_slave; |
---|
1155 | |
---|
1156 | if(hw->ffe_config_state == em_ffe_config_active) |
---|
1157 | hw->ffe_config_state = em_ffe_config_enabled; |
---|
1158 | |
---|
1159 | if(hw->dsp_config_state == em_dsp_config_activated) |
---|
1160 | hw->dsp_config_state = em_dsp_config_enabled; |
---|
1161 | |
---|
1162 | /* when autonegotiation advertisment is only 1000Mbps then we |
---|
1163 | * should disable SmartSpeed and enable Auto MasterSlave |
---|
1164 | * resolution as hardware default. */ |
---|
1165 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
---|
1166 | /* Disable SmartSpeed */ |
---|
1167 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
---|
1168 | if(ret_val) |
---|
1169 | return ret_val; |
---|
1170 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
---|
1171 | ret_val = em_write_phy_reg(hw, |
---|
1172 | IGP01E1000_PHY_PORT_CONFIG, |
---|
1173 | phy_data); |
---|
1174 | if(ret_val) |
---|
1175 | return ret_val; |
---|
1176 | /* Set auto Master/Slave resolution process */ |
---|
1177 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
---|
1178 | if(ret_val) |
---|
1179 | return ret_val; |
---|
1180 | phy_data &= ~CR_1000T_MS_ENABLE; |
---|
1181 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
---|
1182 | if(ret_val) |
---|
1183 | return ret_val; |
---|
1184 | } |
---|
1185 | |
---|
1186 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
---|
1187 | if(ret_val) |
---|
1188 | return ret_val; |
---|
1189 | |
---|
1190 | /* load defaults for future use */ |
---|
1191 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
---|
1192 | ((phy_data & CR_1000T_MS_VALUE) ? |
---|
1193 | em_ms_force_master : |
---|
1194 | em_ms_force_slave) : |
---|
1195 | em_ms_auto; |
---|
1196 | |
---|
1197 | switch (phy_ms_setting) { |
---|
1198 | case em_ms_force_master: |
---|
1199 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
---|
1200 | break; |
---|
1201 | case em_ms_force_slave: |
---|
1202 | phy_data |= CR_1000T_MS_ENABLE; |
---|
1203 | phy_data &= ~(CR_1000T_MS_VALUE); |
---|
1204 | break; |
---|
1205 | case em_ms_auto: |
---|
1206 | phy_data &= ~CR_1000T_MS_ENABLE; |
---|
1207 | default: |
---|
1208 | break; |
---|
1209 | } |
---|
1210 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
---|
1211 | if(ret_val) |
---|
1212 | return ret_val; |
---|
1213 | } |
---|
1214 | |
---|
1215 | return E1000_SUCCESS; |
---|
1216 | } |
---|
1217 | |
---|
1218 | |
---|
1219 | /******************************************************************** |
---|
1220 | * Copper link setup for em_phy_m88 series. |
---|
1221 | * |
---|
1222 | * hw - Struct containing variables accessed by shared code |
---|
1223 | *********************************************************************/ |
---|
1224 | static int32_t |
---|
1225 | em_copper_link_mgp_setup(struct em_hw *hw) |
---|
1226 | { |
---|
1227 | int32_t ret_val; |
---|
1228 | uint16_t phy_data; |
---|
1229 | |
---|
1230 | DEBUGFUNC("em_copper_link_mgp_setup"); |
---|
1231 | |
---|
1232 | if(hw->phy_reset_disable) |
---|
1233 | return E1000_SUCCESS; |
---|
1234 | |
---|
1235 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
---|
1236 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
---|
1237 | if(ret_val) |
---|
1238 | return ret_val; |
---|
1239 | |
---|
1240 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
---|
1241 | |
---|
1242 | /* Options: |
---|
1243 | * MDI/MDI-X = 0 (default) |
---|
1244 | * 0 - Auto for all speeds |
---|
1245 | * 1 - MDI mode |
---|
1246 | * 2 - MDI-X mode |
---|
1247 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
---|
1248 | */ |
---|
1249 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
---|
1250 | |
---|
1251 | switch (hw->mdix) { |
---|
1252 | case 1: |
---|
1253 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
---|
1254 | break; |
---|
1255 | case 2: |
---|
1256 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
---|
1257 | break; |
---|
1258 | case 3: |
---|
1259 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
---|
1260 | break; |
---|
1261 | case 0: |
---|
1262 | default: |
---|
1263 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
---|
1264 | break; |
---|
1265 | } |
---|
1266 | |
---|
1267 | /* Options: |
---|
1268 | * disable_polarity_correction = 0 (default) |
---|
1269 | * Automatic Correction for Reversed Cable Polarity |
---|
1270 | * 0 - Disabled |
---|
1271 | * 1 - Enabled |
---|
1272 | */ |
---|
1273 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
---|
1274 | if(hw->disable_polarity_correction == 1) |
---|
1275 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
---|
1276 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
---|
1277 | if(ret_val) |
---|
1278 | return ret_val; |
---|
1279 | |
---|
1280 | /* Force TX_CLK in the Extended PHY Specific Control Register |
---|
1281 | * to 25MHz clock. |
---|
1282 | */ |
---|
1283 | ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
---|
1284 | if(ret_val) |
---|
1285 | return ret_val; |
---|
1286 | |
---|
1287 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
---|
1288 | |
---|
1289 | if (hw->phy_revision < M88E1011_I_REV_4) { |
---|
1290 | /* Configure Master and Slave downshift values */ |
---|
1291 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
---|
1292 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
---|
1293 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
---|
1294 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
---|
1295 | ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
---|
1296 | if(ret_val) |
---|
1297 | return ret_val; |
---|
1298 | } |
---|
1299 | |
---|
1300 | /* SW Reset the PHY so all changes take effect */ |
---|
1301 | ret_val = em_phy_reset(hw); |
---|
1302 | if(ret_val) { |
---|
1303 | DEBUGOUT("Error Resetting the PHY\n"); |
---|
1304 | return ret_val; |
---|
1305 | } |
---|
1306 | |
---|
1307 | return E1000_SUCCESS; |
---|
1308 | } |
---|
1309 | |
---|
1310 | /******************************************************************** |
---|
1311 | * Setup auto-negotiation and flow control advertisements, |
---|
1312 | * and then perform auto-negotiation. |
---|
1313 | * |
---|
1314 | * hw - Struct containing variables accessed by shared code |
---|
1315 | *********************************************************************/ |
---|
1316 | static int32_t |
---|
1317 | em_copper_link_autoneg(struct em_hw *hw) |
---|
1318 | { |
---|
1319 | int32_t ret_val; |
---|
1320 | uint16_t phy_data; |
---|
1321 | |
---|
1322 | DEBUGFUNC("em_copper_link_autoneg"); |
---|
1323 | |
---|
1324 | /* Perform some bounds checking on the hw->autoneg_advertised |
---|
1325 | * parameter. If this variable is zero, then set it to the default. |
---|
1326 | */ |
---|
1327 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
---|
1328 | |
---|
1329 | /* If autoneg_advertised is zero, we assume it was not defaulted |
---|
1330 | * by the calling code so we set to advertise full capability. |
---|
1331 | */ |
---|
1332 | if(hw->autoneg_advertised == 0) |
---|
1333 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
---|
1334 | |
---|
1335 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
---|
1336 | ret_val = em_phy_setup_autoneg(hw); |
---|
1337 | if(ret_val) { |
---|
1338 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
---|
1339 | return ret_val; |
---|
1340 | } |
---|
1341 | DEBUGOUT("Restarting Auto-Neg\n"); |
---|
1342 | |
---|
1343 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
---|
1344 | * the Auto Neg Restart bit in the PHY control register. |
---|
1345 | */ |
---|
1346 | ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); |
---|
1347 | if(ret_val) |
---|
1348 | return ret_val; |
---|
1349 | |
---|
1350 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
---|
1351 | ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); |
---|
1352 | if(ret_val) |
---|
1353 | return ret_val; |
---|
1354 | |
---|
1355 | /* Does the user want to wait for Auto-Neg to complete here, or |
---|
1356 | * check at a later time (for example, callback routine). |
---|
1357 | */ |
---|
1358 | if(hw->wait_autoneg_complete) { |
---|
1359 | ret_val = em_wait_autoneg(hw); |
---|
1360 | if(ret_val) { |
---|
1361 | DEBUGOUT("Error while waiting for autoneg to complete\n"); |
---|
1362 | return ret_val; |
---|
1363 | } |
---|
1364 | } |
---|
1365 | |
---|
1366 | hw->get_link_status = TRUE; |
---|
1367 | |
---|
1368 | return E1000_SUCCESS; |
---|
1369 | } |
---|
1370 | |
---|
1371 | |
---|
1372 | /****************************************************************************** |
---|
1373 | * Config the MAC and the PHY after link is up. |
---|
1374 | * 1) Set up the MAC to the current PHY speed/duplex |
---|
1375 | * if we are on 82543. If we |
---|
1376 | * are on newer silicon, we only need to configure |
---|
1377 | * collision distance in the Transmit Control Register. |
---|
1378 | * 2) Set up flow control on the MAC to that established with |
---|
1379 | * the link partner. |
---|
1380 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
---|
1381 | * |
---|
1382 | * hw - Struct containing variables accessed by shared code |
---|
1383 | ******************************************************************************/ |
---|
1384 | static int32_t |
---|
1385 | em_copper_link_postconfig(struct em_hw *hw) |
---|
1386 | { |
---|
1387 | int32_t ret_val; |
---|
1388 | DEBUGFUNC("em_copper_link_postconfig"); |
---|
1389 | |
---|
1390 | if(hw->mac_type >= em_82544) { |
---|
1391 | em_config_collision_dist(hw); |
---|
1392 | } else { |
---|
1393 | ret_val = em_config_mac_to_phy(hw); |
---|
1394 | if(ret_val) { |
---|
1395 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
---|
1396 | return ret_val; |
---|
1397 | } |
---|
1398 | } |
---|
1399 | ret_val = em_config_fc_after_link_up(hw); |
---|
1400 | if(ret_val) { |
---|
1401 | DEBUGOUT("Error Configuring Flow Control\n"); |
---|
1402 | return ret_val; |
---|
1403 | } |
---|
1404 | |
---|
1405 | /* Config DSP to improve Giga link quality */ |
---|
1406 | if(hw->phy_type == em_phy_igp) { |
---|
1407 | ret_val = em_config_dsp_after_link_change(hw, TRUE); |
---|
1408 | if(ret_val) { |
---|
1409 | DEBUGOUT("Error Configuring DSP after link up\n"); |
---|
1410 | return ret_val; |
---|
1411 | } |
---|
1412 | } |
---|
1413 | |
---|
1414 | return E1000_SUCCESS; |
---|
1415 | } |
---|
1416 | |
---|
1417 | /****************************************************************************** |
---|
1418 | * Detects which PHY is present and setup the speed and duplex |
---|
1419 | * |
---|
1420 | * hw - Struct containing variables accessed by shared code |
---|
1421 | ******************************************************************************/ |
---|
1422 | static int32_t |
---|
1423 | em_setup_copper_link(struct em_hw *hw) |
---|
1424 | { |
---|
1425 | int32_t ret_val; |
---|
1426 | uint16_t i; |
---|
1427 | uint16_t phy_data; |
---|
1428 | |
---|
1429 | DEBUGFUNC("em_setup_copper_link"); |
---|
1430 | |
---|
1431 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
---|
1432 | ret_val = em_copper_link_preconfig(hw); |
---|
1433 | if(ret_val) |
---|
1434 | return ret_val; |
---|
1435 | |
---|
1436 | if (hw->phy_type == em_phy_igp || |
---|
1437 | hw->phy_type == em_phy_igp_2) { |
---|
1438 | ret_val = em_copper_link_igp_setup(hw); |
---|
1439 | if(ret_val) |
---|
1440 | return ret_val; |
---|
1441 | } else if (hw->phy_type == em_phy_m88) { |
---|
1442 | ret_val = em_copper_link_mgp_setup(hw); |
---|
1443 | if(ret_val) |
---|
1444 | return ret_val; |
---|
1445 | } |
---|
1446 | |
---|
1447 | if(hw->autoneg) { |
---|
1448 | /* Setup autoneg and flow control advertisement |
---|
1449 | * and perform autonegotiation */ |
---|
1450 | ret_val = em_copper_link_autoneg(hw); |
---|
1451 | if(ret_val) |
---|
1452 | return ret_val; |
---|
1453 | } else { |
---|
1454 | /* PHY will be set to 10H, 10F, 100H,or 100F |
---|
1455 | * depending on value from forced_speed_duplex. */ |
---|
1456 | DEBUGOUT("Forcing speed and duplex\n"); |
---|
1457 | ret_val = em_phy_force_speed_duplex(hw); |
---|
1458 | if(ret_val) { |
---|
1459 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
---|
1460 | return ret_val; |
---|
1461 | } |
---|
1462 | } |
---|
1463 | |
---|
1464 | /* Check link status. Wait up to 100 microseconds for link to become |
---|
1465 | * valid. |
---|
1466 | */ |
---|
1467 | for(i = 0; i < 10; i++) { |
---|
1468 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
1469 | if(ret_val) |
---|
1470 | return ret_val; |
---|
1471 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
1472 | if(ret_val) |
---|
1473 | return ret_val; |
---|
1474 | |
---|
1475 | if(phy_data & MII_SR_LINK_STATUS) { |
---|
1476 | /* Config the MAC and PHY after link is up */ |
---|
1477 | ret_val = em_copper_link_postconfig(hw); |
---|
1478 | if(ret_val) |
---|
1479 | return ret_val; |
---|
1480 | |
---|
1481 | DEBUGOUT("Valid link established!!!\n"); |
---|
1482 | return E1000_SUCCESS; |
---|
1483 | } |
---|
1484 | usec_delay(10); |
---|
1485 | } |
---|
1486 | |
---|
1487 | DEBUGOUT("Unable to establish link!!!\n"); |
---|
1488 | return E1000_SUCCESS; |
---|
1489 | } |
---|
1490 | |
---|
1491 | /****************************************************************************** |
---|
1492 | * Configures PHY autoneg and flow control advertisement settings |
---|
1493 | * |
---|
1494 | * hw - Struct containing variables accessed by shared code |
---|
1495 | ******************************************************************************/ |
---|
1496 | int32_t |
---|
1497 | em_phy_setup_autoneg(struct em_hw *hw) |
---|
1498 | { |
---|
1499 | int32_t ret_val; |
---|
1500 | uint16_t mii_autoneg_adv_reg; |
---|
1501 | uint16_t mii_1000t_ctrl_reg; |
---|
1502 | |
---|
1503 | DEBUGFUNC("em_phy_setup_autoneg"); |
---|
1504 | |
---|
1505 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
---|
1506 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
---|
1507 | if(ret_val) |
---|
1508 | return ret_val; |
---|
1509 | |
---|
1510 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
---|
1511 | ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
---|
1512 | if(ret_val) |
---|
1513 | return ret_val; |
---|
1514 | |
---|
1515 | /* Need to parse both autoneg_advertised and fc and set up |
---|
1516 | * the appropriate PHY registers. First we will parse for |
---|
1517 | * autoneg_advertised software override. Since we can advertise |
---|
1518 | * a plethora of combinations, we need to check each bit |
---|
1519 | * individually. |
---|
1520 | */ |
---|
1521 | |
---|
1522 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
---|
1523 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
---|
1524 | * the 1000Base-T Control Register (Address 9). |
---|
1525 | */ |
---|
1526 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
---|
1527 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
---|
1528 | |
---|
1529 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
---|
1530 | |
---|
1531 | /* Do we want to advertise 10 Mb Half Duplex? */ |
---|
1532 | if(hw->autoneg_advertised & ADVERTISE_10_HALF) { |
---|
1533 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
---|
1534 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
---|
1535 | } |
---|
1536 | |
---|
1537 | /* Do we want to advertise 10 Mb Full Duplex? */ |
---|
1538 | if(hw->autoneg_advertised & ADVERTISE_10_FULL) { |
---|
1539 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
---|
1540 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
---|
1541 | } |
---|
1542 | |
---|
1543 | /* Do we want to advertise 100 Mb Half Duplex? */ |
---|
1544 | if(hw->autoneg_advertised & ADVERTISE_100_HALF) { |
---|
1545 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
---|
1546 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
---|
1547 | } |
---|
1548 | |
---|
1549 | /* Do we want to advertise 100 Mb Full Duplex? */ |
---|
1550 | if(hw->autoneg_advertised & ADVERTISE_100_FULL) { |
---|
1551 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
---|
1552 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
---|
1553 | } |
---|
1554 | |
---|
1555 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
---|
1556 | if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
---|
1557 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
---|
1558 | } |
---|
1559 | |
---|
1560 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
---|
1561 | if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
---|
1562 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
---|
1563 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
---|
1564 | } |
---|
1565 | |
---|
1566 | /* Check for a software override of the flow control settings, and |
---|
1567 | * setup the PHY advertisement registers accordingly. If |
---|
1568 | * auto-negotiation is enabled, then software will have to set the |
---|
1569 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
---|
1570 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
---|
1571 | * |
---|
1572 | * The possible values of the "fc" parameter are: |
---|
1573 | * 0: Flow control is completely disabled |
---|
1574 | * 1: Rx flow control is enabled (we can receive pause frames |
---|
1575 | * but not send pause frames). |
---|
1576 | * 2: Tx flow control is enabled (we can send pause frames |
---|
1577 | * but we do not support receiving pause frames). |
---|
1578 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
---|
1579 | * other: No software override. The flow control configuration |
---|
1580 | * in the EEPROM is used. |
---|
1581 | */ |
---|
1582 | switch (hw->fc) { |
---|
1583 | case em_fc_none: /* 0 */ |
---|
1584 | /* Flow control (RX & TX) is completely disabled by a |
---|
1585 | * software over-ride. |
---|
1586 | */ |
---|
1587 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
---|
1588 | break; |
---|
1589 | case em_fc_rx_pause: /* 1 */ |
---|
1590 | /* RX Flow control is enabled, and TX Flow control is |
---|
1591 | * disabled, by a software over-ride. |
---|
1592 | */ |
---|
1593 | /* Since there really isn't a way to advertise that we are |
---|
1594 | * capable of RX Pause ONLY, we will advertise that we |
---|
1595 | * support both symmetric and asymmetric RX PAUSE. Later |
---|
1596 | * (in em_config_fc_after_link_up) we will disable the |
---|
1597 | *hw's ability to send PAUSE frames. |
---|
1598 | */ |
---|
1599 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
---|
1600 | break; |
---|
1601 | case em_fc_tx_pause: /* 2 */ |
---|
1602 | /* TX Flow control is enabled, and RX Flow control is |
---|
1603 | * disabled, by a software over-ride. |
---|
1604 | */ |
---|
1605 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
---|
1606 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
---|
1607 | break; |
---|
1608 | case em_fc_full: /* 3 */ |
---|
1609 | /* Flow control (both RX and TX) is enabled by a software |
---|
1610 | * over-ride. |
---|
1611 | */ |
---|
1612 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
---|
1613 | break; |
---|
1614 | default: |
---|
1615 | DEBUGOUT("Flow control param set incorrectly\n"); |
---|
1616 | return -E1000_ERR_CONFIG; |
---|
1617 | } |
---|
1618 | |
---|
1619 | ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
---|
1620 | if(ret_val) |
---|
1621 | return ret_val; |
---|
1622 | |
---|
1623 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
---|
1624 | |
---|
1625 | ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
---|
1626 | if(ret_val) |
---|
1627 | return ret_val; |
---|
1628 | |
---|
1629 | return E1000_SUCCESS; |
---|
1630 | } |
---|
1631 | |
---|
1632 | /****************************************************************************** |
---|
1633 | * Force PHY speed and duplex settings to hw->forced_speed_duplex |
---|
1634 | * |
---|
1635 | * hw - Struct containing variables accessed by shared code |
---|
1636 | ******************************************************************************/ |
---|
1637 | static int32_t |
---|
1638 | em_phy_force_speed_duplex(struct em_hw *hw) |
---|
1639 | { |
---|
1640 | uint32_t ctrl; |
---|
1641 | int32_t ret_val; |
---|
1642 | uint16_t mii_ctrl_reg; |
---|
1643 | uint16_t mii_status_reg; |
---|
1644 | uint16_t phy_data; |
---|
1645 | uint16_t i; |
---|
1646 | |
---|
1647 | DEBUGFUNC("em_phy_force_speed_duplex"); |
---|
1648 | |
---|
1649 | /* Turn off Flow control if we are forcing speed and duplex. */ |
---|
1650 | hw->fc = em_fc_none; |
---|
1651 | |
---|
1652 | DEBUGOUT1("hw->fc = %d\n", hw->fc); |
---|
1653 | |
---|
1654 | /* Read the Device Control Register. */ |
---|
1655 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
1656 | |
---|
1657 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
---|
1658 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
---|
1659 | ctrl &= ~(DEVICE_SPEED_MASK); |
---|
1660 | |
---|
1661 | /* Clear the Auto Speed Detect Enable bit. */ |
---|
1662 | ctrl &= ~E1000_CTRL_ASDE; |
---|
1663 | |
---|
1664 | /* Read the MII Control Register. */ |
---|
1665 | ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
---|
1666 | if(ret_val) |
---|
1667 | return ret_val; |
---|
1668 | |
---|
1669 | /* We need to disable autoneg in order to force link and duplex. */ |
---|
1670 | |
---|
1671 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
---|
1672 | |
---|
1673 | /* Are we forcing Full or Half Duplex? */ |
---|
1674 | if(hw->forced_speed_duplex == em_100_full || |
---|
1675 | hw->forced_speed_duplex == em_10_full) { |
---|
1676 | /* We want to force full duplex so we SET the full duplex bits in the |
---|
1677 | * Device and MII Control Registers. |
---|
1678 | */ |
---|
1679 | ctrl |= E1000_CTRL_FD; |
---|
1680 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
---|
1681 | DEBUGOUT("Full Duplex\n"); |
---|
1682 | } else { |
---|
1683 | /* We want to force half duplex so we CLEAR the full duplex bits in |
---|
1684 | * the Device and MII Control Registers. |
---|
1685 | */ |
---|
1686 | ctrl &= ~E1000_CTRL_FD; |
---|
1687 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
---|
1688 | DEBUGOUT("Half Duplex\n"); |
---|
1689 | } |
---|
1690 | |
---|
1691 | /* Are we forcing 100Mbps??? */ |
---|
1692 | if(hw->forced_speed_duplex == em_100_full || |
---|
1693 | hw->forced_speed_duplex == em_100_half) { |
---|
1694 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
---|
1695 | ctrl |= E1000_CTRL_SPD_100; |
---|
1696 | mii_ctrl_reg |= MII_CR_SPEED_100; |
---|
1697 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
---|
1698 | DEBUGOUT("Forcing 100mb "); |
---|
1699 | } else { |
---|
1700 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
---|
1701 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
---|
1702 | mii_ctrl_reg |= MII_CR_SPEED_10; |
---|
1703 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
---|
1704 | DEBUGOUT("Forcing 10mb "); |
---|
1705 | } |
---|
1706 | |
---|
1707 | em_config_collision_dist(hw); |
---|
1708 | |
---|
1709 | /* Write the configured values back to the Device Control Reg. */ |
---|
1710 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
1711 | |
---|
1712 | if (hw->phy_type == em_phy_m88) { |
---|
1713 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
---|
1714 | if(ret_val) |
---|
1715 | return ret_val; |
---|
1716 | |
---|
1717 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
---|
1718 | * forced whenever speed are duplex are forced. |
---|
1719 | */ |
---|
1720 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
---|
1721 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
---|
1722 | if(ret_val) |
---|
1723 | return ret_val; |
---|
1724 | |
---|
1725 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
---|
1726 | |
---|
1727 | /* Need to reset the PHY or these changes will be ignored */ |
---|
1728 | mii_ctrl_reg |= MII_CR_RESET; |
---|
1729 | } else { |
---|
1730 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
---|
1731 | * forced whenever speed or duplex are forced. |
---|
1732 | */ |
---|
1733 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
---|
1734 | if(ret_val) |
---|
1735 | return ret_val; |
---|
1736 | |
---|
1737 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
---|
1738 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
---|
1739 | |
---|
1740 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
---|
1741 | if(ret_val) |
---|
1742 | return ret_val; |
---|
1743 | } |
---|
1744 | |
---|
1745 | /* Write back the modified PHY MII control register. */ |
---|
1746 | ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
---|
1747 | if(ret_val) |
---|
1748 | return ret_val; |
---|
1749 | |
---|
1750 | usec_delay(1); |
---|
1751 | |
---|
1752 | /* The wait_autoneg_complete flag may be a little misleading here. |
---|
1753 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
---|
1754 | * But we do want to delay for a period while forcing only so we |
---|
1755 | * don't generate false No Link messages. So we will wait here |
---|
1756 | * only if the user has set wait_autoneg_complete to 1, which is |
---|
1757 | * the default. |
---|
1758 | */ |
---|
1759 | if(hw->wait_autoneg_complete) { |
---|
1760 | /* We will wait for autoneg to complete. */ |
---|
1761 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
---|
1762 | mii_status_reg = 0; |
---|
1763 | |
---|
1764 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
---|
1765 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
---|
1766 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
---|
1767 | * to be set. |
---|
1768 | */ |
---|
1769 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
1770 | if(ret_val) |
---|
1771 | return ret_val; |
---|
1772 | |
---|
1773 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
1774 | if(ret_val) |
---|
1775 | return ret_val; |
---|
1776 | |
---|
1777 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
---|
1778 | msec_delay(100); |
---|
1779 | } |
---|
1780 | if((i == 0) && |
---|
1781 | (hw->phy_type == em_phy_m88)) { |
---|
1782 | /* We didn't get link. Reset the DSP and wait again for link. */ |
---|
1783 | ret_val = em_phy_reset_dsp(hw); |
---|
1784 | if(ret_val) { |
---|
1785 | DEBUGOUT("Error Resetting PHY DSP\n"); |
---|
1786 | return ret_val; |
---|
1787 | } |
---|
1788 | } |
---|
1789 | /* This loop will early-out if the link condition has been met. */ |
---|
1790 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
---|
1791 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
---|
1792 | msec_delay(100); |
---|
1793 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
---|
1794 | * to be set. |
---|
1795 | */ |
---|
1796 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
1797 | if(ret_val) |
---|
1798 | return ret_val; |
---|
1799 | |
---|
1800 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
1801 | if(ret_val) |
---|
1802 | return ret_val; |
---|
1803 | } |
---|
1804 | } |
---|
1805 | |
---|
1806 | if (hw->phy_type == em_phy_m88) { |
---|
1807 | /* Because we reset the PHY above, we need to re-force TX_CLK in the |
---|
1808 | * Extended PHY Specific Control Register to 25MHz clock. This value |
---|
1809 | * defaults back to a 2.5MHz clock when the PHY is reset. |
---|
1810 | */ |
---|
1811 | ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
---|
1812 | if(ret_val) |
---|
1813 | return ret_val; |
---|
1814 | |
---|
1815 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
---|
1816 | ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
---|
1817 | if(ret_val) |
---|
1818 | return ret_val; |
---|
1819 | |
---|
1820 | /* In addition, because of the s/w reset above, we need to enable CRS on |
---|
1821 | * TX. This must be set for both full and half duplex operation. |
---|
1822 | */ |
---|
1823 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
---|
1824 | if(ret_val) |
---|
1825 | return ret_val; |
---|
1826 | |
---|
1827 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
---|
1828 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
---|
1829 | if(ret_val) |
---|
1830 | return ret_val; |
---|
1831 | |
---|
1832 | if((hw->mac_type == em_82544 || hw->mac_type == em_82543) && |
---|
1833 | (!hw->autoneg) && |
---|
1834 | (hw->forced_speed_duplex == em_10_full || |
---|
1835 | hw->forced_speed_duplex == em_10_half)) { |
---|
1836 | ret_val = em_polarity_reversal_workaround(hw); |
---|
1837 | if(ret_val) |
---|
1838 | return ret_val; |
---|
1839 | } |
---|
1840 | } |
---|
1841 | return E1000_SUCCESS; |
---|
1842 | } |
---|
1843 | |
---|
1844 | /****************************************************************************** |
---|
1845 | * Sets the collision distance in the Transmit Control register |
---|
1846 | * |
---|
1847 | * hw - Struct containing variables accessed by shared code |
---|
1848 | * |
---|
1849 | * Link should have been established previously. Reads the speed and duplex |
---|
1850 | * information from the Device Status register. |
---|
1851 | ******************************************************************************/ |
---|
1852 | void |
---|
1853 | em_config_collision_dist(struct em_hw *hw) |
---|
1854 | { |
---|
1855 | uint32_t tctl; |
---|
1856 | |
---|
1857 | DEBUGFUNC("em_config_collision_dist"); |
---|
1858 | |
---|
1859 | tctl = E1000_READ_REG(hw, TCTL); |
---|
1860 | |
---|
1861 | tctl &= ~E1000_TCTL_COLD; |
---|
1862 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
---|
1863 | |
---|
1864 | E1000_WRITE_REG(hw, TCTL, tctl); |
---|
1865 | E1000_WRITE_FLUSH(hw); |
---|
1866 | } |
---|
1867 | |
---|
1868 | /****************************************************************************** |
---|
1869 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
---|
1870 | * |
---|
1871 | * hw - Struct containing variables accessed by shared code |
---|
1872 | * mii_reg - data to write to the MII control register |
---|
1873 | * |
---|
1874 | * The contents of the PHY register containing the needed information need to |
---|
1875 | * be passed in. |
---|
1876 | ******************************************************************************/ |
---|
1877 | static int32_t |
---|
1878 | em_config_mac_to_phy(struct em_hw *hw) |
---|
1879 | { |
---|
1880 | uint32_t ctrl; |
---|
1881 | int32_t ret_val; |
---|
1882 | uint16_t phy_data; |
---|
1883 | |
---|
1884 | DEBUGFUNC("em_config_mac_to_phy"); |
---|
1885 | |
---|
1886 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
---|
1887 | * MAC speed/duplex configuration.*/ |
---|
1888 | if (hw->mac_type >= em_82544) |
---|
1889 | return E1000_SUCCESS; |
---|
1890 | |
---|
1891 | /* Read the Device Control Register and set the bits to Force Speed |
---|
1892 | * and Duplex. |
---|
1893 | */ |
---|
1894 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
1895 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
---|
1896 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
---|
1897 | |
---|
1898 | /* Set up duplex in the Device Control and Transmit Control |
---|
1899 | * registers depending on negotiated values. |
---|
1900 | */ |
---|
1901 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
---|
1902 | if(ret_val) |
---|
1903 | return ret_val; |
---|
1904 | |
---|
1905 | if(phy_data & M88E1000_PSSR_DPLX) |
---|
1906 | ctrl |= E1000_CTRL_FD; |
---|
1907 | else |
---|
1908 | ctrl &= ~E1000_CTRL_FD; |
---|
1909 | |
---|
1910 | em_config_collision_dist(hw); |
---|
1911 | |
---|
1912 | /* Set up speed in the Device Control register depending on |
---|
1913 | * negotiated values. |
---|
1914 | */ |
---|
1915 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
---|
1916 | ctrl |= E1000_CTRL_SPD_1000; |
---|
1917 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
---|
1918 | ctrl |= E1000_CTRL_SPD_100; |
---|
1919 | |
---|
1920 | /* Write the configured values back to the Device Control Reg. */ |
---|
1921 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
1922 | return E1000_SUCCESS; |
---|
1923 | } |
---|
1924 | |
---|
1925 | /****************************************************************************** |
---|
1926 | * Forces the MAC's flow control settings. |
---|
1927 | * |
---|
1928 | * hw - Struct containing variables accessed by shared code |
---|
1929 | * |
---|
1930 | * Sets the TFCE and RFCE bits in the device control register to reflect |
---|
1931 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
---|
1932 | * software when a Copper PHY is used because autonegotiation is managed |
---|
1933 | * by the PHY rather than the MAC. Software must also configure these |
---|
1934 | * bits when link is forced on a fiber connection. |
---|
1935 | *****************************************************************************/ |
---|
1936 | int32_t |
---|
1937 | em_force_mac_fc(struct em_hw *hw) |
---|
1938 | { |
---|
1939 | uint32_t ctrl; |
---|
1940 | |
---|
1941 | DEBUGFUNC("em_force_mac_fc"); |
---|
1942 | |
---|
1943 | /* Get the current configuration of the Device Control Register */ |
---|
1944 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
1945 | |
---|
1946 | /* Because we didn't get link via the internal auto-negotiation |
---|
1947 | * mechanism (we either forced link or we got link via PHY |
---|
1948 | * auto-neg), we have to manually enable/disable transmit an |
---|
1949 | * receive flow control. |
---|
1950 | * |
---|
1951 | * The "Case" statement below enables/disable flow control |
---|
1952 | * according to the "hw->fc" parameter. |
---|
1953 | * |
---|
1954 | * The possible values of the "fc" parameter are: |
---|
1955 | * 0: Flow control is completely disabled |
---|
1956 | * 1: Rx flow control is enabled (we can receive pause |
---|
1957 | * frames but not send pause frames). |
---|
1958 | * 2: Tx flow control is enabled (we can send pause frames |
---|
1959 | * frames but we do not receive pause frames). |
---|
1960 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
---|
1961 | * other: No other values should be possible at this point. |
---|
1962 | */ |
---|
1963 | |
---|
1964 | switch (hw->fc) { |
---|
1965 | case em_fc_none: |
---|
1966 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
---|
1967 | break; |
---|
1968 | case em_fc_rx_pause: |
---|
1969 | ctrl &= (~E1000_CTRL_TFCE); |
---|
1970 | ctrl |= E1000_CTRL_RFCE; |
---|
1971 | break; |
---|
1972 | case em_fc_tx_pause: |
---|
1973 | ctrl &= (~E1000_CTRL_RFCE); |
---|
1974 | ctrl |= E1000_CTRL_TFCE; |
---|
1975 | break; |
---|
1976 | case em_fc_full: |
---|
1977 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
---|
1978 | break; |
---|
1979 | default: |
---|
1980 | DEBUGOUT("Flow control param set incorrectly\n"); |
---|
1981 | return -E1000_ERR_CONFIG; |
---|
1982 | } |
---|
1983 | |
---|
1984 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
---|
1985 | if(hw->mac_type == em_82542_rev2_0) |
---|
1986 | ctrl &= (~E1000_CTRL_TFCE); |
---|
1987 | |
---|
1988 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
1989 | return E1000_SUCCESS; |
---|
1990 | } |
---|
1991 | |
---|
1992 | /****************************************************************************** |
---|
1993 | * Configures flow control settings after link is established |
---|
1994 | * |
---|
1995 | * hw - Struct containing variables accessed by shared code |
---|
1996 | * |
---|
1997 | * Should be called immediately after a valid link has been established. |
---|
1998 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
---|
1999 | * and autonegotiation is enabled, the MAC flow control settings will be set |
---|
2000 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
---|
2001 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
---|
2002 | *****************************************************************************/ |
---|
2003 | int32_t |
---|
2004 | em_config_fc_after_link_up(struct em_hw *hw) |
---|
2005 | { |
---|
2006 | int32_t ret_val; |
---|
2007 | uint16_t mii_status_reg; |
---|
2008 | uint16_t mii_nway_adv_reg; |
---|
2009 | uint16_t mii_nway_lp_ability_reg; |
---|
2010 | uint16_t speed; |
---|
2011 | uint16_t duplex; |
---|
2012 | |
---|
2013 | DEBUGFUNC("em_config_fc_after_link_up"); |
---|
2014 | |
---|
2015 | /* Check for the case where we have fiber media and auto-neg failed |
---|
2016 | * so we had to force link. In this case, we need to force the |
---|
2017 | * configuration of the MAC to match the "fc" parameter. |
---|
2018 | */ |
---|
2019 | if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) || |
---|
2020 | ((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) || |
---|
2021 | ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) { |
---|
2022 | ret_val = em_force_mac_fc(hw); |
---|
2023 | if(ret_val) { |
---|
2024 | DEBUGOUT("Error forcing flow control settings\n"); |
---|
2025 | return ret_val; |
---|
2026 | } |
---|
2027 | } |
---|
2028 | |
---|
2029 | /* Check for the case where we have copper media and auto-neg is |
---|
2030 | * enabled. In this case, we need to check and see if Auto-Neg |
---|
2031 | * has completed, and if so, how the PHY and link partner has |
---|
2032 | * flow control configured. |
---|
2033 | */ |
---|
2034 | if((hw->media_type == em_media_type_copper) && hw->autoneg) { |
---|
2035 | /* Read the MII Status Register and check to see if AutoNeg |
---|
2036 | * has completed. We read this twice because this reg has |
---|
2037 | * some "sticky" (latched) bits. |
---|
2038 | */ |
---|
2039 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
2040 | if(ret_val) |
---|
2041 | return ret_val; |
---|
2042 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
2043 | if(ret_val) |
---|
2044 | return ret_val; |
---|
2045 | |
---|
2046 | if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
---|
2047 | /* The AutoNeg process has completed, so we now need to |
---|
2048 | * read both the Auto Negotiation Advertisement Register |
---|
2049 | * (Address 4) and the Auto_Negotiation Base Page Ability |
---|
2050 | * Register (Address 5) to determine how flow control was |
---|
2051 | * negotiated. |
---|
2052 | */ |
---|
2053 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, |
---|
2054 | &mii_nway_adv_reg); |
---|
2055 | if(ret_val) |
---|
2056 | return ret_val; |
---|
2057 | ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, |
---|
2058 | &mii_nway_lp_ability_reg); |
---|
2059 | if(ret_val) |
---|
2060 | return ret_val; |
---|
2061 | |
---|
2062 | /* Two bits in the Auto Negotiation Advertisement Register |
---|
2063 | * (Address 4) and two bits in the Auto Negotiation Base |
---|
2064 | * Page Ability Register (Address 5) determine flow control |
---|
2065 | * for both the PHY and the link partner. The following |
---|
2066 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
---|
2067 | * 1999, describes these PAUSE resolution bits and how flow |
---|
2068 | * control is determined based upon these settings. |
---|
2069 | * NOTE: DC = Don't Care |
---|
2070 | * |
---|
2071 | * LOCAL DEVICE | LINK PARTNER |
---|
2072 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
---|
2073 | *-------|---------|-------|---------|-------------------- |
---|
2074 | * 0 | 0 | DC | DC | em_fc_none |
---|
2075 | * 0 | 1 | 0 | DC | em_fc_none |
---|
2076 | * 0 | 1 | 1 | 0 | em_fc_none |
---|
2077 | * 0 | 1 | 1 | 1 | em_fc_tx_pause |
---|
2078 | * 1 | 0 | 0 | DC | em_fc_none |
---|
2079 | * 1 | DC | 1 | DC | em_fc_full |
---|
2080 | * 1 | 1 | 0 | 0 | em_fc_none |
---|
2081 | * 1 | 1 | 0 | 1 | em_fc_rx_pause |
---|
2082 | * |
---|
2083 | */ |
---|
2084 | /* Are both PAUSE bits set to 1? If so, this implies |
---|
2085 | * Symmetric Flow Control is enabled at both ends. The |
---|
2086 | * ASM_DIR bits are irrelevant per the spec. |
---|
2087 | * |
---|
2088 | * For Symmetric Flow Control: |
---|
2089 | * |
---|
2090 | * LOCAL DEVICE | LINK PARTNER |
---|
2091 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
---|
2092 | *-------|---------|-------|---------|-------------------- |
---|
2093 | * 1 | DC | 1 | DC | em_fc_full |
---|
2094 | * |
---|
2095 | */ |
---|
2096 | if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
---|
2097 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
---|
2098 | /* Now we need to check if the user selected RX ONLY |
---|
2099 | * of pause frames. In this case, we had to advertise |
---|
2100 | * FULL flow control because we could not advertise RX |
---|
2101 | * ONLY. Hence, we must now check to see if we need to |
---|
2102 | * turn OFF the TRANSMISSION of PAUSE frames. |
---|
2103 | */ |
---|
2104 | if(hw->original_fc == em_fc_full) { |
---|
2105 | hw->fc = em_fc_full; |
---|
2106 | DEBUGOUT("Flow Control = FULL.\r\n"); |
---|
2107 | } else { |
---|
2108 | hw->fc = em_fc_rx_pause; |
---|
2109 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
---|
2110 | } |
---|
2111 | } |
---|
2112 | /* For receiving PAUSE frames ONLY. |
---|
2113 | * |
---|
2114 | * LOCAL DEVICE | LINK PARTNER |
---|
2115 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
---|
2116 | *-------|---------|-------|---------|-------------------- |
---|
2117 | * 0 | 1 | 1 | 1 | em_fc_tx_pause |
---|
2118 | * |
---|
2119 | */ |
---|
2120 | else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
---|
2121 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
---|
2122 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
---|
2123 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
---|
2124 | hw->fc = em_fc_tx_pause; |
---|
2125 | DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); |
---|
2126 | } |
---|
2127 | /* For transmitting PAUSE frames ONLY. |
---|
2128 | * |
---|
2129 | * LOCAL DEVICE | LINK PARTNER |
---|
2130 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
---|
2131 | *-------|---------|-------|---------|-------------------- |
---|
2132 | * 1 | 1 | 0 | 1 | em_fc_rx_pause |
---|
2133 | * |
---|
2134 | */ |
---|
2135 | else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
---|
2136 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
---|
2137 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
---|
2138 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
---|
2139 | hw->fc = em_fc_rx_pause; |
---|
2140 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
---|
2141 | } |
---|
2142 | /* Per the IEEE spec, at this point flow control should be |
---|
2143 | * disabled. However, we want to consider that we could |
---|
2144 | * be connected to a legacy switch that doesn't advertise |
---|
2145 | * desired flow control, but can be forced on the link |
---|
2146 | * partner. So if we advertised no flow control, that is |
---|
2147 | * what we will resolve to. If we advertised some kind of |
---|
2148 | * receive capability (Rx Pause Only or Full Flow Control) |
---|
2149 | * and the link partner advertised none, we will configure |
---|
2150 | * ourselves to enable Rx Flow Control only. We can do |
---|
2151 | * this safely for two reasons: If the link partner really |
---|
2152 | * didn't want flow control enabled, and we enable Rx, no |
---|
2153 | * harm done since we won't be receiving any PAUSE frames |
---|
2154 | * anyway. If the intent on the link partner was to have |
---|
2155 | * flow control enabled, then by us enabling RX only, we |
---|
2156 | * can at least receive pause frames and process them. |
---|
2157 | * This is a good idea because in most cases, since we are |
---|
2158 | * predominantly a server NIC, more times than not we will |
---|
2159 | * be asked to delay transmission of packets than asking |
---|
2160 | * our link partner to pause transmission of frames. |
---|
2161 | */ |
---|
2162 | else if((hw->original_fc == em_fc_none || |
---|
2163 | hw->original_fc == em_fc_tx_pause) || |
---|
2164 | hw->fc_strict_ieee) { |
---|
2165 | hw->fc = em_fc_none; |
---|
2166 | DEBUGOUT("Flow Control = NONE.\r\n"); |
---|
2167 | } else { |
---|
2168 | hw->fc = em_fc_rx_pause; |
---|
2169 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
---|
2170 | } |
---|
2171 | |
---|
2172 | /* Now we need to do one last check... If we auto- |
---|
2173 | * negotiated to HALF DUPLEX, flow control should not be |
---|
2174 | * enabled per IEEE 802.3 spec. |
---|
2175 | */ |
---|
2176 | ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); |
---|
2177 | if(ret_val) { |
---|
2178 | DEBUGOUT("Error getting link speed and duplex\n"); |
---|
2179 | return ret_val; |
---|
2180 | } |
---|
2181 | |
---|
2182 | if(duplex == HALF_DUPLEX) |
---|
2183 | hw->fc = em_fc_none; |
---|
2184 | |
---|
2185 | /* Now we call a subroutine to actually force the MAC |
---|
2186 | * controller to use the correct flow control settings. |
---|
2187 | */ |
---|
2188 | ret_val = em_force_mac_fc(hw); |
---|
2189 | if(ret_val) { |
---|
2190 | DEBUGOUT("Error forcing flow control settings\n"); |
---|
2191 | return ret_val; |
---|
2192 | } |
---|
2193 | } else { |
---|
2194 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); |
---|
2195 | } |
---|
2196 | } |
---|
2197 | return E1000_SUCCESS; |
---|
2198 | } |
---|
2199 | |
---|
2200 | /****************************************************************************** |
---|
2201 | * Checks to see if the link status of the hardware has changed. |
---|
2202 | * |
---|
2203 | * hw - Struct containing variables accessed by shared code |
---|
2204 | * |
---|
2205 | * Called by any function that needs to check the link status of the adapter. |
---|
2206 | *****************************************************************************/ |
---|
2207 | int32_t |
---|
2208 | em_check_for_link(struct em_hw *hw) |
---|
2209 | { |
---|
2210 | uint32_t rxcw = 0; |
---|
2211 | uint32_t ctrl; |
---|
2212 | uint32_t status; |
---|
2213 | uint32_t rctl; |
---|
2214 | uint32_t icr; |
---|
2215 | uint32_t signal = 0; |
---|
2216 | int32_t ret_val; |
---|
2217 | uint16_t phy_data; |
---|
2218 | |
---|
2219 | DEBUGFUNC("em_check_for_link"); |
---|
2220 | |
---|
2221 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2222 | status = E1000_READ_REG(hw, STATUS); |
---|
2223 | |
---|
2224 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
---|
2225 | * set when the optics detect a signal. On older adapters, it will be |
---|
2226 | * cleared when there is a signal. This applies to fiber media only. |
---|
2227 | */ |
---|
2228 | if((hw->media_type == em_media_type_fiber) || |
---|
2229 | (hw->media_type == em_media_type_internal_serdes)) { |
---|
2230 | rxcw = E1000_READ_REG(hw, RXCW); |
---|
2231 | |
---|
2232 | if(hw->media_type == em_media_type_fiber) { |
---|
2233 | signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; |
---|
2234 | if(status & E1000_STATUS_LU) |
---|
2235 | hw->get_link_status = FALSE; |
---|
2236 | } |
---|
2237 | } |
---|
2238 | |
---|
2239 | /* If we have a copper PHY then we only want to go out to the PHY |
---|
2240 | * registers to see if Auto-Neg has completed and/or if our link |
---|
2241 | * status has changed. The get_link_status flag will be set if we |
---|
2242 | * receive a Link Status Change interrupt or we have Rx Sequence |
---|
2243 | * Errors. |
---|
2244 | */ |
---|
2245 | if((hw->media_type == em_media_type_copper) && hw->get_link_status) { |
---|
2246 | /* First we want to see if the MII Status Register reports |
---|
2247 | * link. If so, then we want to get the current speed/duplex |
---|
2248 | * of the PHY. |
---|
2249 | * Read the register twice since the link bit is sticky. |
---|
2250 | */ |
---|
2251 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
2252 | if(ret_val) |
---|
2253 | return ret_val; |
---|
2254 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
2255 | if(ret_val) |
---|
2256 | return ret_val; |
---|
2257 | |
---|
2258 | if(phy_data & MII_SR_LINK_STATUS) { |
---|
2259 | hw->get_link_status = FALSE; |
---|
2260 | /* Check if there was DownShift, must be checked immediately after |
---|
2261 | * link-up */ |
---|
2262 | em_check_downshift(hw); |
---|
2263 | |
---|
2264 | /* If we are on 82544 or 82543 silicon and speed/duplex |
---|
2265 | * are forced to 10H or 10F, then we will implement the polarity |
---|
2266 | * reversal workaround. We disable interrupts first, and upon |
---|
2267 | * returning, place the devices interrupt state to its previous |
---|
2268 | * value except for the link status change interrupt which will |
---|
2269 | * happen due to the execution of this workaround. |
---|
2270 | */ |
---|
2271 | |
---|
2272 | if((hw->mac_type == em_82544 || hw->mac_type == em_82543) && |
---|
2273 | (!hw->autoneg) && |
---|
2274 | (hw->forced_speed_duplex == em_10_full || |
---|
2275 | hw->forced_speed_duplex == em_10_half)) { |
---|
2276 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
---|
2277 | ret_val = em_polarity_reversal_workaround(hw); |
---|
2278 | icr = E1000_READ_REG(hw, ICR); |
---|
2279 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); |
---|
2280 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); |
---|
2281 | } |
---|
2282 | |
---|
2283 | } else { |
---|
2284 | /* No link detected */ |
---|
2285 | em_config_dsp_after_link_change(hw, FALSE); |
---|
2286 | return 0; |
---|
2287 | } |
---|
2288 | |
---|
2289 | /* If we are forcing speed/duplex, then we simply return since |
---|
2290 | * we have already determined whether we have link or not. |
---|
2291 | */ |
---|
2292 | if(!hw->autoneg) return -E1000_ERR_CONFIG; |
---|
2293 | |
---|
2294 | /* optimize the dsp settings for the igp phy */ |
---|
2295 | em_config_dsp_after_link_change(hw, TRUE); |
---|
2296 | |
---|
2297 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
---|
2298 | * have Si on board that is 82544 or newer, Auto |
---|
2299 | * Speed Detection takes care of MAC speed/duplex |
---|
2300 | * configuration. So we only need to configure Collision |
---|
2301 | * Distance in the MAC. Otherwise, we need to force |
---|
2302 | * speed/duplex on the MAC to the current PHY speed/duplex |
---|
2303 | * settings. |
---|
2304 | */ |
---|
2305 | if(hw->mac_type >= em_82544) |
---|
2306 | em_config_collision_dist(hw); |
---|
2307 | else { |
---|
2308 | ret_val = em_config_mac_to_phy(hw); |
---|
2309 | if(ret_val) { |
---|
2310 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
---|
2311 | return ret_val; |
---|
2312 | } |
---|
2313 | } |
---|
2314 | |
---|
2315 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
---|
2316 | * need to restore the desired flow control settings because we may |
---|
2317 | * have had to re-autoneg with a different link partner. |
---|
2318 | */ |
---|
2319 | ret_val = em_config_fc_after_link_up(hw); |
---|
2320 | if(ret_val) { |
---|
2321 | DEBUGOUT("Error configuring flow control\n"); |
---|
2322 | return ret_val; |
---|
2323 | } |
---|
2324 | |
---|
2325 | /* At this point we know that we are on copper and we have |
---|
2326 | * auto-negotiated link. These are conditions for checking the link |
---|
2327 | * partner capability register. We use the link speed to determine if |
---|
2328 | * TBI compatibility needs to be turned on or off. If the link is not |
---|
2329 | * at gigabit speed, then TBI compatibility is not needed. If we are |
---|
2330 | * at gigabit speed, we turn on TBI compatibility. |
---|
2331 | */ |
---|
2332 | if(hw->tbi_compatibility_en) { |
---|
2333 | uint16_t speed, duplex; |
---|
2334 | em_get_speed_and_duplex(hw, &speed, &duplex); |
---|
2335 | if(speed != SPEED_1000) { |
---|
2336 | /* If link speed is not set to gigabit speed, we do not need |
---|
2337 | * to enable TBI compatibility. |
---|
2338 | */ |
---|
2339 | if(hw->tbi_compatibility_on) { |
---|
2340 | /* If we previously were in the mode, turn it off. */ |
---|
2341 | rctl = E1000_READ_REG(hw, RCTL); |
---|
2342 | rctl &= ~E1000_RCTL_SBP; |
---|
2343 | E1000_WRITE_REG(hw, RCTL, rctl); |
---|
2344 | hw->tbi_compatibility_on = FALSE; |
---|
2345 | } |
---|
2346 | } else { |
---|
2347 | /* If TBI compatibility is was previously off, turn it on. For |
---|
2348 | * compatibility with a TBI link partner, we will store bad |
---|
2349 | * packets. Some frames have an additional byte on the end and |
---|
2350 | * will look like CRC errors to to the hardware. |
---|
2351 | */ |
---|
2352 | if(!hw->tbi_compatibility_on) { |
---|
2353 | hw->tbi_compatibility_on = TRUE; |
---|
2354 | rctl = E1000_READ_REG(hw, RCTL); |
---|
2355 | rctl |= E1000_RCTL_SBP; |
---|
2356 | E1000_WRITE_REG(hw, RCTL, rctl); |
---|
2357 | } |
---|
2358 | } |
---|
2359 | } |
---|
2360 | } |
---|
2361 | /* If we don't have link (auto-negotiation failed or link partner cannot |
---|
2362 | * auto-negotiate), the cable is plugged in (we have signal), and our |
---|
2363 | * link partner is not trying to auto-negotiate with us (we are receiving |
---|
2364 | * idles or data), we need to force link up. We also need to give |
---|
2365 | * auto-negotiation time to complete, in case the cable was just plugged |
---|
2366 | * in. The autoneg_failed flag does this. |
---|
2367 | */ |
---|
2368 | else if((((hw->media_type == em_media_type_fiber) && |
---|
2369 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
---|
2370 | (hw->media_type == em_media_type_internal_serdes)) && |
---|
2371 | (!(status & E1000_STATUS_LU)) && |
---|
2372 | (!(rxcw & E1000_RXCW_C))) { |
---|
2373 | if(hw->autoneg_failed == 0) { |
---|
2374 | hw->autoneg_failed = 1; |
---|
2375 | return 0; |
---|
2376 | } |
---|
2377 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); |
---|
2378 | |
---|
2379 | /* Disable auto-negotiation in the TXCW register */ |
---|
2380 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
---|
2381 | |
---|
2382 | /* Force link-up and also force full-duplex. */ |
---|
2383 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2384 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
---|
2385 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
2386 | |
---|
2387 | /* Configure Flow Control after forcing link up. */ |
---|
2388 | ret_val = em_config_fc_after_link_up(hw); |
---|
2389 | if(ret_val) { |
---|
2390 | DEBUGOUT("Error configuring flow control\n"); |
---|
2391 | return ret_val; |
---|
2392 | } |
---|
2393 | } |
---|
2394 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
---|
2395 | * auto-negotiation in the TXCW register and disable forced link in the |
---|
2396 | * Device Control register in an attempt to auto-negotiate with our link |
---|
2397 | * partner. |
---|
2398 | */ |
---|
2399 | else if(((hw->media_type == em_media_type_fiber) || |
---|
2400 | (hw->media_type == em_media_type_internal_serdes)) && |
---|
2401 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
---|
2402 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); |
---|
2403 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
---|
2404 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
---|
2405 | |
---|
2406 | hw->serdes_link_down = FALSE; |
---|
2407 | } |
---|
2408 | /* If we force link for non-auto-negotiation switch, check link status |
---|
2409 | * based on MAC synchronization for internal serdes media type. |
---|
2410 | */ |
---|
2411 | else if((hw->media_type == em_media_type_internal_serdes) && |
---|
2412 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
---|
2413 | /* SYNCH bit and IV bit are sticky. */ |
---|
2414 | usec_delay(10); |
---|
2415 | if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
---|
2416 | if(!(rxcw & E1000_RXCW_IV)) { |
---|
2417 | hw->serdes_link_down = FALSE; |
---|
2418 | DEBUGOUT("SERDES: Link is up.\n"); |
---|
2419 | } |
---|
2420 | } else { |
---|
2421 | hw->serdes_link_down = TRUE; |
---|
2422 | DEBUGOUT("SERDES: Link is down.\n"); |
---|
2423 | } |
---|
2424 | } |
---|
2425 | if((hw->media_type == em_media_type_internal_serdes) && |
---|
2426 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
---|
2427 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
---|
2428 | } |
---|
2429 | return E1000_SUCCESS; |
---|
2430 | } |
---|
2431 | |
---|
2432 | /****************************************************************************** |
---|
2433 | * Detects the current speed and duplex settings of the hardware. |
---|
2434 | * |
---|
2435 | * hw - Struct containing variables accessed by shared code |
---|
2436 | * speed - Speed of the connection |
---|
2437 | * duplex - Duplex setting of the connection |
---|
2438 | *****************************************************************************/ |
---|
2439 | int32_t |
---|
2440 | em_get_speed_and_duplex(struct em_hw *hw, |
---|
2441 | uint16_t *speed, |
---|
2442 | uint16_t *duplex) |
---|
2443 | { |
---|
2444 | uint32_t status; |
---|
2445 | int32_t ret_val; |
---|
2446 | uint16_t phy_data; |
---|
2447 | |
---|
2448 | DEBUGFUNC("em_get_speed_and_duplex"); |
---|
2449 | |
---|
2450 | if(hw->mac_type >= em_82543) { |
---|
2451 | status = E1000_READ_REG(hw, STATUS); |
---|
2452 | if(status & E1000_STATUS_SPEED_1000) { |
---|
2453 | *speed = SPEED_1000; |
---|
2454 | DEBUGOUT("1000 Mbs, "); |
---|
2455 | } else if(status & E1000_STATUS_SPEED_100) { |
---|
2456 | *speed = SPEED_100; |
---|
2457 | DEBUGOUT("100 Mbs, "); |
---|
2458 | } else { |
---|
2459 | *speed = SPEED_10; |
---|
2460 | DEBUGOUT("10 Mbs, "); |
---|
2461 | } |
---|
2462 | |
---|
2463 | if(status & E1000_STATUS_FD) { |
---|
2464 | *duplex = FULL_DUPLEX; |
---|
2465 | DEBUGOUT("Full Duplex\r\n"); |
---|
2466 | } else { |
---|
2467 | *duplex = HALF_DUPLEX; |
---|
2468 | DEBUGOUT(" Half Duplex\r\n"); |
---|
2469 | } |
---|
2470 | } else { |
---|
2471 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); |
---|
2472 | *speed = SPEED_1000; |
---|
2473 | *duplex = FULL_DUPLEX; |
---|
2474 | } |
---|
2475 | |
---|
2476 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
---|
2477 | * if it is operating at half duplex. Here we set the duplex settings to |
---|
2478 | * match the duplex in the link partner's capabilities. |
---|
2479 | */ |
---|
2480 | if(hw->phy_type == em_phy_igp && hw->speed_downgraded) { |
---|
2481 | ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
---|
2482 | if(ret_val) |
---|
2483 | return ret_val; |
---|
2484 | |
---|
2485 | if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
---|
2486 | *duplex = HALF_DUPLEX; |
---|
2487 | else { |
---|
2488 | ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
---|
2489 | if(ret_val) |
---|
2490 | return ret_val; |
---|
2491 | if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
---|
2492 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
---|
2493 | *duplex = HALF_DUPLEX; |
---|
2494 | } |
---|
2495 | } |
---|
2496 | |
---|
2497 | return E1000_SUCCESS; |
---|
2498 | } |
---|
2499 | |
---|
2500 | /****************************************************************************** |
---|
2501 | * Blocks until autoneg completes or times out (~4.5 seconds) |
---|
2502 | * |
---|
2503 | * hw - Struct containing variables accessed by shared code |
---|
2504 | ******************************************************************************/ |
---|
2505 | int32_t |
---|
2506 | em_wait_autoneg(struct em_hw *hw) |
---|
2507 | { |
---|
2508 | int32_t ret_val; |
---|
2509 | uint16_t i; |
---|
2510 | uint16_t phy_data; |
---|
2511 | |
---|
2512 | DEBUGFUNC("em_wait_autoneg"); |
---|
2513 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
---|
2514 | |
---|
2515 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
---|
2516 | for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
---|
2517 | /* Read the MII Status Register and wait for Auto-Neg |
---|
2518 | * Complete bit to be set. |
---|
2519 | */ |
---|
2520 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
2521 | if(ret_val) |
---|
2522 | return ret_val; |
---|
2523 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
2524 | if(ret_val) |
---|
2525 | return ret_val; |
---|
2526 | if(phy_data & MII_SR_AUTONEG_COMPLETE) { |
---|
2527 | return E1000_SUCCESS; |
---|
2528 | } |
---|
2529 | msec_delay(100); |
---|
2530 | } |
---|
2531 | return E1000_SUCCESS; |
---|
2532 | } |
---|
2533 | |
---|
2534 | /****************************************************************************** |
---|
2535 | * Raises the Management Data Clock |
---|
2536 | * |
---|
2537 | * hw - Struct containing variables accessed by shared code |
---|
2538 | * ctrl - Device control register's current value |
---|
2539 | ******************************************************************************/ |
---|
2540 | static void |
---|
2541 | em_raise_mdi_clk(struct em_hw *hw, |
---|
2542 | uint32_t *ctrl) |
---|
2543 | { |
---|
2544 | /* Raise the clock input to the Management Data Clock (by setting the MDC |
---|
2545 | * bit), and then delay 10 microseconds. |
---|
2546 | */ |
---|
2547 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
---|
2548 | E1000_WRITE_FLUSH(hw); |
---|
2549 | usec_delay(10); |
---|
2550 | } |
---|
2551 | |
---|
2552 | /****************************************************************************** |
---|
2553 | * Lowers the Management Data Clock |
---|
2554 | * |
---|
2555 | * hw - Struct containing variables accessed by shared code |
---|
2556 | * ctrl - Device control register's current value |
---|
2557 | ******************************************************************************/ |
---|
2558 | static void |
---|
2559 | em_lower_mdi_clk(struct em_hw *hw, |
---|
2560 | uint32_t *ctrl) |
---|
2561 | { |
---|
2562 | /* Lower the clock input to the Management Data Clock (by clearing the MDC |
---|
2563 | * bit), and then delay 10 microseconds. |
---|
2564 | */ |
---|
2565 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
---|
2566 | E1000_WRITE_FLUSH(hw); |
---|
2567 | usec_delay(10); |
---|
2568 | } |
---|
2569 | |
---|
2570 | /****************************************************************************** |
---|
2571 | * Shifts data bits out to the PHY |
---|
2572 | * |
---|
2573 | * hw - Struct containing variables accessed by shared code |
---|
2574 | * data - Data to send out to the PHY |
---|
2575 | * count - Number of bits to shift out |
---|
2576 | * |
---|
2577 | * Bits are shifted out in MSB to LSB order. |
---|
2578 | ******************************************************************************/ |
---|
2579 | static void |
---|
2580 | em_shift_out_mdi_bits(struct em_hw *hw, |
---|
2581 | uint32_t data, |
---|
2582 | uint16_t count) |
---|
2583 | { |
---|
2584 | uint32_t ctrl; |
---|
2585 | uint32_t mask; |
---|
2586 | |
---|
2587 | /* We need to shift "count" number of bits out to the PHY. So, the value |
---|
2588 | * in the "data" parameter will be shifted out to the PHY one bit at a |
---|
2589 | * time. In order to do this, "data" must be broken down into bits. |
---|
2590 | */ |
---|
2591 | mask = 0x01; |
---|
2592 | mask <<= (count - 1); |
---|
2593 | |
---|
2594 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2595 | |
---|
2596 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
---|
2597 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
---|
2598 | |
---|
2599 | while(mask) { |
---|
2600 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
---|
2601 | * then raising and lowering the Management Data Clock. A "0" is |
---|
2602 | * shifted out to the PHY by setting the MDIO bit to "0" and then |
---|
2603 | * raising and lowering the clock. |
---|
2604 | */ |
---|
2605 | if(data & mask) ctrl |= E1000_CTRL_MDIO; |
---|
2606 | else ctrl &= ~E1000_CTRL_MDIO; |
---|
2607 | |
---|
2608 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
2609 | E1000_WRITE_FLUSH(hw); |
---|
2610 | |
---|
2611 | usec_delay(10); |
---|
2612 | |
---|
2613 | em_raise_mdi_clk(hw, &ctrl); |
---|
2614 | em_lower_mdi_clk(hw, &ctrl); |
---|
2615 | |
---|
2616 | mask = mask >> 1; |
---|
2617 | } |
---|
2618 | } |
---|
2619 | |
---|
2620 | /****************************************************************************** |
---|
2621 | * Shifts data bits in from the PHY |
---|
2622 | * |
---|
2623 | * hw - Struct containing variables accessed by shared code |
---|
2624 | * |
---|
2625 | * Bits are shifted in in MSB to LSB order. |
---|
2626 | ******************************************************************************/ |
---|
2627 | static uint16_t |
---|
2628 | em_shift_in_mdi_bits(struct em_hw *hw) |
---|
2629 | { |
---|
2630 | uint32_t ctrl; |
---|
2631 | uint16_t data = 0; |
---|
2632 | uint8_t i; |
---|
2633 | |
---|
2634 | /* In order to read a register from the PHY, we need to shift in a total |
---|
2635 | * of 18 bits from the PHY. The first two bit (turnaround) times are used |
---|
2636 | * to avoid contention on the MDIO pin when a read operation is performed. |
---|
2637 | * These two bits are ignored by us and thrown away. Bits are "shifted in" |
---|
2638 | * by raising the input to the Management Data Clock (setting the MDC bit), |
---|
2639 | * and then reading the value of the MDIO bit. |
---|
2640 | */ |
---|
2641 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2642 | |
---|
2643 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
---|
2644 | ctrl &= ~E1000_CTRL_MDIO_DIR; |
---|
2645 | ctrl &= ~E1000_CTRL_MDIO; |
---|
2646 | |
---|
2647 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
2648 | E1000_WRITE_FLUSH(hw); |
---|
2649 | |
---|
2650 | /* Raise and Lower the clock before reading in the data. This accounts for |
---|
2651 | * the turnaround bits. The first clock occurred when we clocked out the |
---|
2652 | * last bit of the Register Address. |
---|
2653 | */ |
---|
2654 | em_raise_mdi_clk(hw, &ctrl); |
---|
2655 | em_lower_mdi_clk(hw, &ctrl); |
---|
2656 | |
---|
2657 | for(data = 0, i = 0; i < 16; i++) { |
---|
2658 | data = data << 1; |
---|
2659 | em_raise_mdi_clk(hw, &ctrl); |
---|
2660 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2661 | /* Check to see if we shifted in a "1". */ |
---|
2662 | if(ctrl & E1000_CTRL_MDIO) data |= 1; |
---|
2663 | em_lower_mdi_clk(hw, &ctrl); |
---|
2664 | } |
---|
2665 | |
---|
2666 | em_raise_mdi_clk(hw, &ctrl); |
---|
2667 | em_lower_mdi_clk(hw, &ctrl); |
---|
2668 | |
---|
2669 | return data; |
---|
2670 | } |
---|
2671 | |
---|
2672 | /***************************************************************************** |
---|
2673 | * Reads the value from a PHY register, if the value is on a specific non zero |
---|
2674 | * page, sets the page first. |
---|
2675 | * hw - Struct containing variables accessed by shared code |
---|
2676 | * reg_addr - address of the PHY register to read |
---|
2677 | ******************************************************************************/ |
---|
2678 | int32_t |
---|
2679 | em_read_phy_reg(struct em_hw *hw, |
---|
2680 | uint32_t reg_addr, |
---|
2681 | uint16_t *phy_data) |
---|
2682 | { |
---|
2683 | uint32_t ret_val; |
---|
2684 | |
---|
2685 | DEBUGFUNC("em_read_phy_reg"); |
---|
2686 | |
---|
2687 | if((hw->phy_type == em_phy_igp || |
---|
2688 | hw->phy_type == em_phy_igp_2) && |
---|
2689 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
---|
2690 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
---|
2691 | (uint16_t)reg_addr); |
---|
2692 | if(ret_val) { |
---|
2693 | return ret_val; |
---|
2694 | } |
---|
2695 | } |
---|
2696 | |
---|
2697 | ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
---|
2698 | phy_data); |
---|
2699 | |
---|
2700 | return ret_val; |
---|
2701 | } |
---|
2702 | |
---|
2703 | int32_t |
---|
2704 | em_read_phy_reg_ex(struct em_hw *hw, |
---|
2705 | uint32_t reg_addr, |
---|
2706 | uint16_t *phy_data) |
---|
2707 | { |
---|
2708 | uint32_t i; |
---|
2709 | uint32_t mdic = 0; |
---|
2710 | const uint32_t phy_addr = 1; |
---|
2711 | |
---|
2712 | DEBUGFUNC("em_read_phy_reg_ex"); |
---|
2713 | |
---|
2714 | if(reg_addr > MAX_PHY_REG_ADDRESS) { |
---|
2715 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
---|
2716 | return -E1000_ERR_PARAM; |
---|
2717 | } |
---|
2718 | |
---|
2719 | if(hw->mac_type > em_82543) { |
---|
2720 | /* Set up Op-code, Phy Address, and register address in the MDI |
---|
2721 | * Control register. The MAC will take care of interfacing with the |
---|
2722 | * PHY to retrieve the desired data. |
---|
2723 | */ |
---|
2724 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
---|
2725 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
---|
2726 | (E1000_MDIC_OP_READ)); |
---|
2727 | |
---|
2728 | E1000_WRITE_REG(hw, MDIC, mdic); |
---|
2729 | |
---|
2730 | /* Poll the ready bit to see if the MDI read completed */ |
---|
2731 | for(i = 0; i < 64; i++) { |
---|
2732 | usec_delay(50); |
---|
2733 | mdic = E1000_READ_REG(hw, MDIC); |
---|
2734 | if(mdic & E1000_MDIC_READY) break; |
---|
2735 | } |
---|
2736 | if(!(mdic & E1000_MDIC_READY)) { |
---|
2737 | DEBUGOUT("MDI Read did not complete\n"); |
---|
2738 | return -E1000_ERR_PHY; |
---|
2739 | } |
---|
2740 | if(mdic & E1000_MDIC_ERROR) { |
---|
2741 | DEBUGOUT("MDI Error\n"); |
---|
2742 | return -E1000_ERR_PHY; |
---|
2743 | } |
---|
2744 | *phy_data = (uint16_t) mdic; |
---|
2745 | } else { |
---|
2746 | /* We must first send a preamble through the MDIO pin to signal the |
---|
2747 | * beginning of an MII instruction. This is done by sending 32 |
---|
2748 | * consecutive "1" bits. |
---|
2749 | */ |
---|
2750 | em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
---|
2751 | |
---|
2752 | /* Now combine the next few fields that are required for a read |
---|
2753 | * operation. We use this method instead of calling the |
---|
2754 | * em_shift_out_mdi_bits routine five different times. The format of |
---|
2755 | * a MII read instruction consists of a shift out of 14 bits and is |
---|
2756 | * defined as follows: |
---|
2757 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
---|
2758 | * followed by a shift in of 18 bits. This first two bits shifted in |
---|
2759 | * are TurnAround bits used to avoid contention on the MDIO pin when a |
---|
2760 | * READ operation is performed. These two bits are thrown away |
---|
2761 | * followed by a shift in of 16 bits which contains the desired data. |
---|
2762 | */ |
---|
2763 | mdic = ((reg_addr) | (phy_addr << 5) | |
---|
2764 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
---|
2765 | |
---|
2766 | em_shift_out_mdi_bits(hw, mdic, 14); |
---|
2767 | |
---|
2768 | /* Now that we've shifted out the read command to the MII, we need to |
---|
2769 | * "shift in" the 16-bit value (18 total bits) of the requested PHY |
---|
2770 | * register address. |
---|
2771 | */ |
---|
2772 | *phy_data = em_shift_in_mdi_bits(hw); |
---|
2773 | } |
---|
2774 | return E1000_SUCCESS; |
---|
2775 | } |
---|
2776 | |
---|
2777 | /****************************************************************************** |
---|
2778 | * Writes a value to a PHY register |
---|
2779 | * |
---|
2780 | * hw - Struct containing variables accessed by shared code |
---|
2781 | * reg_addr - address of the PHY register to write |
---|
2782 | * data - data to write to the PHY |
---|
2783 | ******************************************************************************/ |
---|
2784 | int32_t |
---|
2785 | em_write_phy_reg(struct em_hw *hw, |
---|
2786 | uint32_t reg_addr, |
---|
2787 | uint16_t phy_data) |
---|
2788 | { |
---|
2789 | uint32_t ret_val; |
---|
2790 | |
---|
2791 | DEBUGFUNC("em_write_phy_reg"); |
---|
2792 | |
---|
2793 | if((hw->phy_type == em_phy_igp || |
---|
2794 | hw->phy_type == em_phy_igp_2) && |
---|
2795 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
---|
2796 | ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
---|
2797 | (uint16_t)reg_addr); |
---|
2798 | if(ret_val) { |
---|
2799 | return ret_val; |
---|
2800 | } |
---|
2801 | } |
---|
2802 | |
---|
2803 | ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
---|
2804 | phy_data); |
---|
2805 | |
---|
2806 | return ret_val; |
---|
2807 | } |
---|
2808 | |
---|
2809 | int32_t |
---|
2810 | em_write_phy_reg_ex(struct em_hw *hw, |
---|
2811 | uint32_t reg_addr, |
---|
2812 | uint16_t phy_data) |
---|
2813 | { |
---|
2814 | uint32_t i; |
---|
2815 | uint32_t mdic = 0; |
---|
2816 | const uint32_t phy_addr = 1; |
---|
2817 | |
---|
2818 | DEBUGFUNC("em_write_phy_reg_ex"); |
---|
2819 | |
---|
2820 | if(reg_addr > MAX_PHY_REG_ADDRESS) { |
---|
2821 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
---|
2822 | return -E1000_ERR_PARAM; |
---|
2823 | } |
---|
2824 | |
---|
2825 | if(hw->mac_type > em_82543) { |
---|
2826 | /* Set up Op-code, Phy Address, register address, and data intended |
---|
2827 | * for the PHY register in the MDI Control register. The MAC will take |
---|
2828 | * care of interfacing with the PHY to send the desired data. |
---|
2829 | */ |
---|
2830 | mdic = (((uint32_t) phy_data) | |
---|
2831 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
---|
2832 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
---|
2833 | (E1000_MDIC_OP_WRITE)); |
---|
2834 | |
---|
2835 | E1000_WRITE_REG(hw, MDIC, mdic); |
---|
2836 | |
---|
2837 | /* Poll the ready bit to see if the MDI read completed */ |
---|
2838 | for(i = 0; i < 640; i++) { |
---|
2839 | usec_delay(5); |
---|
2840 | mdic = E1000_READ_REG(hw, MDIC); |
---|
2841 | if(mdic & E1000_MDIC_READY) break; |
---|
2842 | } |
---|
2843 | if(!(mdic & E1000_MDIC_READY)) { |
---|
2844 | DEBUGOUT("MDI Write did not complete\n"); |
---|
2845 | return -E1000_ERR_PHY; |
---|
2846 | } |
---|
2847 | } else { |
---|
2848 | /* We'll need to use the SW defined pins to shift the write command |
---|
2849 | * out to the PHY. We first send a preamble to the PHY to signal the |
---|
2850 | * beginning of the MII instruction. This is done by sending 32 |
---|
2851 | * consecutive "1" bits. |
---|
2852 | */ |
---|
2853 | em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
---|
2854 | |
---|
2855 | /* Now combine the remaining required fields that will indicate a |
---|
2856 | * write operation. We use this method instead of calling the |
---|
2857 | * em_shift_out_mdi_bits routine for each field in the command. The |
---|
2858 | * format of a MII write instruction is as follows: |
---|
2859 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
---|
2860 | */ |
---|
2861 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
---|
2862 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
---|
2863 | mdic <<= 16; |
---|
2864 | mdic |= (uint32_t) phy_data; |
---|
2865 | |
---|
2866 | em_shift_out_mdi_bits(hw, mdic, 32); |
---|
2867 | } |
---|
2868 | |
---|
2869 | return E1000_SUCCESS; |
---|
2870 | } |
---|
2871 | |
---|
2872 | |
---|
2873 | /****************************************************************************** |
---|
2874 | * Returns the PHY to the power-on reset state |
---|
2875 | * |
---|
2876 | * hw - Struct containing variables accessed by shared code |
---|
2877 | ******************************************************************************/ |
---|
2878 | int32_t |
---|
2879 | em_phy_hw_reset(struct em_hw *hw) |
---|
2880 | { |
---|
2881 | uint32_t ctrl, ctrl_ext; |
---|
2882 | uint32_t led_ctrl; |
---|
2883 | int32_t ret_val; |
---|
2884 | |
---|
2885 | DEBUGFUNC("em_phy_hw_reset"); |
---|
2886 | |
---|
2887 | /* In the case of the phy reset being blocked, it's not an error, we |
---|
2888 | * simply return success without performing the reset. */ |
---|
2889 | ret_val = em_check_phy_reset_block(hw); |
---|
2890 | if (ret_val) |
---|
2891 | return E1000_SUCCESS; |
---|
2892 | |
---|
2893 | DEBUGOUT("Resetting Phy...\n"); |
---|
2894 | |
---|
2895 | if(hw->mac_type > em_82543) { |
---|
2896 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
---|
2897 | * bit. Then, take it out of reset. |
---|
2898 | */ |
---|
2899 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
2900 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
---|
2901 | E1000_WRITE_FLUSH(hw); |
---|
2902 | msec_delay(10); |
---|
2903 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
2904 | E1000_WRITE_FLUSH(hw); |
---|
2905 | } else { |
---|
2906 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
---|
2907 | * bit to put the PHY into reset. Then, take it out of reset. |
---|
2908 | */ |
---|
2909 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
---|
2910 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
---|
2911 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
---|
2912 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
---|
2913 | E1000_WRITE_FLUSH(hw); |
---|
2914 | msec_delay(10); |
---|
2915 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
---|
2916 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
---|
2917 | E1000_WRITE_FLUSH(hw); |
---|
2918 | } |
---|
2919 | usec_delay(150); |
---|
2920 | |
---|
2921 | if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { |
---|
2922 | /* Configure activity LED after PHY reset */ |
---|
2923 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
---|
2924 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
---|
2925 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
---|
2926 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
---|
2927 | } |
---|
2928 | |
---|
2929 | /* Wait for FW to finish PHY configuration. */ |
---|
2930 | ret_val = em_get_phy_cfg_done(hw); |
---|
2931 | |
---|
2932 | return ret_val; |
---|
2933 | } |
---|
2934 | |
---|
2935 | /****************************************************************************** |
---|
2936 | * Resets the PHY |
---|
2937 | * |
---|
2938 | * hw - Struct containing variables accessed by shared code |
---|
2939 | * |
---|
2940 | * Sets bit 15 of the MII Control regiser |
---|
2941 | ******************************************************************************/ |
---|
2942 | int32_t |
---|
2943 | em_phy_reset(struct em_hw *hw) |
---|
2944 | { |
---|
2945 | int32_t ret_val; |
---|
2946 | uint16_t phy_data; |
---|
2947 | |
---|
2948 | DEBUGFUNC("em_phy_reset"); |
---|
2949 | |
---|
2950 | /* In the case of the phy reset being blocked, it's not an error, we |
---|
2951 | * simply return success without performing the reset. */ |
---|
2952 | ret_val = em_check_phy_reset_block(hw); |
---|
2953 | if (ret_val) |
---|
2954 | return E1000_SUCCESS; |
---|
2955 | |
---|
2956 | switch (hw->mac_type) { |
---|
2957 | case em_82541_rev_2: |
---|
2958 | ret_val = em_phy_hw_reset(hw); |
---|
2959 | if(ret_val) |
---|
2960 | return ret_val; |
---|
2961 | break; |
---|
2962 | default: |
---|
2963 | ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); |
---|
2964 | if(ret_val) |
---|
2965 | return ret_val; |
---|
2966 | |
---|
2967 | phy_data |= MII_CR_RESET; |
---|
2968 | ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); |
---|
2969 | if(ret_val) |
---|
2970 | return ret_val; |
---|
2971 | |
---|
2972 | usec_delay(1); |
---|
2973 | break; |
---|
2974 | } |
---|
2975 | |
---|
2976 | if(hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) |
---|
2977 | em_phy_init_script(hw); |
---|
2978 | |
---|
2979 | return E1000_SUCCESS; |
---|
2980 | } |
---|
2981 | |
---|
2982 | /****************************************************************************** |
---|
2983 | * Probes the expected PHY address for known PHY IDs |
---|
2984 | * |
---|
2985 | * hw - Struct containing variables accessed by shared code |
---|
2986 | ******************************************************************************/ |
---|
2987 | int32_t |
---|
2988 | em_detect_gig_phy(struct em_hw *hw) |
---|
2989 | { |
---|
2990 | int32_t phy_init_status, ret_val; |
---|
2991 | uint16_t phy_id_high, phy_id_low; |
---|
2992 | boolean_t match = FALSE; |
---|
2993 | |
---|
2994 | DEBUGFUNC("em_detect_gig_phy"); |
---|
2995 | |
---|
2996 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
---|
2997 | ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
---|
2998 | if(ret_val) |
---|
2999 | return ret_val; |
---|
3000 | |
---|
3001 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
---|
3002 | usec_delay(20); |
---|
3003 | ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
---|
3004 | if(ret_val) |
---|
3005 | return ret_val; |
---|
3006 | |
---|
3007 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
---|
3008 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
---|
3009 | |
---|
3010 | switch(hw->mac_type) { |
---|
3011 | case em_82543: |
---|
3012 | if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
---|
3013 | break; |
---|
3014 | case em_82544: |
---|
3015 | if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
---|
3016 | break; |
---|
3017 | case em_82540: |
---|
3018 | case em_82545: |
---|
3019 | case em_82545_rev_3: |
---|
3020 | case em_82546: |
---|
3021 | case em_82546_rev_3: |
---|
3022 | if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
---|
3023 | break; |
---|
3024 | case em_82541: |
---|
3025 | case em_82541_rev_2: |
---|
3026 | case em_82547: |
---|
3027 | case em_82547_rev_2: |
---|
3028 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
---|
3029 | break; |
---|
3030 | case em_82573: |
---|
3031 | if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
---|
3032 | break; |
---|
3033 | default: |
---|
3034 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
---|
3035 | return -E1000_ERR_CONFIG; |
---|
3036 | } |
---|
3037 | phy_init_status = em_set_phy_type(hw); |
---|
3038 | |
---|
3039 | if ((match) && (phy_init_status == E1000_SUCCESS)) { |
---|
3040 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
---|
3041 | return E1000_SUCCESS; |
---|
3042 | } |
---|
3043 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
---|
3044 | return -E1000_ERR_PHY; |
---|
3045 | } |
---|
3046 | |
---|
3047 | /****************************************************************************** |
---|
3048 | * Resets the PHY's DSP |
---|
3049 | * |
---|
3050 | * hw - Struct containing variables accessed by shared code |
---|
3051 | ******************************************************************************/ |
---|
3052 | static int32_t |
---|
3053 | em_phy_reset_dsp(struct em_hw *hw) |
---|
3054 | { |
---|
3055 | int32_t ret_val; |
---|
3056 | DEBUGFUNC("em_phy_reset_dsp"); |
---|
3057 | |
---|
3058 | do { |
---|
3059 | ret_val = em_write_phy_reg(hw, 29, 0x001d); |
---|
3060 | if(ret_val) break; |
---|
3061 | ret_val = em_write_phy_reg(hw, 30, 0x00c1); |
---|
3062 | if(ret_val) break; |
---|
3063 | ret_val = em_write_phy_reg(hw, 30, 0x0000); |
---|
3064 | if(ret_val) break; |
---|
3065 | ret_val = E1000_SUCCESS; |
---|
3066 | } while(0); |
---|
3067 | |
---|
3068 | return ret_val; |
---|
3069 | } |
---|
3070 | |
---|
3071 | /****************************************************************************** |
---|
3072 | * Get PHY information from various PHY registers for igp PHY only. |
---|
3073 | * |
---|
3074 | * hw - Struct containing variables accessed by shared code |
---|
3075 | * phy_info - PHY information structure |
---|
3076 | ******************************************************************************/ |
---|
3077 | int32_t |
---|
3078 | em_phy_igp_get_info(struct em_hw *hw, |
---|
3079 | struct em_phy_info *phy_info) |
---|
3080 | { |
---|
3081 | int32_t ret_val; |
---|
3082 | uint16_t phy_data, polarity, min_length, max_length, average; |
---|
3083 | |
---|
3084 | DEBUGFUNC("em_phy_igp_get_info"); |
---|
3085 | |
---|
3086 | /* The downshift status is checked only once, after link is established, |
---|
3087 | * and it stored in the hw->speed_downgraded parameter. */ |
---|
3088 | phy_info->downshift = (em_downshift)hw->speed_downgraded; |
---|
3089 | |
---|
3090 | /* IGP01E1000 does not need to support it. */ |
---|
3091 | phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal; |
---|
3092 | |
---|
3093 | /* IGP01E1000 always correct polarity reversal */ |
---|
3094 | phy_info->polarity_correction = em_polarity_reversal_enabled; |
---|
3095 | |
---|
3096 | /* Check polarity status */ |
---|
3097 | ret_val = em_check_polarity(hw, &polarity); |
---|
3098 | if(ret_val) |
---|
3099 | return ret_val; |
---|
3100 | |
---|
3101 | phy_info->cable_polarity = polarity; |
---|
3102 | |
---|
3103 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
---|
3104 | if(ret_val) |
---|
3105 | return ret_val; |
---|
3106 | |
---|
3107 | phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> |
---|
3108 | IGP01E1000_PSSR_MDIX_SHIFT; |
---|
3109 | |
---|
3110 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
---|
3111 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
---|
3112 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
---|
3113 | ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
---|
3114 | if(ret_val) |
---|
3115 | return ret_val; |
---|
3116 | |
---|
3117 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
---|
3118 | SR_1000T_LOCAL_RX_STATUS_SHIFT; |
---|
3119 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
---|
3120 | SR_1000T_REMOTE_RX_STATUS_SHIFT; |
---|
3121 | |
---|
3122 | /* Get cable length */ |
---|
3123 | ret_val = em_get_cable_length(hw, &min_length, &max_length); |
---|
3124 | if(ret_val) |
---|
3125 | return ret_val; |
---|
3126 | |
---|
3127 | /* Translate to old method */ |
---|
3128 | average = (max_length + min_length) / 2; |
---|
3129 | |
---|
3130 | if(average <= em_igp_cable_length_50) |
---|
3131 | phy_info->cable_length = em_cable_length_50; |
---|
3132 | else if(average <= em_igp_cable_length_80) |
---|
3133 | phy_info->cable_length = em_cable_length_50_80; |
---|
3134 | else if(average <= em_igp_cable_length_110) |
---|
3135 | phy_info->cable_length = em_cable_length_80_110; |
---|
3136 | else if(average <= em_igp_cable_length_140) |
---|
3137 | phy_info->cable_length = em_cable_length_110_140; |
---|
3138 | else |
---|
3139 | phy_info->cable_length = em_cable_length_140; |
---|
3140 | } |
---|
3141 | |
---|
3142 | return E1000_SUCCESS; |
---|
3143 | } |
---|
3144 | |
---|
3145 | /****************************************************************************** |
---|
3146 | * Get PHY information from various PHY registers fot m88 PHY only. |
---|
3147 | * |
---|
3148 | * hw - Struct containing variables accessed by shared code |
---|
3149 | * phy_info - PHY information structure |
---|
3150 | ******************************************************************************/ |
---|
3151 | int32_t |
---|
3152 | em_phy_m88_get_info(struct em_hw *hw, |
---|
3153 | struct em_phy_info *phy_info) |
---|
3154 | { |
---|
3155 | int32_t ret_val; |
---|
3156 | uint16_t phy_data, polarity; |
---|
3157 | |
---|
3158 | DEBUGFUNC("em_phy_m88_get_info"); |
---|
3159 | |
---|
3160 | /* The downshift status is checked only once, after link is established, |
---|
3161 | * and it stored in the hw->speed_downgraded parameter. */ |
---|
3162 | phy_info->downshift = (em_downshift)hw->speed_downgraded; |
---|
3163 | |
---|
3164 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
---|
3165 | if(ret_val) |
---|
3166 | return ret_val; |
---|
3167 | |
---|
3168 | phy_info->extended_10bt_distance = |
---|
3169 | (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
---|
3170 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; |
---|
3171 | phy_info->polarity_correction = |
---|
3172 | (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
---|
3173 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; |
---|
3174 | |
---|
3175 | /* Check polarity status */ |
---|
3176 | ret_val = em_check_polarity(hw, &polarity); |
---|
3177 | if(ret_val) |
---|
3178 | return ret_val; |
---|
3179 | phy_info->cable_polarity = polarity; |
---|
3180 | |
---|
3181 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
---|
3182 | if(ret_val) |
---|
3183 | return ret_val; |
---|
3184 | |
---|
3185 | phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> |
---|
3186 | M88E1000_PSSR_MDIX_SHIFT; |
---|
3187 | |
---|
3188 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
---|
3189 | /* Cable Length Estimation and Local/Remote Receiver Information |
---|
3190 | * are only valid at 1000 Mbps. |
---|
3191 | */ |
---|
3192 | phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
---|
3193 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
---|
3194 | |
---|
3195 | ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
---|
3196 | if(ret_val) |
---|
3197 | return ret_val; |
---|
3198 | |
---|
3199 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
---|
3200 | SR_1000T_LOCAL_RX_STATUS_SHIFT; |
---|
3201 | |
---|
3202 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
---|
3203 | SR_1000T_REMOTE_RX_STATUS_SHIFT; |
---|
3204 | } |
---|
3205 | |
---|
3206 | return E1000_SUCCESS; |
---|
3207 | } |
---|
3208 | |
---|
3209 | /****************************************************************************** |
---|
3210 | * Get PHY information from various PHY registers |
---|
3211 | * |
---|
3212 | * hw - Struct containing variables accessed by shared code |
---|
3213 | * phy_info - PHY information structure |
---|
3214 | ******************************************************************************/ |
---|
3215 | int32_t |
---|
3216 | em_phy_get_info(struct em_hw *hw, |
---|
3217 | struct em_phy_info *phy_info) |
---|
3218 | { |
---|
3219 | int32_t ret_val; |
---|
3220 | uint16_t phy_data; |
---|
3221 | |
---|
3222 | DEBUGFUNC("em_phy_get_info"); |
---|
3223 | |
---|
3224 | phy_info->cable_length = em_cable_length_undefined; |
---|
3225 | phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined; |
---|
3226 | phy_info->cable_polarity = em_rev_polarity_undefined; |
---|
3227 | phy_info->downshift = em_downshift_undefined; |
---|
3228 | phy_info->polarity_correction = em_polarity_reversal_undefined; |
---|
3229 | phy_info->mdix_mode = em_auto_x_mode_undefined; |
---|
3230 | phy_info->local_rx = em_1000t_rx_status_undefined; |
---|
3231 | phy_info->remote_rx = em_1000t_rx_status_undefined; |
---|
3232 | |
---|
3233 | if(hw->media_type != em_media_type_copper) { |
---|
3234 | DEBUGOUT("PHY info is only valid for copper media\n"); |
---|
3235 | return -E1000_ERR_CONFIG; |
---|
3236 | } |
---|
3237 | |
---|
3238 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
3239 | if(ret_val) |
---|
3240 | return ret_val; |
---|
3241 | |
---|
3242 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); |
---|
3243 | if(ret_val) |
---|
3244 | return ret_val; |
---|
3245 | |
---|
3246 | if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
---|
3247 | DEBUGOUT("PHY info is only valid if link is up\n"); |
---|
3248 | return -E1000_ERR_CONFIG; |
---|
3249 | } |
---|
3250 | |
---|
3251 | if(hw->phy_type == em_phy_igp || |
---|
3252 | hw->phy_type == em_phy_igp_2) |
---|
3253 | return em_phy_igp_get_info(hw, phy_info); |
---|
3254 | else |
---|
3255 | return em_phy_m88_get_info(hw, phy_info); |
---|
3256 | } |
---|
3257 | |
---|
3258 | int32_t |
---|
3259 | em_validate_mdi_setting(struct em_hw *hw) |
---|
3260 | { |
---|
3261 | DEBUGFUNC("em_validate_mdi_settings"); |
---|
3262 | |
---|
3263 | if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
---|
3264 | DEBUGOUT("Invalid MDI setting detected\n"); |
---|
3265 | hw->mdix = 1; |
---|
3266 | return -E1000_ERR_CONFIG; |
---|
3267 | } |
---|
3268 | return E1000_SUCCESS; |
---|
3269 | } |
---|
3270 | |
---|
3271 | |
---|
3272 | /****************************************************************************** |
---|
3273 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
---|
3274 | * is configured. |
---|
3275 | * |
---|
3276 | * hw - Struct containing variables accessed by shared code |
---|
3277 | *****************************************************************************/ |
---|
3278 | int32_t |
---|
3279 | em_init_eeprom_params(struct em_hw *hw) |
---|
3280 | { |
---|
3281 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
3282 | uint32_t eecd = E1000_READ_REG(hw, EECD); |
---|
3283 | int32_t ret_val = E1000_SUCCESS; |
---|
3284 | uint16_t eeprom_size; |
---|
3285 | |
---|
3286 | DEBUGFUNC("em_init_eeprom_params"); |
---|
3287 | |
---|
3288 | switch (hw->mac_type) { |
---|
3289 | case em_82542_rev2_0: |
---|
3290 | case em_82542_rev2_1: |
---|
3291 | case em_82543: |
---|
3292 | case em_82544: |
---|
3293 | eeprom->type = em_eeprom_microwire; |
---|
3294 | eeprom->word_size = 64; |
---|
3295 | eeprom->opcode_bits = 3; |
---|
3296 | eeprom->address_bits = 6; |
---|
3297 | eeprom->delay_usec = 50; |
---|
3298 | eeprom->use_eerd = FALSE; |
---|
3299 | eeprom->use_eewr = FALSE; |
---|
3300 | break; |
---|
3301 | case em_82540: |
---|
3302 | case em_82545: |
---|
3303 | case em_82545_rev_3: |
---|
3304 | case em_82546: |
---|
3305 | case em_82546_rev_3: |
---|
3306 | eeprom->type = em_eeprom_microwire; |
---|
3307 | eeprom->opcode_bits = 3; |
---|
3308 | eeprom->delay_usec = 50; |
---|
3309 | if(eecd & E1000_EECD_SIZE) { |
---|
3310 | eeprom->word_size = 256; |
---|
3311 | eeprom->address_bits = 8; |
---|
3312 | } else { |
---|
3313 | eeprom->word_size = 64; |
---|
3314 | eeprom->address_bits = 6; |
---|
3315 | } |
---|
3316 | eeprom->use_eerd = FALSE; |
---|
3317 | eeprom->use_eewr = FALSE; |
---|
3318 | break; |
---|
3319 | case em_82541: |
---|
3320 | case em_82541_rev_2: |
---|
3321 | case em_82547: |
---|
3322 | case em_82547_rev_2: |
---|
3323 | if (eecd & E1000_EECD_TYPE) { |
---|
3324 | eeprom->type = em_eeprom_spi; |
---|
3325 | eeprom->opcode_bits = 8; |
---|
3326 | eeprom->delay_usec = 1; |
---|
3327 | if (eecd & E1000_EECD_ADDR_BITS) { |
---|
3328 | eeprom->page_size = 32; |
---|
3329 | eeprom->address_bits = 16; |
---|
3330 | } else { |
---|
3331 | eeprom->page_size = 8; |
---|
3332 | eeprom->address_bits = 8; |
---|
3333 | } |
---|
3334 | } else { |
---|
3335 | eeprom->type = em_eeprom_microwire; |
---|
3336 | eeprom->opcode_bits = 3; |
---|
3337 | eeprom->delay_usec = 50; |
---|
3338 | if (eecd & E1000_EECD_ADDR_BITS) { |
---|
3339 | eeprom->word_size = 256; |
---|
3340 | eeprom->address_bits = 8; |
---|
3341 | } else { |
---|
3342 | eeprom->word_size = 64; |
---|
3343 | eeprom->address_bits = 6; |
---|
3344 | } |
---|
3345 | } |
---|
3346 | eeprom->use_eerd = FALSE; |
---|
3347 | eeprom->use_eewr = FALSE; |
---|
3348 | break; |
---|
3349 | case em_82573: |
---|
3350 | eeprom->type = em_eeprom_spi; |
---|
3351 | eeprom->opcode_bits = 8; |
---|
3352 | eeprom->delay_usec = 1; |
---|
3353 | if (eecd & E1000_EECD_ADDR_BITS) { |
---|
3354 | eeprom->page_size = 32; |
---|
3355 | eeprom->address_bits = 16; |
---|
3356 | } else { |
---|
3357 | eeprom->page_size = 8; |
---|
3358 | eeprom->address_bits = 8; |
---|
3359 | } |
---|
3360 | eeprom->use_eerd = TRUE; |
---|
3361 | eeprom->use_eewr = TRUE; |
---|
3362 | if(em_is_onboard_nvm_eeprom(hw) == FALSE) { |
---|
3363 | eeprom->type = em_eeprom_flash; |
---|
3364 | eeprom->word_size = 2048; |
---|
3365 | |
---|
3366 | /* Ensure that the Autonomous FLASH update bit is cleared due to |
---|
3367 | * Flash update issue on parts which use a FLASH for NVM. */ |
---|
3368 | eecd &= ~E1000_EECD_AUPDEN; |
---|
3369 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3370 | } |
---|
3371 | break; |
---|
3372 | default: |
---|
3373 | break; |
---|
3374 | } |
---|
3375 | |
---|
3376 | if (eeprom->type == em_eeprom_spi) { |
---|
3377 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
---|
3378 | * 32KB (incremented by powers of 2). |
---|
3379 | */ |
---|
3380 | if(hw->mac_type <= em_82547_rev_2) { |
---|
3381 | /* Set to default value for initial eeprom read. */ |
---|
3382 | eeprom->word_size = 64; |
---|
3383 | ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
---|
3384 | if(ret_val) |
---|
3385 | return ret_val; |
---|
3386 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
---|
3387 | /* 256B eeprom size was not supported in earlier hardware, so we |
---|
3388 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
---|
3389 | * is never the result used in the shifting logic below. */ |
---|
3390 | if(eeprom_size) |
---|
3391 | eeprom_size++; |
---|
3392 | } else { |
---|
3393 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
---|
3394 | E1000_EECD_SIZE_EX_SHIFT); |
---|
3395 | } |
---|
3396 | |
---|
3397 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
---|
3398 | } |
---|
3399 | return ret_val; |
---|
3400 | } |
---|
3401 | |
---|
3402 | /****************************************************************************** |
---|
3403 | * Raises the EEPROM's clock input. |
---|
3404 | * |
---|
3405 | * hw - Struct containing variables accessed by shared code |
---|
3406 | * eecd - EECD's current value |
---|
3407 | *****************************************************************************/ |
---|
3408 | static void |
---|
3409 | em_raise_ee_clk(struct em_hw *hw, |
---|
3410 | uint32_t *eecd) |
---|
3411 | { |
---|
3412 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
---|
3413 | * wait <delay> microseconds. |
---|
3414 | */ |
---|
3415 | *eecd = *eecd | E1000_EECD_SK; |
---|
3416 | E1000_WRITE_REG(hw, EECD, *eecd); |
---|
3417 | E1000_WRITE_FLUSH(hw); |
---|
3418 | usec_delay(hw->eeprom.delay_usec); |
---|
3419 | } |
---|
3420 | |
---|
3421 | /****************************************************************************** |
---|
3422 | * Lowers the EEPROM's clock input. |
---|
3423 | * |
---|
3424 | * hw - Struct containing variables accessed by shared code |
---|
3425 | * eecd - EECD's current value |
---|
3426 | *****************************************************************************/ |
---|
3427 | static void |
---|
3428 | em_lower_ee_clk(struct em_hw *hw, |
---|
3429 | uint32_t *eecd) |
---|
3430 | { |
---|
3431 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
---|
3432 | * wait 50 microseconds. |
---|
3433 | */ |
---|
3434 | *eecd = *eecd & ~E1000_EECD_SK; |
---|
3435 | E1000_WRITE_REG(hw, EECD, *eecd); |
---|
3436 | E1000_WRITE_FLUSH(hw); |
---|
3437 | usec_delay(hw->eeprom.delay_usec); |
---|
3438 | } |
---|
3439 | |
---|
3440 | /****************************************************************************** |
---|
3441 | * Shift data bits out to the EEPROM. |
---|
3442 | * |
---|
3443 | * hw - Struct containing variables accessed by shared code |
---|
3444 | * data - data to send to the EEPROM |
---|
3445 | * count - number of bits to shift out |
---|
3446 | *****************************************************************************/ |
---|
3447 | static void |
---|
3448 | em_shift_out_ee_bits(struct em_hw *hw, |
---|
3449 | uint16_t data, |
---|
3450 | uint16_t count) |
---|
3451 | { |
---|
3452 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
3453 | uint32_t eecd; |
---|
3454 | uint32_t mask; |
---|
3455 | |
---|
3456 | /* We need to shift "count" bits out to the EEPROM. So, value in the |
---|
3457 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
---|
3458 | * In order to do this, "data" must be broken down into bits. |
---|
3459 | */ |
---|
3460 | mask = 0x01 << (count - 1); |
---|
3461 | eecd = E1000_READ_REG(hw, EECD); |
---|
3462 | if (eeprom->type == em_eeprom_microwire) { |
---|
3463 | eecd &= ~E1000_EECD_DO; |
---|
3464 | } else if (eeprom->type == em_eeprom_spi) { |
---|
3465 | eecd |= E1000_EECD_DO; |
---|
3466 | } |
---|
3467 | do { |
---|
3468 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
---|
3469 | * and then raising and then lowering the clock (the SK bit controls |
---|
3470 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
---|
3471 | * by setting "DI" to "0" and then raising and then lowering the clock. |
---|
3472 | */ |
---|
3473 | eecd &= ~E1000_EECD_DI; |
---|
3474 | |
---|
3475 | if(data & mask) |
---|
3476 | eecd |= E1000_EECD_DI; |
---|
3477 | |
---|
3478 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3479 | E1000_WRITE_FLUSH(hw); |
---|
3480 | |
---|
3481 | usec_delay(eeprom->delay_usec); |
---|
3482 | |
---|
3483 | em_raise_ee_clk(hw, &eecd); |
---|
3484 | em_lower_ee_clk(hw, &eecd); |
---|
3485 | |
---|
3486 | mask = mask >> 1; |
---|
3487 | |
---|
3488 | } while(mask); |
---|
3489 | |
---|
3490 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
---|
3491 | eecd &= ~E1000_EECD_DI; |
---|
3492 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3493 | } |
---|
3494 | |
---|
3495 | /****************************************************************************** |
---|
3496 | * Shift data bits in from the EEPROM |
---|
3497 | * |
---|
3498 | * hw - Struct containing variables accessed by shared code |
---|
3499 | *****************************************************************************/ |
---|
3500 | static uint16_t |
---|
3501 | em_shift_in_ee_bits(struct em_hw *hw, |
---|
3502 | uint16_t count) |
---|
3503 | { |
---|
3504 | uint32_t eecd; |
---|
3505 | uint32_t i; |
---|
3506 | uint16_t data; |
---|
3507 | |
---|
3508 | /* In order to read a register from the EEPROM, we need to shift 'count' |
---|
3509 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
---|
3510 | * input to the EEPROM (setting the SK bit), and then reading the value of |
---|
3511 | * the "DO" bit. During this "shifting in" process the "DI" bit should |
---|
3512 | * always be clear. |
---|
3513 | */ |
---|
3514 | |
---|
3515 | eecd = E1000_READ_REG(hw, EECD); |
---|
3516 | |
---|
3517 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
---|
3518 | data = 0; |
---|
3519 | |
---|
3520 | for(i = 0; i < count; i++) { |
---|
3521 | data = data << 1; |
---|
3522 | em_raise_ee_clk(hw, &eecd); |
---|
3523 | |
---|
3524 | eecd = E1000_READ_REG(hw, EECD); |
---|
3525 | |
---|
3526 | eecd &= ~(E1000_EECD_DI); |
---|
3527 | if(eecd & E1000_EECD_DO) |
---|
3528 | data |= 1; |
---|
3529 | |
---|
3530 | em_lower_ee_clk(hw, &eecd); |
---|
3531 | } |
---|
3532 | |
---|
3533 | return data; |
---|
3534 | } |
---|
3535 | |
---|
3536 | /****************************************************************************** |
---|
3537 | * Prepares EEPROM for access |
---|
3538 | * |
---|
3539 | * hw - Struct containing variables accessed by shared code |
---|
3540 | * |
---|
3541 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
---|
3542 | * function should be called before issuing a command to the EEPROM. |
---|
3543 | *****************************************************************************/ |
---|
3544 | static int32_t |
---|
3545 | em_acquire_eeprom(struct em_hw *hw) |
---|
3546 | { |
---|
3547 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
3548 | uint32_t eecd, i=0; |
---|
3549 | |
---|
3550 | DEBUGFUNC("em_acquire_eeprom"); |
---|
3551 | |
---|
3552 | if(em_get_hw_eeprom_semaphore(hw)) |
---|
3553 | return -E1000_ERR_EEPROM; |
---|
3554 | |
---|
3555 | eecd = E1000_READ_REG(hw, EECD); |
---|
3556 | |
---|
3557 | if (hw->mac_type != em_82573) { |
---|
3558 | /* Request EEPROM Access */ |
---|
3559 | if(hw->mac_type > em_82544) { |
---|
3560 | eecd |= E1000_EECD_REQ; |
---|
3561 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3562 | eecd = E1000_READ_REG(hw, EECD); |
---|
3563 | while((!(eecd & E1000_EECD_GNT)) && |
---|
3564 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
---|
3565 | i++; |
---|
3566 | usec_delay(5); |
---|
3567 | eecd = E1000_READ_REG(hw, EECD); |
---|
3568 | } |
---|
3569 | if(!(eecd & E1000_EECD_GNT)) { |
---|
3570 | eecd &= ~E1000_EECD_REQ; |
---|
3571 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3572 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
---|
3573 | return -E1000_ERR_EEPROM; |
---|
3574 | } |
---|
3575 | } |
---|
3576 | } |
---|
3577 | |
---|
3578 | /* Setup EEPROM for Read/Write */ |
---|
3579 | |
---|
3580 | if (eeprom->type == em_eeprom_microwire) { |
---|
3581 | /* Clear SK and DI */ |
---|
3582 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
---|
3583 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3584 | |
---|
3585 | /* Set CS */ |
---|
3586 | eecd |= E1000_EECD_CS; |
---|
3587 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3588 | } else if (eeprom->type == em_eeprom_spi) { |
---|
3589 | /* Clear SK and CS */ |
---|
3590 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
---|
3591 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3592 | usec_delay(1); |
---|
3593 | } |
---|
3594 | |
---|
3595 | return E1000_SUCCESS; |
---|
3596 | } |
---|
3597 | |
---|
3598 | /****************************************************************************** |
---|
3599 | * Returns EEPROM to a "standby" state |
---|
3600 | * |
---|
3601 | * hw - Struct containing variables accessed by shared code |
---|
3602 | *****************************************************************************/ |
---|
3603 | static void |
---|
3604 | em_standby_eeprom(struct em_hw *hw) |
---|
3605 | { |
---|
3606 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
3607 | uint32_t eecd; |
---|
3608 | |
---|
3609 | eecd = E1000_READ_REG(hw, EECD); |
---|
3610 | |
---|
3611 | if(eeprom->type == em_eeprom_microwire) { |
---|
3612 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
---|
3613 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3614 | E1000_WRITE_FLUSH(hw); |
---|
3615 | usec_delay(eeprom->delay_usec); |
---|
3616 | |
---|
3617 | /* Clock high */ |
---|
3618 | eecd |= E1000_EECD_SK; |
---|
3619 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3620 | E1000_WRITE_FLUSH(hw); |
---|
3621 | usec_delay(eeprom->delay_usec); |
---|
3622 | |
---|
3623 | /* Select EEPROM */ |
---|
3624 | eecd |= E1000_EECD_CS; |
---|
3625 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3626 | E1000_WRITE_FLUSH(hw); |
---|
3627 | usec_delay(eeprom->delay_usec); |
---|
3628 | |
---|
3629 | /* Clock low */ |
---|
3630 | eecd &= ~E1000_EECD_SK; |
---|
3631 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3632 | E1000_WRITE_FLUSH(hw); |
---|
3633 | usec_delay(eeprom->delay_usec); |
---|
3634 | } else if(eeprom->type == em_eeprom_spi) { |
---|
3635 | /* Toggle CS to flush commands */ |
---|
3636 | eecd |= E1000_EECD_CS; |
---|
3637 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3638 | E1000_WRITE_FLUSH(hw); |
---|
3639 | usec_delay(eeprom->delay_usec); |
---|
3640 | eecd &= ~E1000_EECD_CS; |
---|
3641 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3642 | E1000_WRITE_FLUSH(hw); |
---|
3643 | usec_delay(eeprom->delay_usec); |
---|
3644 | } |
---|
3645 | } |
---|
3646 | |
---|
3647 | /****************************************************************************** |
---|
3648 | * Terminates a command by inverting the EEPROM's chip select pin |
---|
3649 | * |
---|
3650 | * hw - Struct containing variables accessed by shared code |
---|
3651 | *****************************************************************************/ |
---|
3652 | static void |
---|
3653 | em_release_eeprom(struct em_hw *hw) |
---|
3654 | { |
---|
3655 | uint32_t eecd; |
---|
3656 | |
---|
3657 | DEBUGFUNC("em_release_eeprom"); |
---|
3658 | |
---|
3659 | eecd = E1000_READ_REG(hw, EECD); |
---|
3660 | |
---|
3661 | if (hw->eeprom.type == em_eeprom_spi) { |
---|
3662 | eecd |= E1000_EECD_CS; /* Pull CS high */ |
---|
3663 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
---|
3664 | |
---|
3665 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3666 | |
---|
3667 | usec_delay(hw->eeprom.delay_usec); |
---|
3668 | } else if(hw->eeprom.type == em_eeprom_microwire) { |
---|
3669 | /* cleanup eeprom */ |
---|
3670 | |
---|
3671 | /* CS on Microwire is active-high */ |
---|
3672 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
---|
3673 | |
---|
3674 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3675 | |
---|
3676 | /* Rising edge of clock */ |
---|
3677 | eecd |= E1000_EECD_SK; |
---|
3678 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3679 | E1000_WRITE_FLUSH(hw); |
---|
3680 | usec_delay(hw->eeprom.delay_usec); |
---|
3681 | |
---|
3682 | /* Falling edge of clock */ |
---|
3683 | eecd &= ~E1000_EECD_SK; |
---|
3684 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3685 | E1000_WRITE_FLUSH(hw); |
---|
3686 | usec_delay(hw->eeprom.delay_usec); |
---|
3687 | } |
---|
3688 | |
---|
3689 | /* Stop requesting EEPROM access */ |
---|
3690 | if(hw->mac_type > em_82544) { |
---|
3691 | eecd &= ~E1000_EECD_REQ; |
---|
3692 | E1000_WRITE_REG(hw, EECD, eecd); |
---|
3693 | } |
---|
3694 | |
---|
3695 | em_put_hw_eeprom_semaphore(hw); |
---|
3696 | } |
---|
3697 | |
---|
3698 | /****************************************************************************** |
---|
3699 | * Reads a 16 bit word from the EEPROM. |
---|
3700 | * |
---|
3701 | * hw - Struct containing variables accessed by shared code |
---|
3702 | *****************************************************************************/ |
---|
3703 | int32_t |
---|
3704 | em_spi_eeprom_ready(struct em_hw *hw) |
---|
3705 | { |
---|
3706 | uint16_t retry_count = 0; |
---|
3707 | uint8_t spi_stat_reg; |
---|
3708 | |
---|
3709 | DEBUGFUNC("em_spi_eeprom_ready"); |
---|
3710 | |
---|
3711 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
---|
3712 | * EEPROM will signal that the command has been completed by clearing |
---|
3713 | * bit 0 of the internal status register. If it's not cleared within |
---|
3714 | * 5 milliseconds, then error out. |
---|
3715 | */ |
---|
3716 | retry_count = 0; |
---|
3717 | do { |
---|
3718 | em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
---|
3719 | hw->eeprom.opcode_bits); |
---|
3720 | spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8); |
---|
3721 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
---|
3722 | break; |
---|
3723 | |
---|
3724 | usec_delay(5); |
---|
3725 | retry_count += 5; |
---|
3726 | |
---|
3727 | em_standby_eeprom(hw); |
---|
3728 | } while(retry_count < EEPROM_MAX_RETRY_SPI); |
---|
3729 | |
---|
3730 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
---|
3731 | * only 0-5mSec on 5V devices) |
---|
3732 | */ |
---|
3733 | if(retry_count >= EEPROM_MAX_RETRY_SPI) { |
---|
3734 | DEBUGOUT("SPI EEPROM Status error\n"); |
---|
3735 | return -E1000_ERR_EEPROM; |
---|
3736 | } |
---|
3737 | |
---|
3738 | return E1000_SUCCESS; |
---|
3739 | } |
---|
3740 | |
---|
3741 | /****************************************************************************** |
---|
3742 | * Reads a 16 bit word from the EEPROM. |
---|
3743 | * |
---|
3744 | * hw - Struct containing variables accessed by shared code |
---|
3745 | * offset - offset of word in the EEPROM to read |
---|
3746 | * data - word read from the EEPROM |
---|
3747 | * words - number of words to read |
---|
3748 | *****************************************************************************/ |
---|
3749 | int32_t |
---|
3750 | em_read_eeprom(struct em_hw *hw, |
---|
3751 | uint16_t offset, |
---|
3752 | uint16_t words, |
---|
3753 | uint16_t *data) |
---|
3754 | { |
---|
3755 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
3756 | uint32_t i = 0; |
---|
3757 | int32_t ret_val; |
---|
3758 | |
---|
3759 | DEBUGFUNC("em_read_eeprom"); |
---|
3760 | |
---|
3761 | /* A check for invalid values: offset too large, too many words, and not |
---|
3762 | * enough words. |
---|
3763 | */ |
---|
3764 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
---|
3765 | (words == 0)) { |
---|
3766 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
---|
3767 | return -E1000_ERR_EEPROM; |
---|
3768 | } |
---|
3769 | |
---|
3770 | /* FLASH reads without acquiring the semaphore are safe in 82573-based |
---|
3771 | * controllers. |
---|
3772 | */ |
---|
3773 | if ((em_is_onboard_nvm_eeprom(hw) == TRUE) || |
---|
3774 | (hw->mac_type != em_82573)) { |
---|
3775 | /* Prepare the EEPROM for reading */ |
---|
3776 | if(em_acquire_eeprom(hw) != E1000_SUCCESS) |
---|
3777 | return -E1000_ERR_EEPROM; |
---|
3778 | } |
---|
3779 | |
---|
3780 | if(eeprom->use_eerd == TRUE) { |
---|
3781 | ret_val = em_read_eeprom_eerd(hw, offset, words, data); |
---|
3782 | if ((em_is_onboard_nvm_eeprom(hw) == TRUE) || |
---|
3783 | (hw->mac_type != em_82573)) |
---|
3784 | em_release_eeprom(hw); |
---|
3785 | return ret_val; |
---|
3786 | } |
---|
3787 | |
---|
3788 | if(eeprom->type == em_eeprom_spi) { |
---|
3789 | uint16_t word_in; |
---|
3790 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
---|
3791 | |
---|
3792 | if(em_spi_eeprom_ready(hw)) { |
---|
3793 | em_release_eeprom(hw); |
---|
3794 | return -E1000_ERR_EEPROM; |
---|
3795 | } |
---|
3796 | |
---|
3797 | em_standby_eeprom(hw); |
---|
3798 | |
---|
3799 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
---|
3800 | if((eeprom->address_bits == 8) && (offset >= 128)) |
---|
3801 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
---|
3802 | |
---|
3803 | /* Send the READ command (opcode + addr) */ |
---|
3804 | em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
---|
3805 | em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); |
---|
3806 | |
---|
3807 | /* Read the data. The address of the eeprom internally increments with |
---|
3808 | * each byte (spi) being read, saving on the overhead of eeprom setup |
---|
3809 | * and tear-down. The address counter will roll over if reading beyond |
---|
3810 | * the size of the eeprom, thus allowing the entire memory to be read |
---|
3811 | * starting from any offset. */ |
---|
3812 | for (i = 0; i < words; i++) { |
---|
3813 | word_in = em_shift_in_ee_bits(hw, 16); |
---|
3814 | data[i] = (word_in >> 8) | (word_in << 8); |
---|
3815 | } |
---|
3816 | } else if(eeprom->type == em_eeprom_microwire) { |
---|
3817 | for (i = 0; i < words; i++) { |
---|
3818 | /* Send the READ command (opcode + addr) */ |
---|
3819 | em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, |
---|
3820 | eeprom->opcode_bits); |
---|
3821 | em_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
---|
3822 | eeprom->address_bits); |
---|
3823 | |
---|
3824 | /* Read the data. For microwire, each word requires the overhead |
---|
3825 | * of eeprom setup and tear-down. */ |
---|
3826 | data[i] = em_shift_in_ee_bits(hw, 16); |
---|
3827 | em_standby_eeprom(hw); |
---|
3828 | } |
---|
3829 | } |
---|
3830 | |
---|
3831 | /* End this read operation */ |
---|
3832 | em_release_eeprom(hw); |
---|
3833 | |
---|
3834 | return E1000_SUCCESS; |
---|
3835 | } |
---|
3836 | |
---|
3837 | /****************************************************************************** |
---|
3838 | * Reads a 16 bit word from the EEPROM using the EERD register. |
---|
3839 | * |
---|
3840 | * hw - Struct containing variables accessed by shared code |
---|
3841 | * offset - offset of word in the EEPROM to read |
---|
3842 | * data - word read from the EEPROM |
---|
3843 | * words - number of words to read |
---|
3844 | *****************************************************************************/ |
---|
3845 | int32_t |
---|
3846 | em_read_eeprom_eerd(struct em_hw *hw, |
---|
3847 | uint16_t offset, |
---|
3848 | uint16_t words, |
---|
3849 | uint16_t *data) |
---|
3850 | { |
---|
3851 | uint32_t i, eerd = 0; |
---|
3852 | int32_t error = 0; |
---|
3853 | |
---|
3854 | for (i = 0; i < words; i++) { |
---|
3855 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
---|
3856 | E1000_EEPROM_RW_REG_START; |
---|
3857 | |
---|
3858 | E1000_WRITE_REG(hw, EERD, eerd); |
---|
3859 | error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
---|
3860 | |
---|
3861 | if(error) { |
---|
3862 | break; |
---|
3863 | } |
---|
3864 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
---|
3865 | |
---|
3866 | } |
---|
3867 | |
---|
3868 | return error; |
---|
3869 | } |
---|
3870 | |
---|
3871 | /****************************************************************************** |
---|
3872 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
---|
3873 | * |
---|
3874 | * hw - Struct containing variables accessed by shared code |
---|
3875 | * offset - offset of word in the EEPROM to read |
---|
3876 | * data - word read from the EEPROM |
---|
3877 | * words - number of words to read |
---|
3878 | *****************************************************************************/ |
---|
3879 | int32_t |
---|
3880 | em_write_eeprom_eewr(struct em_hw *hw, |
---|
3881 | uint16_t offset, |
---|
3882 | uint16_t words, |
---|
3883 | uint16_t *data) |
---|
3884 | { |
---|
3885 | uint32_t register_value = 0; |
---|
3886 | uint32_t i = 0; |
---|
3887 | int32_t error = 0; |
---|
3888 | |
---|
3889 | for (i = 0; i < words; i++) { |
---|
3890 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
---|
3891 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
---|
3892 | E1000_EEPROM_RW_REG_START; |
---|
3893 | |
---|
3894 | error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
---|
3895 | if(error) { |
---|
3896 | break; |
---|
3897 | } |
---|
3898 | |
---|
3899 | E1000_WRITE_REG(hw, EEWR, register_value); |
---|
3900 | |
---|
3901 | error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
---|
3902 | |
---|
3903 | if(error) { |
---|
3904 | break; |
---|
3905 | } |
---|
3906 | } |
---|
3907 | |
---|
3908 | return error; |
---|
3909 | } |
---|
3910 | |
---|
3911 | /****************************************************************************** |
---|
3912 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
---|
3913 | * |
---|
3914 | * hw - Struct containing variables accessed by shared code |
---|
3915 | *****************************************************************************/ |
---|
3916 | int32_t |
---|
3917 | em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) |
---|
3918 | { |
---|
3919 | uint32_t attempts = 100000; |
---|
3920 | uint32_t i, reg = 0; |
---|
3921 | int32_t done = E1000_ERR_EEPROM; |
---|
3922 | |
---|
3923 | for(i = 0; i < attempts; i++) { |
---|
3924 | if(eerd == E1000_EEPROM_POLL_READ) |
---|
3925 | reg = E1000_READ_REG(hw, EERD); |
---|
3926 | else |
---|
3927 | reg = E1000_READ_REG(hw, EEWR); |
---|
3928 | |
---|
3929 | if(reg & E1000_EEPROM_RW_REG_DONE) { |
---|
3930 | done = E1000_SUCCESS; |
---|
3931 | break; |
---|
3932 | } |
---|
3933 | usec_delay(5); |
---|
3934 | } |
---|
3935 | |
---|
3936 | return done; |
---|
3937 | } |
---|
3938 | |
---|
3939 | /*************************************************************************** |
---|
3940 | * Description: Determines if the onboard NVM is FLASH or EEPROM. |
---|
3941 | * |
---|
3942 | * hw - Struct containing variables accessed by shared code |
---|
3943 | ****************************************************************************/ |
---|
3944 | boolean_t |
---|
3945 | em_is_onboard_nvm_eeprom(struct em_hw *hw) |
---|
3946 | { |
---|
3947 | uint32_t eecd = 0; |
---|
3948 | |
---|
3949 | if(hw->mac_type == em_82573) { |
---|
3950 | eecd = E1000_READ_REG(hw, EECD); |
---|
3951 | |
---|
3952 | /* Isolate bits 15 & 16 */ |
---|
3953 | eecd = ((eecd >> 15) & 0x03); |
---|
3954 | |
---|
3955 | /* If both bits are set, device is Flash type */ |
---|
3956 | if(eecd == 0x03) { |
---|
3957 | return FALSE; |
---|
3958 | } |
---|
3959 | } |
---|
3960 | return TRUE; |
---|
3961 | } |
---|
3962 | |
---|
3963 | /****************************************************************************** |
---|
3964 | * Verifies that the EEPROM has a valid checksum |
---|
3965 | * |
---|
3966 | * hw - Struct containing variables accessed by shared code |
---|
3967 | * |
---|
3968 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
---|
3969 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
---|
3970 | * valid. |
---|
3971 | *****************************************************************************/ |
---|
3972 | int32_t |
---|
3973 | em_validate_eeprom_checksum(struct em_hw *hw) |
---|
3974 | { |
---|
3975 | uint16_t checksum = 0; |
---|
3976 | uint16_t i, eeprom_data; |
---|
3977 | |
---|
3978 | DEBUGFUNC("em_validate_eeprom_checksum"); |
---|
3979 | |
---|
3980 | if ((hw->mac_type == em_82573) && |
---|
3981 | (em_is_onboard_nvm_eeprom(hw) == FALSE)) { |
---|
3982 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
---|
3983 | * 10h-12h. Checksum may need to be fixed. */ |
---|
3984 | em_read_eeprom(hw, 0x10, 1, &eeprom_data); |
---|
3985 | if ((eeprom_data & 0x10) == 0) { |
---|
3986 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum |
---|
3987 | * has already been fixed. If the checksum is still wrong and this |
---|
3988 | * bit is a 1, we need to return bad checksum. Otherwise, we need |
---|
3989 | * to set this bit to a 1 and update the checksum. */ |
---|
3990 | em_read_eeprom(hw, 0x23, 1, &eeprom_data); |
---|
3991 | if ((eeprom_data & 0x8000) == 0) { |
---|
3992 | eeprom_data |= 0x8000; |
---|
3993 | em_write_eeprom(hw, 0x23, 1, &eeprom_data); |
---|
3994 | em_update_eeprom_checksum(hw); |
---|
3995 | } |
---|
3996 | } |
---|
3997 | } |
---|
3998 | |
---|
3999 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
---|
4000 | if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
---|
4001 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4002 | return -E1000_ERR_EEPROM; |
---|
4003 | } |
---|
4004 | checksum += eeprom_data; |
---|
4005 | } |
---|
4006 | |
---|
4007 | if(checksum == (uint16_t) EEPROM_SUM) |
---|
4008 | return E1000_SUCCESS; |
---|
4009 | else { |
---|
4010 | DEBUGOUT("EEPROM Checksum Invalid\n"); |
---|
4011 | return -E1000_ERR_EEPROM; |
---|
4012 | } |
---|
4013 | } |
---|
4014 | |
---|
4015 | /****************************************************************************** |
---|
4016 | * Calculates the EEPROM checksum and writes it to the EEPROM |
---|
4017 | * |
---|
4018 | * hw - Struct containing variables accessed by shared code |
---|
4019 | * |
---|
4020 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
---|
4021 | * Writes the difference to word offset 63 of the EEPROM. |
---|
4022 | *****************************************************************************/ |
---|
4023 | int32_t |
---|
4024 | em_update_eeprom_checksum(struct em_hw *hw) |
---|
4025 | { |
---|
4026 | uint16_t checksum = 0; |
---|
4027 | uint16_t i, eeprom_data; |
---|
4028 | |
---|
4029 | DEBUGFUNC("em_update_eeprom_checksum"); |
---|
4030 | |
---|
4031 | for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
---|
4032 | if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
---|
4033 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4034 | return -E1000_ERR_EEPROM; |
---|
4035 | } |
---|
4036 | checksum += eeprom_data; |
---|
4037 | } |
---|
4038 | checksum = (uint16_t) EEPROM_SUM - checksum; |
---|
4039 | if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
---|
4040 | DEBUGOUT("EEPROM Write Error\n"); |
---|
4041 | return -E1000_ERR_EEPROM; |
---|
4042 | } else if (hw->eeprom.type == em_eeprom_flash) { |
---|
4043 | em_commit_shadow_ram(hw); |
---|
4044 | } |
---|
4045 | return E1000_SUCCESS; |
---|
4046 | } |
---|
4047 | |
---|
4048 | /****************************************************************************** |
---|
4049 | * Parent function for writing words to the different EEPROM types. |
---|
4050 | * |
---|
4051 | * hw - Struct containing variables accessed by shared code |
---|
4052 | * offset - offset within the EEPROM to be written to |
---|
4053 | * words - number of words to write |
---|
4054 | * data - 16 bit word to be written to the EEPROM |
---|
4055 | * |
---|
4056 | * If em_update_eeprom_checksum is not called after this function, the |
---|
4057 | * EEPROM will most likely contain an invalid checksum. |
---|
4058 | *****************************************************************************/ |
---|
4059 | int32_t |
---|
4060 | em_write_eeprom(struct em_hw *hw, |
---|
4061 | uint16_t offset, |
---|
4062 | uint16_t words, |
---|
4063 | uint16_t *data) |
---|
4064 | { |
---|
4065 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
4066 | int32_t status = 0; |
---|
4067 | |
---|
4068 | DEBUGFUNC("em_write_eeprom"); |
---|
4069 | |
---|
4070 | /* A check for invalid values: offset too large, too many words, and not |
---|
4071 | * enough words. |
---|
4072 | */ |
---|
4073 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
---|
4074 | (words == 0)) { |
---|
4075 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
---|
4076 | return -E1000_ERR_EEPROM; |
---|
4077 | } |
---|
4078 | |
---|
4079 | /* 82573 reads only through eerd */ |
---|
4080 | if(eeprom->use_eewr == TRUE) |
---|
4081 | return em_write_eeprom_eewr(hw, offset, words, data); |
---|
4082 | |
---|
4083 | /* Prepare the EEPROM for writing */ |
---|
4084 | if (em_acquire_eeprom(hw) != E1000_SUCCESS) |
---|
4085 | return -E1000_ERR_EEPROM; |
---|
4086 | |
---|
4087 | if(eeprom->type == em_eeprom_microwire) { |
---|
4088 | status = em_write_eeprom_microwire(hw, offset, words, data); |
---|
4089 | } else { |
---|
4090 | status = em_write_eeprom_spi(hw, offset, words, data); |
---|
4091 | msec_delay(10); |
---|
4092 | } |
---|
4093 | |
---|
4094 | /* Done with writing */ |
---|
4095 | em_release_eeprom(hw); |
---|
4096 | |
---|
4097 | return status; |
---|
4098 | } |
---|
4099 | |
---|
4100 | /****************************************************************************** |
---|
4101 | * Writes a 16 bit word to a given offset in an SPI EEPROM. |
---|
4102 | * |
---|
4103 | * hw - Struct containing variables accessed by shared code |
---|
4104 | * offset - offset within the EEPROM to be written to |
---|
4105 | * words - number of words to write |
---|
4106 | * data - pointer to array of 8 bit words to be written to the EEPROM |
---|
4107 | * |
---|
4108 | *****************************************************************************/ |
---|
4109 | int32_t |
---|
4110 | em_write_eeprom_spi(struct em_hw *hw, |
---|
4111 | uint16_t offset, |
---|
4112 | uint16_t words, |
---|
4113 | uint16_t *data) |
---|
4114 | { |
---|
4115 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
4116 | uint16_t widx = 0; |
---|
4117 | |
---|
4118 | DEBUGFUNC("em_write_eeprom_spi"); |
---|
4119 | |
---|
4120 | while (widx < words) { |
---|
4121 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; |
---|
4122 | |
---|
4123 | if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
---|
4124 | |
---|
4125 | em_standby_eeprom(hw); |
---|
4126 | |
---|
4127 | /* Send the WRITE ENABLE command (8 bit opcode ) */ |
---|
4128 | em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
---|
4129 | eeprom->opcode_bits); |
---|
4130 | |
---|
4131 | em_standby_eeprom(hw); |
---|
4132 | |
---|
4133 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
---|
4134 | if((eeprom->address_bits == 8) && (offset >= 128)) |
---|
4135 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
---|
4136 | |
---|
4137 | /* Send the Write command (8-bit opcode + addr) */ |
---|
4138 | em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
---|
4139 | |
---|
4140 | em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), |
---|
4141 | eeprom->address_bits); |
---|
4142 | |
---|
4143 | /* Send the data */ |
---|
4144 | |
---|
4145 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
---|
4146 | while (widx < words) { |
---|
4147 | uint16_t word_out = data[widx]; |
---|
4148 | word_out = (word_out >> 8) | (word_out << 8); |
---|
4149 | em_shift_out_ee_bits(hw, word_out, 16); |
---|
4150 | widx++; |
---|
4151 | |
---|
4152 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
---|
4153 | * operation, while the smaller eeproms are capable of an 8-byte |
---|
4154 | * PAGE WRITE operation. Break the inner loop to pass new address |
---|
4155 | */ |
---|
4156 | if((((offset + widx)*2) % eeprom->page_size) == 0) { |
---|
4157 | em_standby_eeprom(hw); |
---|
4158 | break; |
---|
4159 | } |
---|
4160 | } |
---|
4161 | } |
---|
4162 | |
---|
4163 | return E1000_SUCCESS; |
---|
4164 | } |
---|
4165 | |
---|
4166 | /****************************************************************************** |
---|
4167 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. |
---|
4168 | * |
---|
4169 | * hw - Struct containing variables accessed by shared code |
---|
4170 | * offset - offset within the EEPROM to be written to |
---|
4171 | * words - number of words to write |
---|
4172 | * data - pointer to array of 16 bit words to be written to the EEPROM |
---|
4173 | * |
---|
4174 | *****************************************************************************/ |
---|
4175 | int32_t |
---|
4176 | em_write_eeprom_microwire(struct em_hw *hw, |
---|
4177 | uint16_t offset, |
---|
4178 | uint16_t words, |
---|
4179 | uint16_t *data) |
---|
4180 | { |
---|
4181 | struct em_eeprom_info *eeprom = &hw->eeprom; |
---|
4182 | uint32_t eecd; |
---|
4183 | uint16_t words_written = 0; |
---|
4184 | uint16_t i = 0; |
---|
4185 | |
---|
4186 | DEBUGFUNC("em_write_eeprom_microwire"); |
---|
4187 | |
---|
4188 | /* Send the write enable command to the EEPROM (3-bit opcode plus |
---|
4189 | * 6/8-bit dummy address beginning with 11). It's less work to include |
---|
4190 | * the 11 of the dummy address as part of the opcode than it is to shift |
---|
4191 | * it over the correct number of bits for the address. This puts the |
---|
4192 | * EEPROM into write/erase mode. |
---|
4193 | */ |
---|
4194 | em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
---|
4195 | (uint16_t)(eeprom->opcode_bits + 2)); |
---|
4196 | |
---|
4197 | em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
---|
4198 | |
---|
4199 | /* Prepare the EEPROM */ |
---|
4200 | em_standby_eeprom(hw); |
---|
4201 | |
---|
4202 | while (words_written < words) { |
---|
4203 | /* Send the Write command (3-bit opcode + addr) */ |
---|
4204 | em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
---|
4205 | eeprom->opcode_bits); |
---|
4206 | |
---|
4207 | em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), |
---|
4208 | eeprom->address_bits); |
---|
4209 | |
---|
4210 | /* Send the data */ |
---|
4211 | em_shift_out_ee_bits(hw, data[words_written], 16); |
---|
4212 | |
---|
4213 | /* Toggle the CS line. This in effect tells the EEPROM to execute |
---|
4214 | * the previous command. |
---|
4215 | */ |
---|
4216 | em_standby_eeprom(hw); |
---|
4217 | |
---|
4218 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
---|
4219 | * signal that the command has been completed by raising the DO signal. |
---|
4220 | * If DO does not go high in 10 milliseconds, then error out. |
---|
4221 | */ |
---|
4222 | for(i = 0; i < 200; i++) { |
---|
4223 | eecd = E1000_READ_REG(hw, EECD); |
---|
4224 | if(eecd & E1000_EECD_DO) break; |
---|
4225 | usec_delay(50); |
---|
4226 | } |
---|
4227 | if(i == 200) { |
---|
4228 | DEBUGOUT("EEPROM Write did not complete\n"); |
---|
4229 | return -E1000_ERR_EEPROM; |
---|
4230 | } |
---|
4231 | |
---|
4232 | /* Recover from write */ |
---|
4233 | em_standby_eeprom(hw); |
---|
4234 | |
---|
4235 | words_written++; |
---|
4236 | } |
---|
4237 | |
---|
4238 | /* Send the write disable command to the EEPROM (3-bit opcode plus |
---|
4239 | * 6/8-bit dummy address beginning with 10). It's less work to include |
---|
4240 | * the 10 of the dummy address as part of the opcode than it is to shift |
---|
4241 | * it over the correct number of bits for the address. This takes the |
---|
4242 | * EEPROM out of write/erase mode. |
---|
4243 | */ |
---|
4244 | em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
---|
4245 | (uint16_t)(eeprom->opcode_bits + 2)); |
---|
4246 | |
---|
4247 | em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
---|
4248 | |
---|
4249 | return E1000_SUCCESS; |
---|
4250 | } |
---|
4251 | |
---|
4252 | /****************************************************************************** |
---|
4253 | * Flushes the cached eeprom to NVM. This is done by saving the modified values |
---|
4254 | * in the eeprom cache and the non modified values in the currently active bank |
---|
4255 | * to the new bank. |
---|
4256 | * |
---|
4257 | * hw - Struct containing variables accessed by shared code |
---|
4258 | * offset - offset of word in the EEPROM to read |
---|
4259 | * data - word read from the EEPROM |
---|
4260 | * words - number of words to read |
---|
4261 | *****************************************************************************/ |
---|
4262 | int32_t |
---|
4263 | em_commit_shadow_ram(struct em_hw *hw) |
---|
4264 | { |
---|
4265 | uint32_t attempts = 100000; |
---|
4266 | uint32_t eecd = 0; |
---|
4267 | uint32_t flop = 0; |
---|
4268 | uint32_t i = 0; |
---|
4269 | int32_t error = E1000_SUCCESS; |
---|
4270 | |
---|
4271 | /* The flop register will be used to determine if flash type is STM */ |
---|
4272 | flop = E1000_READ_REG(hw, FLOP); |
---|
4273 | |
---|
4274 | if (hw->mac_type == em_82573) { |
---|
4275 | for (i=0; i < attempts; i++) { |
---|
4276 | eecd = E1000_READ_REG(hw, EECD); |
---|
4277 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
---|
4278 | break; |
---|
4279 | } |
---|
4280 | usec_delay(5); |
---|
4281 | } |
---|
4282 | |
---|
4283 | if (i == attempts) { |
---|
4284 | return -E1000_ERR_EEPROM; |
---|
4285 | } |
---|
4286 | |
---|
4287 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
---|
4288 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
---|
4289 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
---|
4290 | } |
---|
4291 | |
---|
4292 | /* Perform the flash update */ |
---|
4293 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
---|
4294 | |
---|
4295 | for (i=0; i < attempts; i++) { |
---|
4296 | eecd = E1000_READ_REG(hw, EECD); |
---|
4297 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
---|
4298 | break; |
---|
4299 | } |
---|
4300 | usec_delay(5); |
---|
4301 | } |
---|
4302 | |
---|
4303 | if (i == attempts) { |
---|
4304 | return -E1000_ERR_EEPROM; |
---|
4305 | } |
---|
4306 | } |
---|
4307 | |
---|
4308 | return error; |
---|
4309 | } |
---|
4310 | |
---|
4311 | /****************************************************************************** |
---|
4312 | * Reads the adapter's part number from the EEPROM |
---|
4313 | * |
---|
4314 | * hw - Struct containing variables accessed by shared code |
---|
4315 | * part_num - Adapter's part number |
---|
4316 | *****************************************************************************/ |
---|
4317 | int32_t |
---|
4318 | em_read_part_num(struct em_hw *hw, |
---|
4319 | uint32_t *part_num) |
---|
4320 | { |
---|
4321 | uint16_t offset = EEPROM_PBA_BYTE_1; |
---|
4322 | uint16_t eeprom_data; |
---|
4323 | |
---|
4324 | DEBUGFUNC("em_read_part_num"); |
---|
4325 | |
---|
4326 | /* Get word 0 from EEPROM */ |
---|
4327 | if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
---|
4328 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4329 | return -E1000_ERR_EEPROM; |
---|
4330 | } |
---|
4331 | /* Save word 0 in upper half of part_num */ |
---|
4332 | *part_num = (uint32_t) (eeprom_data << 16); |
---|
4333 | |
---|
4334 | /* Get word 1 from EEPROM */ |
---|
4335 | if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { |
---|
4336 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4337 | return -E1000_ERR_EEPROM; |
---|
4338 | } |
---|
4339 | /* Save word 1 in lower half of part_num */ |
---|
4340 | *part_num |= eeprom_data; |
---|
4341 | |
---|
4342 | return E1000_SUCCESS; |
---|
4343 | } |
---|
4344 | |
---|
4345 | /****************************************************************************** |
---|
4346 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
---|
4347 | * second function of dual function devices |
---|
4348 | * |
---|
4349 | * hw - Struct containing variables accessed by shared code |
---|
4350 | *****************************************************************************/ |
---|
4351 | int32_t |
---|
4352 | em_read_mac_addr(struct em_hw * hw) |
---|
4353 | { |
---|
4354 | uint16_t offset; |
---|
4355 | uint16_t eeprom_data, i; |
---|
4356 | |
---|
4357 | DEBUGFUNC("em_read_mac_addr"); |
---|
4358 | |
---|
4359 | for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
---|
4360 | offset = i >> 1; |
---|
4361 | if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
---|
4362 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4363 | return -E1000_ERR_EEPROM; |
---|
4364 | } |
---|
4365 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
---|
4366 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
---|
4367 | } |
---|
4368 | if(((hw->mac_type == em_82546) || (hw->mac_type == em_82546_rev_3)) && |
---|
4369 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) |
---|
4370 | hw->perm_mac_addr[5] ^= 0x01; |
---|
4371 | |
---|
4372 | for(i = 0; i < NODE_ADDRESS_SIZE; i++) |
---|
4373 | hw->mac_addr[i] = hw->perm_mac_addr[i]; |
---|
4374 | return E1000_SUCCESS; |
---|
4375 | } |
---|
4376 | |
---|
4377 | /****************************************************************************** |
---|
4378 | * Initializes receive address filters. |
---|
4379 | * |
---|
4380 | * hw - Struct containing variables accessed by shared code |
---|
4381 | * |
---|
4382 | * Places the MAC address in receive address register 0 and clears the rest |
---|
4383 | * of the receive addresss registers. Clears the multicast table. Assumes |
---|
4384 | * the receiver is in reset when the routine is called. |
---|
4385 | *****************************************************************************/ |
---|
4386 | void |
---|
4387 | em_init_rx_addrs(struct em_hw *hw) |
---|
4388 | { |
---|
4389 | uint32_t i; |
---|
4390 | uint32_t rar_num; |
---|
4391 | |
---|
4392 | DEBUGFUNC("em_init_rx_addrs"); |
---|
4393 | |
---|
4394 | /* Setup the receive address. */ |
---|
4395 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
---|
4396 | |
---|
4397 | em_rar_set(hw, hw->mac_addr, 0); |
---|
4398 | |
---|
4399 | rar_num = E1000_RAR_ENTRIES; |
---|
4400 | /* Zero out the other 15 receive addresses. */ |
---|
4401 | DEBUGOUT("Clearing RAR[1-15]\n"); |
---|
4402 | for(i = 1; i < rar_num; i++) { |
---|
4403 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
---|
4404 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
---|
4405 | } |
---|
4406 | } |
---|
4407 | |
---|
4408 | /****************************************************************************** |
---|
4409 | * Updates the MAC's list of multicast addresses. |
---|
4410 | * |
---|
4411 | * hw - Struct containing variables accessed by shared code |
---|
4412 | * mc_addr_list - the list of new multicast addresses |
---|
4413 | * mc_addr_count - number of addresses |
---|
4414 | * pad - number of bytes between addresses in the list |
---|
4415 | * rar_used_count - offset where to start adding mc addresses into the RAR's |
---|
4416 | * |
---|
4417 | * The given list replaces any existing list. Clears the last 15 receive |
---|
4418 | * address registers and the multicast table. Uses receive address registers |
---|
4419 | * for the first 15 multicast addresses, and hashes the rest into the |
---|
4420 | * multicast table. |
---|
4421 | *****************************************************************************/ |
---|
4422 | void |
---|
4423 | em_mc_addr_list_update(struct em_hw *hw, |
---|
4424 | uint8_t *mc_addr_list, |
---|
4425 | uint32_t mc_addr_count, |
---|
4426 | uint32_t pad, |
---|
4427 | uint32_t rar_used_count) |
---|
4428 | { |
---|
4429 | uint32_t hash_value; |
---|
4430 | uint32_t i; |
---|
4431 | uint32_t num_rar_entry; |
---|
4432 | uint32_t num_mta_entry; |
---|
4433 | |
---|
4434 | DEBUGFUNC("em_mc_addr_list_update"); |
---|
4435 | |
---|
4436 | /* Set the new number of MC addresses that we are being requested to use. */ |
---|
4437 | hw->num_mc_addrs = mc_addr_count; |
---|
4438 | |
---|
4439 | /* Clear RAR[1-15] */ |
---|
4440 | DEBUGOUT(" Clearing RAR[1-15]\n"); |
---|
4441 | num_rar_entry = E1000_RAR_ENTRIES; |
---|
4442 | for(i = rar_used_count; i < num_rar_entry; i++) { |
---|
4443 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
---|
4444 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
---|
4445 | } |
---|
4446 | |
---|
4447 | /* Clear the MTA */ |
---|
4448 | DEBUGOUT(" Clearing MTA\n"); |
---|
4449 | num_mta_entry = E1000_NUM_MTA_REGISTERS; |
---|
4450 | for(i = 0; i < num_mta_entry; i++) { |
---|
4451 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
---|
4452 | } |
---|
4453 | |
---|
4454 | /* Add the new addresses */ |
---|
4455 | for(i = 0; i < mc_addr_count; i++) { |
---|
4456 | DEBUGOUT(" Adding the multicast addresses:\n"); |
---|
4457 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, |
---|
4458 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], |
---|
4459 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], |
---|
4460 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], |
---|
4461 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], |
---|
4462 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], |
---|
4463 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); |
---|
4464 | |
---|
4465 | hash_value = em_hash_mc_addr(hw, |
---|
4466 | mc_addr_list + |
---|
4467 | (i * (ETH_LENGTH_OF_ADDRESS + pad))); |
---|
4468 | |
---|
4469 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); |
---|
4470 | |
---|
4471 | /* Place this multicast address in the RAR if there is room, * |
---|
4472 | * else put it in the MTA |
---|
4473 | */ |
---|
4474 | if (rar_used_count < num_rar_entry) { |
---|
4475 | em_rar_set(hw, |
---|
4476 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), |
---|
4477 | rar_used_count); |
---|
4478 | rar_used_count++; |
---|
4479 | } else { |
---|
4480 | em_mta_set(hw, hash_value); |
---|
4481 | } |
---|
4482 | } |
---|
4483 | DEBUGOUT("MC Update Complete\n"); |
---|
4484 | } |
---|
4485 | |
---|
4486 | /****************************************************************************** |
---|
4487 | * Hashes an address to determine its location in the multicast table |
---|
4488 | * |
---|
4489 | * hw - Struct containing variables accessed by shared code |
---|
4490 | * mc_addr - the multicast address to hash |
---|
4491 | *****************************************************************************/ |
---|
4492 | uint32_t |
---|
4493 | em_hash_mc_addr(struct em_hw *hw, |
---|
4494 | uint8_t *mc_addr) |
---|
4495 | { |
---|
4496 | uint32_t hash_value = 0; |
---|
4497 | |
---|
4498 | /* The portion of the address that is used for the hash table is |
---|
4499 | * determined by the mc_filter_type setting. |
---|
4500 | */ |
---|
4501 | switch (hw->mc_filter_type) { |
---|
4502 | /* [0] [1] [2] [3] [4] [5] |
---|
4503 | * 01 AA 00 12 34 56 |
---|
4504 | * LSB MSB |
---|
4505 | */ |
---|
4506 | case 0: |
---|
4507 | /* [47:36] i.e. 0x563 for above example address */ |
---|
4508 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
---|
4509 | break; |
---|
4510 | case 1: |
---|
4511 | /* [46:35] i.e. 0xAC6 for above example address */ |
---|
4512 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); |
---|
4513 | break; |
---|
4514 | case 2: |
---|
4515 | /* [45:34] i.e. 0x5D8 for above example address */ |
---|
4516 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
---|
4517 | break; |
---|
4518 | case 3: |
---|
4519 | /* [43:32] i.e. 0x634 for above example address */ |
---|
4520 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); |
---|
4521 | break; |
---|
4522 | } |
---|
4523 | |
---|
4524 | hash_value &= 0xFFF; |
---|
4525 | |
---|
4526 | return hash_value; |
---|
4527 | } |
---|
4528 | |
---|
4529 | /****************************************************************************** |
---|
4530 | * Sets the bit in the multicast table corresponding to the hash value. |
---|
4531 | * |
---|
4532 | * hw - Struct containing variables accessed by shared code |
---|
4533 | * hash_value - Multicast address hash value |
---|
4534 | *****************************************************************************/ |
---|
4535 | void |
---|
4536 | em_mta_set(struct em_hw *hw, |
---|
4537 | uint32_t hash_value) |
---|
4538 | { |
---|
4539 | uint32_t hash_bit, hash_reg; |
---|
4540 | uint32_t mta; |
---|
4541 | uint32_t temp; |
---|
4542 | |
---|
4543 | /* The MTA is a register array of 128 32-bit registers. |
---|
4544 | * It is treated like an array of 4096 bits. We want to set |
---|
4545 | * bit BitArray[hash_value]. So we figure out what register |
---|
4546 | * the bit is in, read it, OR in the new bit, then write |
---|
4547 | * back the new value. The register is determined by the |
---|
4548 | * upper 7 bits of the hash value and the bit within that |
---|
4549 | * register are determined by the lower 5 bits of the value. |
---|
4550 | */ |
---|
4551 | hash_reg = (hash_value >> 5) & 0x7F; |
---|
4552 | hash_bit = hash_value & 0x1F; |
---|
4553 | |
---|
4554 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); |
---|
4555 | |
---|
4556 | mta |= (1 << hash_bit); |
---|
4557 | |
---|
4558 | /* If we are on an 82544 and we are trying to write an odd offset |
---|
4559 | * in the MTA, save off the previous entry before writing and |
---|
4560 | * restore the old value after writing. |
---|
4561 | */ |
---|
4562 | if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { |
---|
4563 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
---|
4564 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
---|
4565 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
---|
4566 | } else { |
---|
4567 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
---|
4568 | } |
---|
4569 | } |
---|
4570 | |
---|
4571 | /****************************************************************************** |
---|
4572 | * Puts an ethernet address into a receive address register. |
---|
4573 | * |
---|
4574 | * hw - Struct containing variables accessed by shared code |
---|
4575 | * addr - Address to put into receive address register |
---|
4576 | * index - Receive address register to write |
---|
4577 | *****************************************************************************/ |
---|
4578 | void |
---|
4579 | em_rar_set(struct em_hw *hw, |
---|
4580 | uint8_t *addr, |
---|
4581 | uint32_t index) |
---|
4582 | { |
---|
4583 | uint32_t rar_low, rar_high; |
---|
4584 | |
---|
4585 | /* HW expects these in little endian so we reverse the byte order |
---|
4586 | * from network order (big endian) to little endian |
---|
4587 | */ |
---|
4588 | rar_low = ((uint32_t) addr[0] | |
---|
4589 | ((uint32_t) addr[1] << 8) | |
---|
4590 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); |
---|
4591 | |
---|
4592 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV); |
---|
4593 | |
---|
4594 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
---|
4595 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
---|
4596 | } |
---|
4597 | |
---|
4598 | /****************************************************************************** |
---|
4599 | * Writes a value to the specified offset in the VLAN filter table. |
---|
4600 | * |
---|
4601 | * hw - Struct containing variables accessed by shared code |
---|
4602 | * offset - Offset in VLAN filer table to write |
---|
4603 | * value - Value to write into VLAN filter table |
---|
4604 | *****************************************************************************/ |
---|
4605 | void |
---|
4606 | em_write_vfta(struct em_hw *hw, |
---|
4607 | uint32_t offset, |
---|
4608 | uint32_t value) |
---|
4609 | { |
---|
4610 | uint32_t temp; |
---|
4611 | |
---|
4612 | if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) { |
---|
4613 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
---|
4614 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
---|
4615 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
---|
4616 | } else { |
---|
4617 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
---|
4618 | } |
---|
4619 | } |
---|
4620 | |
---|
4621 | /****************************************************************************** |
---|
4622 | * Clears the VLAN filer table |
---|
4623 | * |
---|
4624 | * hw - Struct containing variables accessed by shared code |
---|
4625 | *****************************************************************************/ |
---|
4626 | void |
---|
4627 | em_clear_vfta(struct em_hw *hw) |
---|
4628 | { |
---|
4629 | uint32_t offset; |
---|
4630 | uint32_t vfta_value = 0; |
---|
4631 | uint32_t vfta_offset = 0; |
---|
4632 | uint32_t vfta_bit_in_reg = 0; |
---|
4633 | |
---|
4634 | if (hw->mac_type == em_82573) { |
---|
4635 | if (hw->mng_cookie.vlan_id != 0) { |
---|
4636 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN |
---|
4637 | * ID. The following operations determine which 32b entry |
---|
4638 | * (i.e. offset) into the array we want to set the VLAN ID |
---|
4639 | * (i.e. bit) of the manageability unit. */ |
---|
4640 | vfta_offset = (hw->mng_cookie.vlan_id >> |
---|
4641 | E1000_VFTA_ENTRY_SHIFT) & |
---|
4642 | E1000_VFTA_ENTRY_MASK; |
---|
4643 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
---|
4644 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
---|
4645 | } |
---|
4646 | } |
---|
4647 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
---|
4648 | /* If the offset we want to clear is the same offset of the |
---|
4649 | * manageability VLAN ID, then clear all bits except that of the |
---|
4650 | * manageability unit */ |
---|
4651 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
---|
4652 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
---|
4653 | } |
---|
4654 | } |
---|
4655 | |
---|
4656 | int32_t |
---|
4657 | em_id_led_init(struct em_hw * hw) |
---|
4658 | { |
---|
4659 | uint32_t ledctl; |
---|
4660 | const uint32_t ledctl_mask = 0x000000FF; |
---|
4661 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
---|
4662 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
---|
4663 | uint16_t eeprom_data, i, temp; |
---|
4664 | const uint16_t led_mask = 0x0F; |
---|
4665 | |
---|
4666 | DEBUGFUNC("em_id_led_init"); |
---|
4667 | |
---|
4668 | if(hw->mac_type < em_82540) { |
---|
4669 | /* Nothing to do */ |
---|
4670 | return E1000_SUCCESS; |
---|
4671 | } |
---|
4672 | |
---|
4673 | ledctl = E1000_READ_REG(hw, LEDCTL); |
---|
4674 | hw->ledctl_default = ledctl; |
---|
4675 | hw->ledctl_mode1 = hw->ledctl_default; |
---|
4676 | hw->ledctl_mode2 = hw->ledctl_default; |
---|
4677 | |
---|
4678 | if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
---|
4679 | DEBUGOUT("EEPROM Read Error\n"); |
---|
4680 | return -E1000_ERR_EEPROM; |
---|
4681 | } |
---|
4682 | if((eeprom_data== ID_LED_RESERVED_0000) || |
---|
4683 | (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; |
---|
4684 | for(i = 0; i < 4; i++) { |
---|
4685 | temp = (eeprom_data >> (i << 2)) & led_mask; |
---|
4686 | switch(temp) { |
---|
4687 | case ID_LED_ON1_DEF2: |
---|
4688 | case ID_LED_ON1_ON2: |
---|
4689 | case ID_LED_ON1_OFF2: |
---|
4690 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
---|
4691 | hw->ledctl_mode1 |= ledctl_on << (i << 3); |
---|
4692 | break; |
---|
4693 | case ID_LED_OFF1_DEF2: |
---|
4694 | case ID_LED_OFF1_ON2: |
---|
4695 | case ID_LED_OFF1_OFF2: |
---|
4696 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
---|
4697 | hw->ledctl_mode1 |= ledctl_off << (i << 3); |
---|
4698 | break; |
---|
4699 | default: |
---|
4700 | /* Do nothing */ |
---|
4701 | break; |
---|
4702 | } |
---|
4703 | switch(temp) { |
---|
4704 | case ID_LED_DEF1_ON2: |
---|
4705 | case ID_LED_ON1_ON2: |
---|
4706 | case ID_LED_OFF1_ON2: |
---|
4707 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
---|
4708 | hw->ledctl_mode2 |= ledctl_on << (i << 3); |
---|
4709 | break; |
---|
4710 | case ID_LED_DEF1_OFF2: |
---|
4711 | case ID_LED_ON1_OFF2: |
---|
4712 | case ID_LED_OFF1_OFF2: |
---|
4713 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
---|
4714 | hw->ledctl_mode2 |= ledctl_off << (i << 3); |
---|
4715 | break; |
---|
4716 | default: |
---|
4717 | /* Do nothing */ |
---|
4718 | break; |
---|
4719 | } |
---|
4720 | } |
---|
4721 | return E1000_SUCCESS; |
---|
4722 | } |
---|
4723 | |
---|
4724 | /****************************************************************************** |
---|
4725 | * Prepares SW controlable LED for use and saves the current state of the LED. |
---|
4726 | * |
---|
4727 | * hw - Struct containing variables accessed by shared code |
---|
4728 | *****************************************************************************/ |
---|
4729 | int32_t |
---|
4730 | em_setup_led(struct em_hw *hw) |
---|
4731 | { |
---|
4732 | uint32_t ledctl; |
---|
4733 | int32_t ret_val = E1000_SUCCESS; |
---|
4734 | |
---|
4735 | DEBUGFUNC("em_setup_led"); |
---|
4736 | |
---|
4737 | switch(hw->mac_type) { |
---|
4738 | case em_82542_rev2_0: |
---|
4739 | case em_82542_rev2_1: |
---|
4740 | case em_82543: |
---|
4741 | case em_82544: |
---|
4742 | /* No setup necessary */ |
---|
4743 | break; |
---|
4744 | case em_82541: |
---|
4745 | case em_82547: |
---|
4746 | case em_82541_rev_2: |
---|
4747 | case em_82547_rev_2: |
---|
4748 | /* Turn off PHY Smart Power Down (if enabled) */ |
---|
4749 | ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
---|
4750 | &hw->phy_spd_default); |
---|
4751 | if(ret_val) |
---|
4752 | return ret_val; |
---|
4753 | ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
---|
4754 | (uint16_t)(hw->phy_spd_default & |
---|
4755 | ~IGP01E1000_GMII_SPD)); |
---|
4756 | if(ret_val) |
---|
4757 | return ret_val; |
---|
4758 | /* Fall Through */ |
---|
4759 | default: |
---|
4760 | if(hw->media_type == em_media_type_fiber) { |
---|
4761 | ledctl = E1000_READ_REG(hw, LEDCTL); |
---|
4762 | /* Save current LEDCTL settings */ |
---|
4763 | hw->ledctl_default = ledctl; |
---|
4764 | /* Turn off LED0 */ |
---|
4765 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
---|
4766 | E1000_LEDCTL_LED0_BLINK | |
---|
4767 | E1000_LEDCTL_LED0_MODE_MASK); |
---|
4768 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
---|
4769 | E1000_LEDCTL_LED0_MODE_SHIFT); |
---|
4770 | E1000_WRITE_REG(hw, LEDCTL, ledctl); |
---|
4771 | } else if(hw->media_type == em_media_type_copper) |
---|
4772 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
---|
4773 | break; |
---|
4774 | } |
---|
4775 | |
---|
4776 | return E1000_SUCCESS; |
---|
4777 | } |
---|
4778 | |
---|
4779 | /****************************************************************************** |
---|
4780 | * Restores the saved state of the SW controlable LED. |
---|
4781 | * |
---|
4782 | * hw - Struct containing variables accessed by shared code |
---|
4783 | *****************************************************************************/ |
---|
4784 | int32_t |
---|
4785 | em_cleanup_led(struct em_hw *hw) |
---|
4786 | { |
---|
4787 | int32_t ret_val = E1000_SUCCESS; |
---|
4788 | |
---|
4789 | DEBUGFUNC("em_cleanup_led"); |
---|
4790 | |
---|
4791 | switch(hw->mac_type) { |
---|
4792 | case em_82542_rev2_0: |
---|
4793 | case em_82542_rev2_1: |
---|
4794 | case em_82543: |
---|
4795 | case em_82544: |
---|
4796 | /* No cleanup necessary */ |
---|
4797 | break; |
---|
4798 | case em_82541: |
---|
4799 | case em_82547: |
---|
4800 | case em_82541_rev_2: |
---|
4801 | case em_82547_rev_2: |
---|
4802 | /* Turn on PHY Smart Power Down (if previously enabled) */ |
---|
4803 | ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
---|
4804 | hw->phy_spd_default); |
---|
4805 | if(ret_val) |
---|
4806 | return ret_val; |
---|
4807 | /* Fall Through */ |
---|
4808 | default: |
---|
4809 | /* Restore LEDCTL settings */ |
---|
4810 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); |
---|
4811 | break; |
---|
4812 | } |
---|
4813 | |
---|
4814 | return E1000_SUCCESS; |
---|
4815 | } |
---|
4816 | |
---|
4817 | /****************************************************************************** |
---|
4818 | * Turns on the software controllable LED |
---|
4819 | * |
---|
4820 | * hw - Struct containing variables accessed by shared code |
---|
4821 | *****************************************************************************/ |
---|
4822 | int32_t |
---|
4823 | em_led_on(struct em_hw *hw) |
---|
4824 | { |
---|
4825 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
---|
4826 | |
---|
4827 | DEBUGFUNC("em_led_on"); |
---|
4828 | |
---|
4829 | switch(hw->mac_type) { |
---|
4830 | case em_82542_rev2_0: |
---|
4831 | case em_82542_rev2_1: |
---|
4832 | case em_82543: |
---|
4833 | /* Set SW Defineable Pin 0 to turn on the LED */ |
---|
4834 | ctrl |= E1000_CTRL_SWDPIN0; |
---|
4835 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4836 | break; |
---|
4837 | case em_82544: |
---|
4838 | if(hw->media_type == em_media_type_fiber) { |
---|
4839 | /* Set SW Defineable Pin 0 to turn on the LED */ |
---|
4840 | ctrl |= E1000_CTRL_SWDPIN0; |
---|
4841 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4842 | } else { |
---|
4843 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
---|
4844 | ctrl &= ~E1000_CTRL_SWDPIN0; |
---|
4845 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4846 | } |
---|
4847 | break; |
---|
4848 | default: |
---|
4849 | if(hw->media_type == em_media_type_fiber) { |
---|
4850 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
---|
4851 | ctrl &= ~E1000_CTRL_SWDPIN0; |
---|
4852 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4853 | } else if(hw->media_type == em_media_type_copper) { |
---|
4854 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
---|
4855 | return E1000_SUCCESS; |
---|
4856 | } |
---|
4857 | break; |
---|
4858 | } |
---|
4859 | |
---|
4860 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
4861 | |
---|
4862 | return E1000_SUCCESS; |
---|
4863 | } |
---|
4864 | |
---|
4865 | /****************************************************************************** |
---|
4866 | * Turns off the software controllable LED |
---|
4867 | * |
---|
4868 | * hw - Struct containing variables accessed by shared code |
---|
4869 | *****************************************************************************/ |
---|
4870 | int32_t |
---|
4871 | em_led_off(struct em_hw *hw) |
---|
4872 | { |
---|
4873 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
---|
4874 | |
---|
4875 | DEBUGFUNC("em_led_off"); |
---|
4876 | |
---|
4877 | switch(hw->mac_type) { |
---|
4878 | case em_82542_rev2_0: |
---|
4879 | case em_82542_rev2_1: |
---|
4880 | case em_82543: |
---|
4881 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
---|
4882 | ctrl &= ~E1000_CTRL_SWDPIN0; |
---|
4883 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4884 | break; |
---|
4885 | case em_82544: |
---|
4886 | if(hw->media_type == em_media_type_fiber) { |
---|
4887 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
---|
4888 | ctrl &= ~E1000_CTRL_SWDPIN0; |
---|
4889 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4890 | } else { |
---|
4891 | /* Set SW Defineable Pin 0 to turn off the LED */ |
---|
4892 | ctrl |= E1000_CTRL_SWDPIN0; |
---|
4893 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4894 | } |
---|
4895 | break; |
---|
4896 | default: |
---|
4897 | if(hw->media_type == em_media_type_fiber) { |
---|
4898 | /* Set SW Defineable Pin 0 to turn off the LED */ |
---|
4899 | ctrl |= E1000_CTRL_SWDPIN0; |
---|
4900 | ctrl |= E1000_CTRL_SWDPIO0; |
---|
4901 | } else if(hw->media_type == em_media_type_copper) { |
---|
4902 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
---|
4903 | return E1000_SUCCESS; |
---|
4904 | } |
---|
4905 | break; |
---|
4906 | } |
---|
4907 | |
---|
4908 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
4909 | |
---|
4910 | return E1000_SUCCESS; |
---|
4911 | } |
---|
4912 | |
---|
4913 | /****************************************************************************** |
---|
4914 | * Clears all hardware statistics counters. |
---|
4915 | * |
---|
4916 | * hw - Struct containing variables accessed by shared code |
---|
4917 | *****************************************************************************/ |
---|
4918 | void |
---|
4919 | em_clear_hw_cntrs(struct em_hw *hw) |
---|
4920 | { |
---|
4921 | volatile uint32_t temp; |
---|
4922 | |
---|
4923 | temp = E1000_READ_REG(hw, CRCERRS); |
---|
4924 | temp = E1000_READ_REG(hw, SYMERRS); |
---|
4925 | temp = E1000_READ_REG(hw, MPC); |
---|
4926 | temp = E1000_READ_REG(hw, SCC); |
---|
4927 | temp = E1000_READ_REG(hw, ECOL); |
---|
4928 | temp = E1000_READ_REG(hw, MCC); |
---|
4929 | temp = E1000_READ_REG(hw, LATECOL); |
---|
4930 | temp = E1000_READ_REG(hw, COLC); |
---|
4931 | temp = E1000_READ_REG(hw, DC); |
---|
4932 | temp = E1000_READ_REG(hw, SEC); |
---|
4933 | temp = E1000_READ_REG(hw, RLEC); |
---|
4934 | temp = E1000_READ_REG(hw, XONRXC); |
---|
4935 | temp = E1000_READ_REG(hw, XONTXC); |
---|
4936 | temp = E1000_READ_REG(hw, XOFFRXC); |
---|
4937 | temp = E1000_READ_REG(hw, XOFFTXC); |
---|
4938 | temp = E1000_READ_REG(hw, FCRUC); |
---|
4939 | temp = E1000_READ_REG(hw, PRC64); |
---|
4940 | temp = E1000_READ_REG(hw, PRC127); |
---|
4941 | temp = E1000_READ_REG(hw, PRC255); |
---|
4942 | temp = E1000_READ_REG(hw, PRC511); |
---|
4943 | temp = E1000_READ_REG(hw, PRC1023); |
---|
4944 | temp = E1000_READ_REG(hw, PRC1522); |
---|
4945 | temp = E1000_READ_REG(hw, GPRC); |
---|
4946 | temp = E1000_READ_REG(hw, BPRC); |
---|
4947 | temp = E1000_READ_REG(hw, MPRC); |
---|
4948 | temp = E1000_READ_REG(hw, GPTC); |
---|
4949 | temp = E1000_READ_REG(hw, GORCL); |
---|
4950 | temp = E1000_READ_REG(hw, GORCH); |
---|
4951 | temp = E1000_READ_REG(hw, GOTCL); |
---|
4952 | temp = E1000_READ_REG(hw, GOTCH); |
---|
4953 | temp = E1000_READ_REG(hw, RNBC); |
---|
4954 | temp = E1000_READ_REG(hw, RUC); |
---|
4955 | temp = E1000_READ_REG(hw, RFC); |
---|
4956 | temp = E1000_READ_REG(hw, ROC); |
---|
4957 | temp = E1000_READ_REG(hw, RJC); |
---|
4958 | temp = E1000_READ_REG(hw, TORL); |
---|
4959 | temp = E1000_READ_REG(hw, TORH); |
---|
4960 | temp = E1000_READ_REG(hw, TOTL); |
---|
4961 | temp = E1000_READ_REG(hw, TOTH); |
---|
4962 | temp = E1000_READ_REG(hw, TPR); |
---|
4963 | temp = E1000_READ_REG(hw, TPT); |
---|
4964 | temp = E1000_READ_REG(hw, PTC64); |
---|
4965 | temp = E1000_READ_REG(hw, PTC127); |
---|
4966 | temp = E1000_READ_REG(hw, PTC255); |
---|
4967 | temp = E1000_READ_REG(hw, PTC511); |
---|
4968 | temp = E1000_READ_REG(hw, PTC1023); |
---|
4969 | temp = E1000_READ_REG(hw, PTC1522); |
---|
4970 | temp = E1000_READ_REG(hw, MPTC); |
---|
4971 | temp = E1000_READ_REG(hw, BPTC); |
---|
4972 | |
---|
4973 | if(hw->mac_type < em_82543) return; |
---|
4974 | |
---|
4975 | temp = E1000_READ_REG(hw, ALGNERRC); |
---|
4976 | temp = E1000_READ_REG(hw, RXERRC); |
---|
4977 | temp = E1000_READ_REG(hw, TNCRS); |
---|
4978 | temp = E1000_READ_REG(hw, CEXTERR); |
---|
4979 | temp = E1000_READ_REG(hw, TSCTC); |
---|
4980 | temp = E1000_READ_REG(hw, TSCTFC); |
---|
4981 | |
---|
4982 | if(hw->mac_type <= em_82544) return; |
---|
4983 | |
---|
4984 | temp = E1000_READ_REG(hw, MGTPRC); |
---|
4985 | temp = E1000_READ_REG(hw, MGTPDC); |
---|
4986 | temp = E1000_READ_REG(hw, MGTPTC); |
---|
4987 | |
---|
4988 | if(hw->mac_type <= em_82547_rev_2) return; |
---|
4989 | |
---|
4990 | temp = E1000_READ_REG(hw, IAC); |
---|
4991 | temp = E1000_READ_REG(hw, ICRXOC); |
---|
4992 | temp = E1000_READ_REG(hw, ICRXPTC); |
---|
4993 | temp = E1000_READ_REG(hw, ICRXATC); |
---|
4994 | temp = E1000_READ_REG(hw, ICTXPTC); |
---|
4995 | temp = E1000_READ_REG(hw, ICTXATC); |
---|
4996 | temp = E1000_READ_REG(hw, ICTXQEC); |
---|
4997 | temp = E1000_READ_REG(hw, ICTXQMTC); |
---|
4998 | temp = E1000_READ_REG(hw, ICRXDMTC); |
---|
4999 | |
---|
5000 | } |
---|
5001 | |
---|
5002 | /****************************************************************************** |
---|
5003 | * Resets Adaptive IFS to its default state. |
---|
5004 | * |
---|
5005 | * hw - Struct containing variables accessed by shared code |
---|
5006 | * |
---|
5007 | * Call this after em_init_hw. You may override the IFS defaults by setting |
---|
5008 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> |
---|
5009 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
---|
5010 | * before calling this function. |
---|
5011 | *****************************************************************************/ |
---|
5012 | void |
---|
5013 | em_reset_adaptive(struct em_hw *hw) |
---|
5014 | { |
---|
5015 | DEBUGFUNC("em_reset_adaptive"); |
---|
5016 | |
---|
5017 | if(hw->adaptive_ifs) { |
---|
5018 | if(!hw->ifs_params_forced) { |
---|
5019 | hw->current_ifs_val = 0; |
---|
5020 | hw->ifs_min_val = IFS_MIN; |
---|
5021 | hw->ifs_max_val = IFS_MAX; |
---|
5022 | hw->ifs_step_size = IFS_STEP; |
---|
5023 | hw->ifs_ratio = IFS_RATIO; |
---|
5024 | } |
---|
5025 | hw->in_ifs_mode = FALSE; |
---|
5026 | E1000_WRITE_REG(hw, AIT, 0); |
---|
5027 | } else { |
---|
5028 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
---|
5029 | } |
---|
5030 | } |
---|
5031 | |
---|
5032 | /****************************************************************************** |
---|
5033 | * Called during the callback/watchdog routine to update IFS value based on |
---|
5034 | * the ratio of transmits to collisions. |
---|
5035 | * |
---|
5036 | * hw - Struct containing variables accessed by shared code |
---|
5037 | * tx_packets - Number of transmits since last callback |
---|
5038 | * total_collisions - Number of collisions since last callback |
---|
5039 | *****************************************************************************/ |
---|
5040 | void |
---|
5041 | em_update_adaptive(struct em_hw *hw) |
---|
5042 | { |
---|
5043 | DEBUGFUNC("em_update_adaptive"); |
---|
5044 | |
---|
5045 | if(hw->adaptive_ifs) { |
---|
5046 | if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { |
---|
5047 | if(hw->tx_packet_delta > MIN_NUM_XMITS) { |
---|
5048 | hw->in_ifs_mode = TRUE; |
---|
5049 | if(hw->current_ifs_val < hw->ifs_max_val) { |
---|
5050 | if(hw->current_ifs_val == 0) |
---|
5051 | hw->current_ifs_val = hw->ifs_min_val; |
---|
5052 | else |
---|
5053 | hw->current_ifs_val += hw->ifs_step_size; |
---|
5054 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); |
---|
5055 | } |
---|
5056 | } |
---|
5057 | } else { |
---|
5058 | if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
---|
5059 | hw->current_ifs_val = 0; |
---|
5060 | hw->in_ifs_mode = FALSE; |
---|
5061 | E1000_WRITE_REG(hw, AIT, 0); |
---|
5062 | } |
---|
5063 | } |
---|
5064 | } else { |
---|
5065 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
---|
5066 | } |
---|
5067 | } |
---|
5068 | |
---|
5069 | /****************************************************************************** |
---|
5070 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
---|
5071 | * |
---|
5072 | * hw - Struct containing variables accessed by shared code |
---|
5073 | * frame_len - The length of the frame in question |
---|
5074 | * mac_addr - The Ethernet destination address of the frame in question |
---|
5075 | *****************************************************************************/ |
---|
5076 | void |
---|
5077 | em_tbi_adjust_stats(struct em_hw *hw, |
---|
5078 | struct em_hw_stats *stats, |
---|
5079 | uint32_t frame_len, |
---|
5080 | uint8_t *mac_addr) |
---|
5081 | { |
---|
5082 | uint64_t carry_bit; |
---|
5083 | |
---|
5084 | /* First adjust the frame length. */ |
---|
5085 | frame_len--; |
---|
5086 | /* We need to adjust the statistics counters, since the hardware |
---|
5087 | * counters overcount this packet as a CRC error and undercount |
---|
5088 | * the packet as a good packet |
---|
5089 | */ |
---|
5090 | /* This packet should not be counted as a CRC error. */ |
---|
5091 | stats->crcerrs--; |
---|
5092 | /* This packet does count as a Good Packet Received. */ |
---|
5093 | stats->gprc++; |
---|
5094 | |
---|
5095 | /* Adjust the Good Octets received counters */ |
---|
5096 | carry_bit = 0x80000000 & stats->gorcl; |
---|
5097 | stats->gorcl += frame_len; |
---|
5098 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
---|
5099 | * Received Count) was one before the addition, |
---|
5100 | * AND it is zero after, then we lost the carry out, |
---|
5101 | * need to add one to Gorch (Good Octets Received Count High). |
---|
5102 | * This could be simplified if all environments supported |
---|
5103 | * 64-bit integers. |
---|
5104 | */ |
---|
5105 | if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
---|
5106 | stats->gorch++; |
---|
5107 | /* Is this a broadcast or multicast? Check broadcast first, |
---|
5108 | * since the test for a multicast frame will test positive on |
---|
5109 | * a broadcast frame. |
---|
5110 | */ |
---|
5111 | if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
---|
5112 | /* Broadcast packet */ |
---|
5113 | stats->bprc++; |
---|
5114 | else if(*mac_addr & 0x01) |
---|
5115 | /* Multicast packet */ |
---|
5116 | stats->mprc++; |
---|
5117 | |
---|
5118 | if(frame_len == hw->max_frame_size) { |
---|
5119 | /* In this case, the hardware has overcounted the number of |
---|
5120 | * oversize frames. |
---|
5121 | */ |
---|
5122 | if(stats->roc > 0) |
---|
5123 | stats->roc--; |
---|
5124 | } |
---|
5125 | |
---|
5126 | /* Adjust the bin counters when the extra byte put the frame in the |
---|
5127 | * wrong bin. Remember that the frame_len was adjusted above. |
---|
5128 | */ |
---|
5129 | if(frame_len == 64) { |
---|
5130 | stats->prc64++; |
---|
5131 | stats->prc127--; |
---|
5132 | } else if(frame_len == 127) { |
---|
5133 | stats->prc127++; |
---|
5134 | stats->prc255--; |
---|
5135 | } else if(frame_len == 255) { |
---|
5136 | stats->prc255++; |
---|
5137 | stats->prc511--; |
---|
5138 | } else if(frame_len == 511) { |
---|
5139 | stats->prc511++; |
---|
5140 | stats->prc1023--; |
---|
5141 | } else if(frame_len == 1023) { |
---|
5142 | stats->prc1023++; |
---|
5143 | stats->prc1522--; |
---|
5144 | } else if(frame_len == 1522) { |
---|
5145 | stats->prc1522++; |
---|
5146 | } |
---|
5147 | } |
---|
5148 | |
---|
5149 | /****************************************************************************** |
---|
5150 | * Gets the current PCI bus type, speed, and width of the hardware |
---|
5151 | * |
---|
5152 | * hw - Struct containing variables accessed by shared code |
---|
5153 | *****************************************************************************/ |
---|
5154 | void |
---|
5155 | em_get_bus_info(struct em_hw *hw) |
---|
5156 | { |
---|
5157 | uint32_t status; |
---|
5158 | |
---|
5159 | switch (hw->mac_type) { |
---|
5160 | case em_82542_rev2_0: |
---|
5161 | case em_82542_rev2_1: |
---|
5162 | hw->bus_type = em_bus_type_unknown; |
---|
5163 | hw->bus_speed = em_bus_speed_unknown; |
---|
5164 | hw->bus_width = em_bus_width_unknown; |
---|
5165 | break; |
---|
5166 | case em_82573: |
---|
5167 | hw->bus_type = em_bus_type_pci_express; |
---|
5168 | hw->bus_speed = em_bus_speed_2500; |
---|
5169 | hw->bus_width = em_bus_width_pciex_4; |
---|
5170 | break; |
---|
5171 | default: |
---|
5172 | status = E1000_READ_REG(hw, STATUS); |
---|
5173 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
---|
5174 | em_bus_type_pcix : em_bus_type_pci; |
---|
5175 | |
---|
5176 | if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
---|
5177 | hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? |
---|
5178 | em_bus_speed_66 : em_bus_speed_120; |
---|
5179 | } else if(hw->bus_type == em_bus_type_pci) { |
---|
5180 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
---|
5181 | em_bus_speed_66 : em_bus_speed_33; |
---|
5182 | } else { |
---|
5183 | switch (status & E1000_STATUS_PCIX_SPEED) { |
---|
5184 | case E1000_STATUS_PCIX_SPEED_66: |
---|
5185 | hw->bus_speed = em_bus_speed_66; |
---|
5186 | break; |
---|
5187 | case E1000_STATUS_PCIX_SPEED_100: |
---|
5188 | hw->bus_speed = em_bus_speed_100; |
---|
5189 | break; |
---|
5190 | case E1000_STATUS_PCIX_SPEED_133: |
---|
5191 | hw->bus_speed = em_bus_speed_133; |
---|
5192 | break; |
---|
5193 | default: |
---|
5194 | hw->bus_speed = em_bus_speed_reserved; |
---|
5195 | break; |
---|
5196 | } |
---|
5197 | } |
---|
5198 | hw->bus_width = (status & E1000_STATUS_BUS64) ? |
---|
5199 | em_bus_width_64 : em_bus_width_32; |
---|
5200 | break; |
---|
5201 | } |
---|
5202 | } |
---|
5203 | /****************************************************************************** |
---|
5204 | * Reads a value from one of the devices registers using port I/O (as opposed |
---|
5205 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
---|
5206 | * |
---|
5207 | * hw - Struct containing variables accessed by shared code |
---|
5208 | * offset - offset to read from |
---|
5209 | *****************************************************************************/ |
---|
5210 | uint32_t |
---|
5211 | em_read_reg_io(struct em_hw *hw, |
---|
5212 | uint32_t offset) |
---|
5213 | { |
---|
5214 | unsigned long io_addr = hw->io_base; |
---|
5215 | unsigned long io_data = hw->io_base + 4; |
---|
5216 | |
---|
5217 | em_io_write(hw, io_addr, offset); |
---|
5218 | return em_io_read(hw, io_data); |
---|
5219 | } |
---|
5220 | |
---|
5221 | /****************************************************************************** |
---|
5222 | * Writes a value to one of the devices registers using port I/O (as opposed to |
---|
5223 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
---|
5224 | * |
---|
5225 | * hw - Struct containing variables accessed by shared code |
---|
5226 | * offset - offset to write to |
---|
5227 | * value - value to write |
---|
5228 | *****************************************************************************/ |
---|
5229 | void |
---|
5230 | em_write_reg_io(struct em_hw *hw, |
---|
5231 | uint32_t offset, |
---|
5232 | uint32_t value) |
---|
5233 | { |
---|
5234 | unsigned long io_addr = hw->io_base; |
---|
5235 | unsigned long io_data = hw->io_base + 4; |
---|
5236 | |
---|
5237 | em_io_write(hw, io_addr, offset); |
---|
5238 | em_io_write(hw, io_data, value); |
---|
5239 | } |
---|
5240 | |
---|
5241 | |
---|
5242 | /****************************************************************************** |
---|
5243 | * Estimates the cable length. |
---|
5244 | * |
---|
5245 | * hw - Struct containing variables accessed by shared code |
---|
5246 | * min_length - The estimated minimum length |
---|
5247 | * max_length - The estimated maximum length |
---|
5248 | * |
---|
5249 | * returns: - E1000_ERR_XXX |
---|
5250 | * E1000_SUCCESS |
---|
5251 | * |
---|
5252 | * This function always returns a ranged length (minimum & maximum). |
---|
5253 | * So for M88 phy's, this function interprets the one value returned from the |
---|
5254 | * register to the minimum and maximum range. |
---|
5255 | * For IGP phy's, the function calculates the range by the AGC registers. |
---|
5256 | *****************************************************************************/ |
---|
5257 | int32_t |
---|
5258 | em_get_cable_length(struct em_hw *hw, |
---|
5259 | uint16_t *min_length, |
---|
5260 | uint16_t *max_length) |
---|
5261 | { |
---|
5262 | int32_t ret_val; |
---|
5263 | uint16_t agc_value = 0; |
---|
5264 | uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
---|
5265 | uint16_t i, phy_data; |
---|
5266 | uint16_t cable_length; |
---|
5267 | |
---|
5268 | DEBUGFUNC("em_get_cable_length"); |
---|
5269 | |
---|
5270 | *min_length = *max_length = 0; |
---|
5271 | |
---|
5272 | /* Use old method for Phy older than IGP */ |
---|
5273 | if(hw->phy_type == em_phy_m88) { |
---|
5274 | |
---|
5275 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
---|
5276 | &phy_data); |
---|
5277 | if(ret_val) |
---|
5278 | return ret_val; |
---|
5279 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
---|
5280 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
---|
5281 | |
---|
5282 | /* Convert the enum value to ranged values */ |
---|
5283 | switch (cable_length) { |
---|
5284 | case em_cable_length_50: |
---|
5285 | *min_length = 0; |
---|
5286 | *max_length = em_igp_cable_length_50; |
---|
5287 | break; |
---|
5288 | case em_cable_length_50_80: |
---|
5289 | *min_length = em_igp_cable_length_50; |
---|
5290 | *max_length = em_igp_cable_length_80; |
---|
5291 | break; |
---|
5292 | case em_cable_length_80_110: |
---|
5293 | *min_length = em_igp_cable_length_80; |
---|
5294 | *max_length = em_igp_cable_length_110; |
---|
5295 | break; |
---|
5296 | case em_cable_length_110_140: |
---|
5297 | *min_length = em_igp_cable_length_110; |
---|
5298 | *max_length = em_igp_cable_length_140; |
---|
5299 | break; |
---|
5300 | case em_cable_length_140: |
---|
5301 | *min_length = em_igp_cable_length_140; |
---|
5302 | *max_length = em_igp_cable_length_170; |
---|
5303 | break; |
---|
5304 | default: |
---|
5305 | return -E1000_ERR_PHY; |
---|
5306 | break; |
---|
5307 | } |
---|
5308 | } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */ |
---|
5309 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
---|
5310 | {IGP01E1000_PHY_AGC_A, |
---|
5311 | IGP01E1000_PHY_AGC_B, |
---|
5312 | IGP01E1000_PHY_AGC_C, |
---|
5313 | IGP01E1000_PHY_AGC_D}; |
---|
5314 | /* Read the AGC registers for all channels */ |
---|
5315 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
---|
5316 | |
---|
5317 | ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
---|
5318 | if(ret_val) |
---|
5319 | return ret_val; |
---|
5320 | |
---|
5321 | cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
---|
5322 | |
---|
5323 | /* Array bound check. */ |
---|
5324 | if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || |
---|
5325 | (cur_agc == 0)) |
---|
5326 | return -E1000_ERR_PHY; |
---|
5327 | |
---|
5328 | agc_value += cur_agc; |
---|
5329 | |
---|
5330 | /* Update minimal AGC value. */ |
---|
5331 | if(min_agc > cur_agc) |
---|
5332 | min_agc = cur_agc; |
---|
5333 | } |
---|
5334 | |
---|
5335 | /* Remove the minimal AGC result for length < 50m */ |
---|
5336 | if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) { |
---|
5337 | agc_value -= min_agc; |
---|
5338 | |
---|
5339 | /* Get the average length of the remaining 3 channels */ |
---|
5340 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
---|
5341 | } else { |
---|
5342 | /* Get the average length of all the 4 channels. */ |
---|
5343 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
---|
5344 | } |
---|
5345 | |
---|
5346 | /* Set the range of the calculated length. */ |
---|
5347 | *min_length = ((em_igp_cable_length_table[agc_value] - |
---|
5348 | IGP01E1000_AGC_RANGE) > 0) ? |
---|
5349 | (em_igp_cable_length_table[agc_value] - |
---|
5350 | IGP01E1000_AGC_RANGE) : 0; |
---|
5351 | *max_length = em_igp_cable_length_table[agc_value] + |
---|
5352 | IGP01E1000_AGC_RANGE; |
---|
5353 | } |
---|
5354 | |
---|
5355 | return E1000_SUCCESS; |
---|
5356 | } |
---|
5357 | |
---|
5358 | /****************************************************************************** |
---|
5359 | * Check the cable polarity |
---|
5360 | * |
---|
5361 | * hw - Struct containing variables accessed by shared code |
---|
5362 | * polarity - output parameter : 0 - Polarity is not reversed |
---|
5363 | * 1 - Polarity is reversed. |
---|
5364 | * |
---|
5365 | * returns: - E1000_ERR_XXX |
---|
5366 | * E1000_SUCCESS |
---|
5367 | * |
---|
5368 | * For phy's older then IGP, this function simply reads the polarity bit in the |
---|
5369 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
---|
5370 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
---|
5371 | * return 0. If the link speed is 1000 Mbps the polarity status is in the |
---|
5372 | * IGP01E1000_PHY_PCS_INIT_REG. |
---|
5373 | *****************************************************************************/ |
---|
5374 | int32_t |
---|
5375 | em_check_polarity(struct em_hw *hw, |
---|
5376 | uint16_t *polarity) |
---|
5377 | { |
---|
5378 | int32_t ret_val; |
---|
5379 | uint16_t phy_data; |
---|
5380 | #ifdef __rtems__ |
---|
5381 | *polarity = 0; /* keep compiler happy */ |
---|
5382 | #endif |
---|
5383 | |
---|
5384 | DEBUGFUNC("em_check_polarity"); |
---|
5385 | |
---|
5386 | if(hw->phy_type == em_phy_m88) { |
---|
5387 | /* return the Polarity bit in the Status register. */ |
---|
5388 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
---|
5389 | &phy_data); |
---|
5390 | if(ret_val) |
---|
5391 | return ret_val; |
---|
5392 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> |
---|
5393 | M88E1000_PSSR_REV_POLARITY_SHIFT; |
---|
5394 | } else if(hw->phy_type == em_phy_igp || |
---|
5395 | hw->phy_type == em_phy_igp_2) { |
---|
5396 | /* Read the Status register to check the speed */ |
---|
5397 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
---|
5398 | &phy_data); |
---|
5399 | if(ret_val) |
---|
5400 | return ret_val; |
---|
5401 | |
---|
5402 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
---|
5403 | * find the polarity status */ |
---|
5404 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
---|
5405 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
---|
5406 | |
---|
5407 | /* Read the GIG initialization PCS register (0x00B4) */ |
---|
5408 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
---|
5409 | &phy_data); |
---|
5410 | if(ret_val) |
---|
5411 | return ret_val; |
---|
5412 | |
---|
5413 | /* Check the polarity bits */ |
---|
5414 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; |
---|
5415 | } else { |
---|
5416 | /* For 10 Mbps, read the polarity bit in the status register. (for |
---|
5417 | * 100 Mbps this bit is always 0) */ |
---|
5418 | *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; |
---|
5419 | } |
---|
5420 | } |
---|
5421 | return E1000_SUCCESS; |
---|
5422 | } |
---|
5423 | |
---|
5424 | /****************************************************************************** |
---|
5425 | * Check if Downshift occured |
---|
5426 | * |
---|
5427 | * hw - Struct containing variables accessed by shared code |
---|
5428 | * downshift - output parameter : 0 - No Downshift ocured. |
---|
5429 | * 1 - Downshift ocured. |
---|
5430 | * |
---|
5431 | * returns: - E1000_ERR_XXX |
---|
5432 | * E1000_SUCCESS |
---|
5433 | * |
---|
5434 | * For phy's older then IGP, this function reads the Downshift bit in the Phy |
---|
5435 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
---|
5436 | * Link Health register. In IGP this bit is latched high, so the driver must |
---|
5437 | * read it immediately after link is established. |
---|
5438 | *****************************************************************************/ |
---|
5439 | int32_t |
---|
5440 | em_check_downshift(struct em_hw *hw) |
---|
5441 | { |
---|
5442 | int32_t ret_val; |
---|
5443 | uint16_t phy_data; |
---|
5444 | |
---|
5445 | DEBUGFUNC("em_check_downshift"); |
---|
5446 | |
---|
5447 | if(hw->phy_type == em_phy_igp || |
---|
5448 | hw->phy_type == em_phy_igp_2) { |
---|
5449 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
---|
5450 | &phy_data); |
---|
5451 | if(ret_val) |
---|
5452 | return ret_val; |
---|
5453 | |
---|
5454 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
---|
5455 | } else if(hw->phy_type == em_phy_m88) { |
---|
5456 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
---|
5457 | &phy_data); |
---|
5458 | if(ret_val) |
---|
5459 | return ret_val; |
---|
5460 | |
---|
5461 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
---|
5462 | M88E1000_PSSR_DOWNSHIFT_SHIFT; |
---|
5463 | } |
---|
5464 | |
---|
5465 | return E1000_SUCCESS; |
---|
5466 | } |
---|
5467 | |
---|
5468 | /***************************************************************************** |
---|
5469 | * |
---|
5470 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
---|
5471 | * gigabit link is achieved to improve link quality. |
---|
5472 | * |
---|
5473 | * hw: Struct containing variables accessed by shared code |
---|
5474 | * |
---|
5475 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
---|
5476 | * E1000_SUCCESS at any other case. |
---|
5477 | * |
---|
5478 | ****************************************************************************/ |
---|
5479 | |
---|
5480 | int32_t |
---|
5481 | em_config_dsp_after_link_change(struct em_hw *hw, |
---|
5482 | boolean_t link_up) |
---|
5483 | { |
---|
5484 | int32_t ret_val; |
---|
5485 | uint16_t phy_data, phy_saved_data, speed, duplex, i; |
---|
5486 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
---|
5487 | {IGP01E1000_PHY_AGC_PARAM_A, |
---|
5488 | IGP01E1000_PHY_AGC_PARAM_B, |
---|
5489 | IGP01E1000_PHY_AGC_PARAM_C, |
---|
5490 | IGP01E1000_PHY_AGC_PARAM_D}; |
---|
5491 | uint16_t min_length, max_length; |
---|
5492 | |
---|
5493 | DEBUGFUNC("em_config_dsp_after_link_change"); |
---|
5494 | |
---|
5495 | if(hw->phy_type != em_phy_igp) |
---|
5496 | return E1000_SUCCESS; |
---|
5497 | |
---|
5498 | if(link_up) { |
---|
5499 | ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); |
---|
5500 | if(ret_val) { |
---|
5501 | DEBUGOUT("Error getting link speed and duplex\n"); |
---|
5502 | return ret_val; |
---|
5503 | } |
---|
5504 | |
---|
5505 | if(speed == SPEED_1000) { |
---|
5506 | |
---|
5507 | em_get_cable_length(hw, &min_length, &max_length); |
---|
5508 | |
---|
5509 | if((hw->dsp_config_state == em_dsp_config_enabled) && |
---|
5510 | min_length >= em_igp_cable_length_50) { |
---|
5511 | |
---|
5512 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
---|
5513 | ret_val = em_read_phy_reg(hw, dsp_reg_array[i], |
---|
5514 | &phy_data); |
---|
5515 | if(ret_val) |
---|
5516 | return ret_val; |
---|
5517 | |
---|
5518 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
---|
5519 | |
---|
5520 | ret_val = em_write_phy_reg(hw, dsp_reg_array[i], |
---|
5521 | phy_data); |
---|
5522 | if(ret_val) |
---|
5523 | return ret_val; |
---|
5524 | } |
---|
5525 | hw->dsp_config_state = em_dsp_config_activated; |
---|
5526 | } |
---|
5527 | |
---|
5528 | if((hw->ffe_config_state == em_ffe_config_enabled) && |
---|
5529 | (min_length < em_igp_cable_length_50)) { |
---|
5530 | |
---|
5531 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
---|
5532 | uint32_t idle_errs = 0; |
---|
5533 | |
---|
5534 | /* clear previous idle error counts */ |
---|
5535 | ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, |
---|
5536 | &phy_data); |
---|
5537 | if(ret_val) |
---|
5538 | return ret_val; |
---|
5539 | |
---|
5540 | for(i = 0; i < ffe_idle_err_timeout; i++) { |
---|
5541 | usec_delay(1000); |
---|
5542 | ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, |
---|
5543 | &phy_data); |
---|
5544 | if(ret_val) |
---|
5545 | return ret_val; |
---|
5546 | |
---|
5547 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
---|
5548 | if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
---|
5549 | hw->ffe_config_state = em_ffe_config_active; |
---|
5550 | |
---|
5551 | ret_val = em_write_phy_reg(hw, |
---|
5552 | IGP01E1000_PHY_DSP_FFE, |
---|
5553 | IGP01E1000_PHY_DSP_FFE_CM_CP); |
---|
5554 | if(ret_val) |
---|
5555 | return ret_val; |
---|
5556 | break; |
---|
5557 | } |
---|
5558 | |
---|
5559 | if(idle_errs) |
---|
5560 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
---|
5561 | } |
---|
5562 | } |
---|
5563 | } |
---|
5564 | } else { |
---|
5565 | if(hw->dsp_config_state == em_dsp_config_activated) { |
---|
5566 | /* Save off the current value of register 0x2F5B to be restored at |
---|
5567 | * the end of the routines. */ |
---|
5568 | ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
---|
5569 | |
---|
5570 | if(ret_val) |
---|
5571 | return ret_val; |
---|
5572 | |
---|
5573 | /* Disable the PHY transmitter */ |
---|
5574 | ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); |
---|
5575 | |
---|
5576 | if(ret_val) |
---|
5577 | return ret_val; |
---|
5578 | |
---|
5579 | msec_delay_irq(20); |
---|
5580 | |
---|
5581 | ret_val = em_write_phy_reg(hw, 0x0000, |
---|
5582 | IGP01E1000_IEEE_FORCE_GIGA); |
---|
5583 | if(ret_val) |
---|
5584 | return ret_val; |
---|
5585 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
---|
5586 | ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
---|
5587 | if(ret_val) |
---|
5588 | return ret_val; |
---|
5589 | |
---|
5590 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
---|
5591 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
---|
5592 | |
---|
5593 | ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data); |
---|
5594 | if(ret_val) |
---|
5595 | return ret_val; |
---|
5596 | } |
---|
5597 | |
---|
5598 | ret_val = em_write_phy_reg(hw, 0x0000, |
---|
5599 | IGP01E1000_IEEE_RESTART_AUTONEG); |
---|
5600 | if(ret_val) |
---|
5601 | return ret_val; |
---|
5602 | |
---|
5603 | msec_delay_irq(20); |
---|
5604 | |
---|
5605 | /* Now enable the transmitter */ |
---|
5606 | ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
---|
5607 | |
---|
5608 | if(ret_val) |
---|
5609 | return ret_val; |
---|
5610 | |
---|
5611 | hw->dsp_config_state = em_dsp_config_enabled; |
---|
5612 | } |
---|
5613 | |
---|
5614 | if(hw->ffe_config_state == em_ffe_config_active) { |
---|
5615 | /* Save off the current value of register 0x2F5B to be restored at |
---|
5616 | * the end of the routines. */ |
---|
5617 | ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
---|
5618 | |
---|
5619 | if(ret_val) |
---|
5620 | return ret_val; |
---|
5621 | |
---|
5622 | /* Disable the PHY transmitter */ |
---|
5623 | ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); |
---|
5624 | |
---|
5625 | if(ret_val) |
---|
5626 | return ret_val; |
---|
5627 | |
---|
5628 | msec_delay_irq(20); |
---|
5629 | |
---|
5630 | ret_val = em_write_phy_reg(hw, 0x0000, |
---|
5631 | IGP01E1000_IEEE_FORCE_GIGA); |
---|
5632 | if(ret_val) |
---|
5633 | return ret_val; |
---|
5634 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
---|
5635 | IGP01E1000_PHY_DSP_FFE_DEFAULT); |
---|
5636 | if(ret_val) |
---|
5637 | return ret_val; |
---|
5638 | |
---|
5639 | ret_val = em_write_phy_reg(hw, 0x0000, |
---|
5640 | IGP01E1000_IEEE_RESTART_AUTONEG); |
---|
5641 | if(ret_val) |
---|
5642 | return ret_val; |
---|
5643 | |
---|
5644 | msec_delay_irq(20); |
---|
5645 | |
---|
5646 | /* Now enable the transmitter */ |
---|
5647 | ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
---|
5648 | |
---|
5649 | if(ret_val) |
---|
5650 | return ret_val; |
---|
5651 | |
---|
5652 | hw->ffe_config_state = em_ffe_config_enabled; |
---|
5653 | } |
---|
5654 | } |
---|
5655 | return E1000_SUCCESS; |
---|
5656 | } |
---|
5657 | |
---|
5658 | /***************************************************************************** |
---|
5659 | * Set PHY to class A mode |
---|
5660 | * Assumes the following operations will follow to enable the new class mode. |
---|
5661 | * 1. Do a PHY soft reset |
---|
5662 | * 2. Restart auto-negotiation or force link. |
---|
5663 | * |
---|
5664 | * hw - Struct containing variables accessed by shared code |
---|
5665 | ****************************************************************************/ |
---|
5666 | static int32_t |
---|
5667 | em_set_phy_mode(struct em_hw *hw) |
---|
5668 | { |
---|
5669 | int32_t ret_val; |
---|
5670 | uint16_t eeprom_data; |
---|
5671 | |
---|
5672 | DEBUGFUNC("em_set_phy_mode"); |
---|
5673 | |
---|
5674 | if((hw->mac_type == em_82545_rev_3) && |
---|
5675 | (hw->media_type == em_media_type_copper)) { |
---|
5676 | ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
---|
5677 | if(ret_val) { |
---|
5678 | return ret_val; |
---|
5679 | } |
---|
5680 | |
---|
5681 | if((eeprom_data != EEPROM_RESERVED_WORD) && |
---|
5682 | (eeprom_data & EEPROM_PHY_CLASS_A)) { |
---|
5683 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
---|
5684 | if(ret_val) |
---|
5685 | return ret_val; |
---|
5686 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); |
---|
5687 | if(ret_val) |
---|
5688 | return ret_val; |
---|
5689 | |
---|
5690 | hw->phy_reset_disable = FALSE; |
---|
5691 | } |
---|
5692 | } |
---|
5693 | |
---|
5694 | return E1000_SUCCESS; |
---|
5695 | } |
---|
5696 | |
---|
5697 | /***************************************************************************** |
---|
5698 | * |
---|
5699 | * This function sets the lplu state according to the active flag. When |
---|
5700 | * activating lplu this function also disables smart speed and vise versa. |
---|
5701 | * lplu will not be activated unless the device autonegotiation advertisment |
---|
5702 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
---|
5703 | * hw: Struct containing variables accessed by shared code |
---|
5704 | * active - true to enable lplu false to disable lplu. |
---|
5705 | * |
---|
5706 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
---|
5707 | * E1000_SUCCESS at any other case. |
---|
5708 | * |
---|
5709 | ****************************************************************************/ |
---|
5710 | |
---|
5711 | int32_t |
---|
5712 | em_set_d3_lplu_state(struct em_hw *hw, |
---|
5713 | boolean_t active) |
---|
5714 | { |
---|
5715 | int32_t ret_val; |
---|
5716 | uint16_t phy_data; |
---|
5717 | DEBUGFUNC("em_set_d3_lplu_state"); |
---|
5718 | |
---|
5719 | if(hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2) |
---|
5720 | return E1000_SUCCESS; |
---|
5721 | |
---|
5722 | /* During driver activity LPLU should not be used or it will attain link |
---|
5723 | * from the lowest speeds starting from 10Mbps. The capability is used for |
---|
5724 | * Dx transitions and states */ |
---|
5725 | if(hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { |
---|
5726 | ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
---|
5727 | if(ret_val) |
---|
5728 | return ret_val; |
---|
5729 | } else { |
---|
5730 | ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
---|
5731 | if(ret_val) |
---|
5732 | return ret_val; |
---|
5733 | } |
---|
5734 | |
---|
5735 | if(!active) { |
---|
5736 | if(hw->mac_type == em_82541_rev_2 || |
---|
5737 | hw->mac_type == em_82547_rev_2) { |
---|
5738 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
---|
5739 | ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
---|
5740 | if(ret_val) |
---|
5741 | return ret_val; |
---|
5742 | } else { |
---|
5743 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
---|
5744 | ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
---|
5745 | phy_data); |
---|
5746 | if (ret_val) |
---|
5747 | return ret_val; |
---|
5748 | } |
---|
5749 | |
---|
5750 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
---|
5751 | * Dx states where the power conservation is most important. During |
---|
5752 | * driver activity we should enable SmartSpeed, so performance is |
---|
5753 | * maintained. */ |
---|
5754 | if (hw->smart_speed == em_smart_speed_on) { |
---|
5755 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5756 | &phy_data); |
---|
5757 | if(ret_val) |
---|
5758 | return ret_val; |
---|
5759 | |
---|
5760 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
---|
5761 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5762 | phy_data); |
---|
5763 | if(ret_val) |
---|
5764 | return ret_val; |
---|
5765 | } else if (hw->smart_speed == em_smart_speed_off) { |
---|
5766 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5767 | &phy_data); |
---|
5768 | if (ret_val) |
---|
5769 | return ret_val; |
---|
5770 | |
---|
5771 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
---|
5772 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5773 | phy_data); |
---|
5774 | if(ret_val) |
---|
5775 | return ret_val; |
---|
5776 | } |
---|
5777 | |
---|
5778 | } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
---|
5779 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
---|
5780 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
---|
5781 | |
---|
5782 | if(hw->mac_type == em_82541_rev_2 || |
---|
5783 | hw->mac_type == em_82547_rev_2) { |
---|
5784 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
---|
5785 | ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
---|
5786 | if(ret_val) |
---|
5787 | return ret_val; |
---|
5788 | } else { |
---|
5789 | phy_data |= IGP02E1000_PM_D3_LPLU; |
---|
5790 | ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
---|
5791 | phy_data); |
---|
5792 | if (ret_val) |
---|
5793 | return ret_val; |
---|
5794 | } |
---|
5795 | |
---|
5796 | /* When LPLU is enabled we should disable SmartSpeed */ |
---|
5797 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
---|
5798 | if(ret_val) |
---|
5799 | return ret_val; |
---|
5800 | |
---|
5801 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
---|
5802 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
---|
5803 | if(ret_val) |
---|
5804 | return ret_val; |
---|
5805 | |
---|
5806 | } |
---|
5807 | return E1000_SUCCESS; |
---|
5808 | } |
---|
5809 | |
---|
5810 | /***************************************************************************** |
---|
5811 | * |
---|
5812 | * This function sets the lplu d0 state according to the active flag. When |
---|
5813 | * activating lplu this function also disables smart speed and vise versa. |
---|
5814 | * lplu will not be activated unless the device autonegotiation advertisment |
---|
5815 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
---|
5816 | * hw: Struct containing variables accessed by shared code |
---|
5817 | * active - true to enable lplu false to disable lplu. |
---|
5818 | * |
---|
5819 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
---|
5820 | * E1000_SUCCESS at any other case. |
---|
5821 | * |
---|
5822 | ****************************************************************************/ |
---|
5823 | |
---|
5824 | int32_t |
---|
5825 | em_set_d0_lplu_state(struct em_hw *hw, |
---|
5826 | boolean_t active) |
---|
5827 | { |
---|
5828 | int32_t ret_val; |
---|
5829 | uint16_t phy_data; |
---|
5830 | DEBUGFUNC("em_set_d0_lplu_state"); |
---|
5831 | |
---|
5832 | if(hw->mac_type <= em_82547_rev_2) |
---|
5833 | return E1000_SUCCESS; |
---|
5834 | |
---|
5835 | ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
---|
5836 | if(ret_val) |
---|
5837 | return ret_val; |
---|
5838 | |
---|
5839 | if (!active) { |
---|
5840 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
---|
5841 | ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
---|
5842 | if (ret_val) |
---|
5843 | return ret_val; |
---|
5844 | |
---|
5845 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
---|
5846 | * Dx states where the power conservation is most important. During |
---|
5847 | * driver activity we should enable SmartSpeed, so performance is |
---|
5848 | * maintained. */ |
---|
5849 | if (hw->smart_speed == em_smart_speed_on) { |
---|
5850 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5851 | &phy_data); |
---|
5852 | if(ret_val) |
---|
5853 | return ret_val; |
---|
5854 | |
---|
5855 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
---|
5856 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5857 | phy_data); |
---|
5858 | if(ret_val) |
---|
5859 | return ret_val; |
---|
5860 | } else if (hw->smart_speed == em_smart_speed_off) { |
---|
5861 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5862 | &phy_data); |
---|
5863 | if (ret_val) |
---|
5864 | return ret_val; |
---|
5865 | |
---|
5866 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
---|
5867 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
---|
5868 | phy_data); |
---|
5869 | if(ret_val) |
---|
5870 | return ret_val; |
---|
5871 | } |
---|
5872 | |
---|
5873 | |
---|
5874 | } else { |
---|
5875 | |
---|
5876 | phy_data |= IGP02E1000_PM_D0_LPLU; |
---|
5877 | ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
---|
5878 | if (ret_val) |
---|
5879 | return ret_val; |
---|
5880 | |
---|
5881 | /* When LPLU is enabled we should disable SmartSpeed */ |
---|
5882 | ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
---|
5883 | if(ret_val) |
---|
5884 | return ret_val; |
---|
5885 | |
---|
5886 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
---|
5887 | ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
---|
5888 | if(ret_val) |
---|
5889 | return ret_val; |
---|
5890 | |
---|
5891 | } |
---|
5892 | return E1000_SUCCESS; |
---|
5893 | } |
---|
5894 | |
---|
5895 | /****************************************************************************** |
---|
5896 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
---|
5897 | * |
---|
5898 | * hw - Struct containing variables accessed by shared code |
---|
5899 | *****************************************************************************/ |
---|
5900 | static int32_t |
---|
5901 | em_set_vco_speed(struct em_hw *hw) |
---|
5902 | { |
---|
5903 | int32_t ret_val; |
---|
5904 | uint16_t default_page = 0; |
---|
5905 | uint16_t phy_data; |
---|
5906 | |
---|
5907 | DEBUGFUNC("em_set_vco_speed"); |
---|
5908 | |
---|
5909 | switch(hw->mac_type) { |
---|
5910 | case em_82545_rev_3: |
---|
5911 | case em_82546_rev_3: |
---|
5912 | break; |
---|
5913 | default: |
---|
5914 | return E1000_SUCCESS; |
---|
5915 | } |
---|
5916 | |
---|
5917 | /* Set PHY register 30, page 5, bit 8 to 0 */ |
---|
5918 | |
---|
5919 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
---|
5920 | if(ret_val) |
---|
5921 | return ret_val; |
---|
5922 | |
---|
5923 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
---|
5924 | if(ret_val) |
---|
5925 | return ret_val; |
---|
5926 | |
---|
5927 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
---|
5928 | if(ret_val) |
---|
5929 | return ret_val; |
---|
5930 | |
---|
5931 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
---|
5932 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
---|
5933 | if(ret_val) |
---|
5934 | return ret_val; |
---|
5935 | |
---|
5936 | /* Set PHY register 30, page 4, bit 11 to 1 */ |
---|
5937 | |
---|
5938 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
---|
5939 | if(ret_val) |
---|
5940 | return ret_val; |
---|
5941 | |
---|
5942 | ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
---|
5943 | if(ret_val) |
---|
5944 | return ret_val; |
---|
5945 | |
---|
5946 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
---|
5947 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
---|
5948 | if(ret_val) |
---|
5949 | return ret_val; |
---|
5950 | |
---|
5951 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
---|
5952 | if(ret_val) |
---|
5953 | return ret_val; |
---|
5954 | |
---|
5955 | return E1000_SUCCESS; |
---|
5956 | } |
---|
5957 | |
---|
5958 | |
---|
5959 | /***************************************************************************** |
---|
5960 | * This function reads the cookie from ARC ram. |
---|
5961 | * |
---|
5962 | * returns: - E1000_SUCCESS . |
---|
5963 | ****************************************************************************/ |
---|
5964 | int32_t |
---|
5965 | em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer) |
---|
5966 | { |
---|
5967 | uint8_t i; |
---|
5968 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
---|
5969 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
---|
5970 | |
---|
5971 | length = (length >> 2); |
---|
5972 | offset = (offset >> 2); |
---|
5973 | |
---|
5974 | for (i = 0; i < length; i++) { |
---|
5975 | *((uint32_t *) buffer + i) = |
---|
5976 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
---|
5977 | } |
---|
5978 | return E1000_SUCCESS; |
---|
5979 | } |
---|
5980 | |
---|
5981 | |
---|
5982 | /***************************************************************************** |
---|
5983 | * This function checks whether the HOST IF is enabled for command operaton |
---|
5984 | * and also checks whether the previous command is completed. |
---|
5985 | * It busy waits in case of previous command is not completed. |
---|
5986 | * |
---|
5987 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
---|
5988 | * timeout |
---|
5989 | * - E1000_SUCCESS for success. |
---|
5990 | ****************************************************************************/ |
---|
5991 | int32_t |
---|
5992 | em_mng_enable_host_if(struct em_hw * hw) |
---|
5993 | { |
---|
5994 | uint32_t hicr; |
---|
5995 | uint8_t i; |
---|
5996 | |
---|
5997 | /* Check that the host interface is enabled. */ |
---|
5998 | hicr = E1000_READ_REG(hw, HICR); |
---|
5999 | if ((hicr & E1000_HICR_EN) == 0) { |
---|
6000 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); |
---|
6001 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
---|
6002 | } |
---|
6003 | /* check the previous command is completed */ |
---|
6004 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
---|
6005 | hicr = E1000_READ_REG(hw, HICR); |
---|
6006 | if (!(hicr & E1000_HICR_C)) |
---|
6007 | break; |
---|
6008 | msec_delay_irq(1); |
---|
6009 | } |
---|
6010 | |
---|
6011 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
---|
6012 | DEBUGOUT("Previous command timeout failed .\n"); |
---|
6013 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
---|
6014 | } |
---|
6015 | return E1000_SUCCESS; |
---|
6016 | } |
---|
6017 | |
---|
6018 | /***************************************************************************** |
---|
6019 | * This function writes the buffer content at the offset given on the host if. |
---|
6020 | * It also does alignment considerations to do the writes in most efficient way. |
---|
6021 | * Also fills up the sum of the buffer in *buffer parameter. |
---|
6022 | * |
---|
6023 | * returns - E1000_SUCCESS for success. |
---|
6024 | ****************************************************************************/ |
---|
6025 | int32_t |
---|
6026 | em_mng_host_if_write(struct em_hw * hw, uint8_t *buffer, |
---|
6027 | uint16_t length, uint16_t offset, uint8_t *sum) |
---|
6028 | { |
---|
6029 | uint8_t *tmp; |
---|
6030 | uint8_t *bufptr = buffer; |
---|
6031 | uint32_t data; |
---|
6032 | uint16_t remaining, i, j, prev_bytes; |
---|
6033 | |
---|
6034 | /* sum = only sum of the data and it is not checksum */ |
---|
6035 | |
---|
6036 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { |
---|
6037 | return -E1000_ERR_PARAM; |
---|
6038 | } |
---|
6039 | |
---|
6040 | tmp = (uint8_t *)&data; |
---|
6041 | prev_bytes = offset & 0x3; |
---|
6042 | offset &= 0xFFFC; |
---|
6043 | offset >>= 2; |
---|
6044 | |
---|
6045 | if (prev_bytes) { |
---|
6046 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); |
---|
6047 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { |
---|
6048 | *(tmp + j) = *bufptr++; |
---|
6049 | *sum += *(tmp + j); |
---|
6050 | } |
---|
6051 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); |
---|
6052 | length -= j - prev_bytes; |
---|
6053 | offset++; |
---|
6054 | } |
---|
6055 | |
---|
6056 | remaining = length & 0x3; |
---|
6057 | length -= remaining; |
---|
6058 | |
---|
6059 | /* Calculate length in DWORDs */ |
---|
6060 | length >>= 2; |
---|
6061 | |
---|
6062 | /* The device driver writes the relevant command block into the |
---|
6063 | * ram area. */ |
---|
6064 | for (i = 0; i < length; i++) { |
---|
6065 | for (j = 0; j < sizeof(uint32_t); j++) { |
---|
6066 | *(tmp + j) = *bufptr++; |
---|
6067 | *sum += *(tmp + j); |
---|
6068 | } |
---|
6069 | |
---|
6070 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
---|
6071 | } |
---|
6072 | if (remaining) { |
---|
6073 | for (j = 0; j < sizeof(uint32_t); j++) { |
---|
6074 | if (j < remaining) |
---|
6075 | *(tmp + j) = *bufptr++; |
---|
6076 | else |
---|
6077 | *(tmp + j) = 0; |
---|
6078 | |
---|
6079 | *sum += *(tmp + j); |
---|
6080 | } |
---|
6081 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
---|
6082 | } |
---|
6083 | |
---|
6084 | return E1000_SUCCESS; |
---|
6085 | } |
---|
6086 | |
---|
6087 | |
---|
6088 | /***************************************************************************** |
---|
6089 | * This function writes the command header after does the checksum calculation. |
---|
6090 | * |
---|
6091 | * returns - E1000_SUCCESS for success. |
---|
6092 | ****************************************************************************/ |
---|
6093 | int32_t |
---|
6094 | em_mng_write_cmd_header(struct em_hw * hw, |
---|
6095 | struct em_host_mng_command_header * hdr) |
---|
6096 | { |
---|
6097 | uint16_t i; |
---|
6098 | uint8_t sum; |
---|
6099 | uint8_t *buffer; |
---|
6100 | |
---|
6101 | /* Write the whole command header structure which includes sum of |
---|
6102 | * the buffer */ |
---|
6103 | |
---|
6104 | uint16_t length = sizeof(struct em_host_mng_command_header); |
---|
6105 | |
---|
6106 | sum = hdr->checksum; |
---|
6107 | hdr->checksum = 0; |
---|
6108 | |
---|
6109 | buffer = (uint8_t *) hdr; |
---|
6110 | i = length; |
---|
6111 | while(i--) |
---|
6112 | sum += buffer[i]; |
---|
6113 | |
---|
6114 | hdr->checksum = 0 - sum; |
---|
6115 | |
---|
6116 | length >>= 2; |
---|
6117 | /* The device driver writes the relevant command block into the ram area. */ |
---|
6118 | for (i = 0; i < length; i++) |
---|
6119 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
---|
6120 | |
---|
6121 | return E1000_SUCCESS; |
---|
6122 | } |
---|
6123 | |
---|
6124 | |
---|
6125 | /***************************************************************************** |
---|
6126 | * This function indicates to ARC that a new command is pending which completes |
---|
6127 | * one write operation by the driver. |
---|
6128 | * |
---|
6129 | * returns - E1000_SUCCESS for success. |
---|
6130 | ****************************************************************************/ |
---|
6131 | int32_t |
---|
6132 | em_mng_write_commit( |
---|
6133 | struct em_hw * hw) |
---|
6134 | { |
---|
6135 | uint32_t hicr; |
---|
6136 | |
---|
6137 | hicr = E1000_READ_REG(hw, HICR); |
---|
6138 | /* Setting this bit tells the ARC that a new command is pending. */ |
---|
6139 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); |
---|
6140 | |
---|
6141 | return E1000_SUCCESS; |
---|
6142 | } |
---|
6143 | |
---|
6144 | |
---|
6145 | /***************************************************************************** |
---|
6146 | * This function checks the mode of the firmware. |
---|
6147 | * |
---|
6148 | * returns - TRUE when the mode is IAMT or FALSE. |
---|
6149 | ****************************************************************************/ |
---|
6150 | boolean_t |
---|
6151 | em_check_mng_mode( |
---|
6152 | struct em_hw *hw) |
---|
6153 | { |
---|
6154 | uint32_t fwsm; |
---|
6155 | |
---|
6156 | fwsm = E1000_READ_REG(hw, FWSM); |
---|
6157 | |
---|
6158 | if((fwsm & E1000_FWSM_MODE_MASK) == |
---|
6159 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
---|
6160 | return TRUE; |
---|
6161 | |
---|
6162 | return FALSE; |
---|
6163 | } |
---|
6164 | |
---|
6165 | |
---|
6166 | /***************************************************************************** |
---|
6167 | * This function writes the dhcp info . |
---|
6168 | ****************************************************************************/ |
---|
6169 | int32_t |
---|
6170 | em_mng_write_dhcp_info(struct em_hw * hw, uint8_t *buffer, |
---|
6171 | uint16_t length) |
---|
6172 | { |
---|
6173 | int32_t ret_val; |
---|
6174 | struct em_host_mng_command_header hdr; |
---|
6175 | |
---|
6176 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
---|
6177 | hdr.command_length = length; |
---|
6178 | hdr.reserved1 = 0; |
---|
6179 | hdr.reserved2 = 0; |
---|
6180 | hdr.checksum = 0; |
---|
6181 | |
---|
6182 | ret_val = em_mng_enable_host_if(hw); |
---|
6183 | if (ret_val == E1000_SUCCESS) { |
---|
6184 | ret_val = em_mng_host_if_write(hw, buffer, length, sizeof(hdr), |
---|
6185 | &(hdr.checksum)); |
---|
6186 | if (ret_val == E1000_SUCCESS) { |
---|
6187 | ret_val = em_mng_write_cmd_header(hw, &hdr); |
---|
6188 | if (ret_val == E1000_SUCCESS) |
---|
6189 | ret_val = em_mng_write_commit(hw); |
---|
6190 | } |
---|
6191 | } |
---|
6192 | return ret_val; |
---|
6193 | } |
---|
6194 | |
---|
6195 | |
---|
6196 | /***************************************************************************** |
---|
6197 | * This function calculates the checksum. |
---|
6198 | * |
---|
6199 | * returns - checksum of buffer contents. |
---|
6200 | ****************************************************************************/ |
---|
6201 | uint8_t |
---|
6202 | em_calculate_mng_checksum(char *buffer, uint32_t length) |
---|
6203 | { |
---|
6204 | uint8_t sum = 0; |
---|
6205 | uint32_t i; |
---|
6206 | |
---|
6207 | if (!buffer) |
---|
6208 | return 0; |
---|
6209 | |
---|
6210 | for (i=0; i < length; i++) |
---|
6211 | sum += buffer[i]; |
---|
6212 | |
---|
6213 | return (uint8_t) (0 - sum); |
---|
6214 | } |
---|
6215 | |
---|
6216 | /***************************************************************************** |
---|
6217 | * This function checks whether tx pkt filtering needs to be enabled or not. |
---|
6218 | * |
---|
6219 | * returns - TRUE for packet filtering or FALSE. |
---|
6220 | ****************************************************************************/ |
---|
6221 | boolean_t |
---|
6222 | em_enable_tx_pkt_filtering(struct em_hw *hw) |
---|
6223 | { |
---|
6224 | /* called in init as well as watchdog timer functions */ |
---|
6225 | |
---|
6226 | int32_t ret_val, checksum; |
---|
6227 | boolean_t tx_filter = FALSE; |
---|
6228 | struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
---|
6229 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); |
---|
6230 | |
---|
6231 | if (em_check_mng_mode(hw)) { |
---|
6232 | ret_val = em_mng_enable_host_if(hw); |
---|
6233 | if (ret_val == E1000_SUCCESS) { |
---|
6234 | ret_val = em_host_if_read_cookie(hw, buffer); |
---|
6235 | if (ret_val == E1000_SUCCESS) { |
---|
6236 | checksum = hdr->checksum; |
---|
6237 | hdr->checksum = 0; |
---|
6238 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && |
---|
6239 | checksum == em_calculate_mng_checksum((char *)buffer, |
---|
6240 | E1000_MNG_DHCP_COOKIE_LENGTH)) { |
---|
6241 | if (hdr->status & |
---|
6242 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) |
---|
6243 | tx_filter = TRUE; |
---|
6244 | } else |
---|
6245 | tx_filter = TRUE; |
---|
6246 | } else |
---|
6247 | tx_filter = TRUE; |
---|
6248 | } |
---|
6249 | } |
---|
6250 | |
---|
6251 | hw->tx_pkt_filtering = tx_filter; |
---|
6252 | return tx_filter; |
---|
6253 | } |
---|
6254 | |
---|
6255 | /****************************************************************************** |
---|
6256 | * Verifies the hardware needs to allow ARPs to be processed by the host |
---|
6257 | * |
---|
6258 | * hw - Struct containing variables accessed by shared code |
---|
6259 | * |
---|
6260 | * returns: - TRUE/FALSE |
---|
6261 | * |
---|
6262 | *****************************************************************************/ |
---|
6263 | uint32_t |
---|
6264 | em_enable_mng_pass_thru(struct em_hw *hw) |
---|
6265 | { |
---|
6266 | uint32_t manc; |
---|
6267 | uint32_t fwsm, factps; |
---|
6268 | |
---|
6269 | if (hw->asf_firmware_present) { |
---|
6270 | manc = E1000_READ_REG(hw, MANC); |
---|
6271 | |
---|
6272 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
---|
6273 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
---|
6274 | return FALSE; |
---|
6275 | if (em_arc_subsystem_valid(hw) == TRUE) { |
---|
6276 | fwsm = E1000_READ_REG(hw, FWSM); |
---|
6277 | factps = E1000_READ_REG(hw, FACTPS); |
---|
6278 | |
---|
6279 | if (((fwsm & E1000_FWSM_MODE_MASK) == |
---|
6280 | (em_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && |
---|
6281 | (factps & E1000_FACTPS_MNGCG)) |
---|
6282 | return TRUE; |
---|
6283 | } else |
---|
6284 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
---|
6285 | return TRUE; |
---|
6286 | } |
---|
6287 | return FALSE; |
---|
6288 | } |
---|
6289 | |
---|
6290 | static int32_t |
---|
6291 | em_polarity_reversal_workaround(struct em_hw *hw) |
---|
6292 | { |
---|
6293 | int32_t ret_val; |
---|
6294 | uint16_t mii_status_reg; |
---|
6295 | uint16_t i; |
---|
6296 | |
---|
6297 | /* Polarity reversal workaround for forced 10F/10H links. */ |
---|
6298 | |
---|
6299 | /* Disable the transmitter on the PHY */ |
---|
6300 | |
---|
6301 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
---|
6302 | if(ret_val) |
---|
6303 | return ret_val; |
---|
6304 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
---|
6305 | if(ret_val) |
---|
6306 | return ret_val; |
---|
6307 | |
---|
6308 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
---|
6309 | if(ret_val) |
---|
6310 | return ret_val; |
---|
6311 | |
---|
6312 | /* This loop will early-out if the NO link condition has been met. */ |
---|
6313 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
---|
6314 | /* Read the MII Status Register and wait for Link Status bit |
---|
6315 | * to be clear. |
---|
6316 | */ |
---|
6317 | |
---|
6318 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
6319 | if(ret_val) |
---|
6320 | return ret_val; |
---|
6321 | |
---|
6322 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
6323 | if(ret_val) |
---|
6324 | return ret_val; |
---|
6325 | |
---|
6326 | if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
---|
6327 | msec_delay_irq(100); |
---|
6328 | } |
---|
6329 | |
---|
6330 | /* Recommended delay time after link has been lost */ |
---|
6331 | msec_delay_irq(1000); |
---|
6332 | |
---|
6333 | /* Now we will re-enable th transmitter on the PHY */ |
---|
6334 | |
---|
6335 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
---|
6336 | if(ret_val) |
---|
6337 | return ret_val; |
---|
6338 | msec_delay_irq(50); |
---|
6339 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
---|
6340 | if(ret_val) |
---|
6341 | return ret_val; |
---|
6342 | msec_delay_irq(50); |
---|
6343 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
---|
6344 | if(ret_val) |
---|
6345 | return ret_val; |
---|
6346 | msec_delay_irq(50); |
---|
6347 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
---|
6348 | if(ret_val) |
---|
6349 | return ret_val; |
---|
6350 | |
---|
6351 | ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
---|
6352 | if(ret_val) |
---|
6353 | return ret_val; |
---|
6354 | |
---|
6355 | /* This loop will early-out if the link condition has been met. */ |
---|
6356 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
---|
6357 | /* Read the MII Status Register and wait for Link Status bit |
---|
6358 | * to be set. |
---|
6359 | */ |
---|
6360 | |
---|
6361 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
6362 | if(ret_val) |
---|
6363 | return ret_val; |
---|
6364 | |
---|
6365 | ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
---|
6366 | if(ret_val) |
---|
6367 | return ret_val; |
---|
6368 | |
---|
6369 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
---|
6370 | msec_delay_irq(100); |
---|
6371 | } |
---|
6372 | return E1000_SUCCESS; |
---|
6373 | } |
---|
6374 | |
---|
6375 | /*************************************************************************** |
---|
6376 | * |
---|
6377 | * Disables PCI-Express master access. |
---|
6378 | * |
---|
6379 | * hw: Struct containing variables accessed by shared code |
---|
6380 | * |
---|
6381 | * returns: - none. |
---|
6382 | * |
---|
6383 | ***************************************************************************/ |
---|
6384 | void |
---|
6385 | em_set_pci_express_master_disable(struct em_hw *hw) |
---|
6386 | { |
---|
6387 | uint32_t ctrl; |
---|
6388 | |
---|
6389 | DEBUGFUNC("em_set_pci_express_master_disable"); |
---|
6390 | |
---|
6391 | if (hw->bus_type != em_bus_type_pci_express) |
---|
6392 | return; |
---|
6393 | |
---|
6394 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
6395 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
---|
6396 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
6397 | } |
---|
6398 | |
---|
6399 | /*************************************************************************** |
---|
6400 | * |
---|
6401 | * Enables PCI-Express master access. |
---|
6402 | * |
---|
6403 | * hw: Struct containing variables accessed by shared code |
---|
6404 | * |
---|
6405 | * returns: - none. |
---|
6406 | * |
---|
6407 | ***************************************************************************/ |
---|
6408 | void |
---|
6409 | em_enable_pciex_master(struct em_hw *hw) |
---|
6410 | { |
---|
6411 | uint32_t ctrl; |
---|
6412 | |
---|
6413 | DEBUGFUNC("em_enable_pciex_master"); |
---|
6414 | |
---|
6415 | if (hw->bus_type != em_bus_type_pci_express) |
---|
6416 | return; |
---|
6417 | |
---|
6418 | ctrl = E1000_READ_REG(hw, CTRL); |
---|
6419 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; |
---|
6420 | E1000_WRITE_REG(hw, CTRL, ctrl); |
---|
6421 | } |
---|
6422 | |
---|
6423 | /******************************************************************************* |
---|
6424 | * |
---|
6425 | * Disables PCI-Express master access and verifies there are no pending requests |
---|
6426 | * |
---|
6427 | * hw: Struct containing variables accessed by shared code |
---|
6428 | * |
---|
6429 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't |
---|
6430 | * caused the master requests to be disabled. |
---|
6431 | * E1000_SUCCESS master requests disabled. |
---|
6432 | * |
---|
6433 | ******************************************************************************/ |
---|
6434 | int32_t |
---|
6435 | em_disable_pciex_master(struct em_hw *hw) |
---|
6436 | { |
---|
6437 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
---|
6438 | |
---|
6439 | DEBUGFUNC("em_disable_pciex_master"); |
---|
6440 | |
---|
6441 | if (hw->bus_type != em_bus_type_pci_express) |
---|
6442 | return E1000_SUCCESS; |
---|
6443 | |
---|
6444 | em_set_pci_express_master_disable(hw); |
---|
6445 | |
---|
6446 | while(timeout) { |
---|
6447 | if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
---|
6448 | break; |
---|
6449 | else |
---|
6450 | usec_delay(100); |
---|
6451 | timeout--; |
---|
6452 | } |
---|
6453 | |
---|
6454 | if(!timeout) { |
---|
6455 | DEBUGOUT("Master requests are pending.\n"); |
---|
6456 | return -E1000_ERR_MASTER_REQUESTS_PENDING; |
---|
6457 | } |
---|
6458 | |
---|
6459 | return E1000_SUCCESS; |
---|
6460 | } |
---|
6461 | |
---|
6462 | /******************************************************************************* |
---|
6463 | * |
---|
6464 | * Check for EEPROM Auto Read bit done. |
---|
6465 | * |
---|
6466 | * hw: Struct containing variables accessed by shared code |
---|
6467 | * |
---|
6468 | * returns: - E1000_ERR_RESET if fail to reset MAC |
---|
6469 | * E1000_SUCCESS at any other case. |
---|
6470 | * |
---|
6471 | ******************************************************************************/ |
---|
6472 | int32_t |
---|
6473 | em_get_auto_rd_done(struct em_hw *hw) |
---|
6474 | { |
---|
6475 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; |
---|
6476 | |
---|
6477 | DEBUGFUNC("em_get_auto_rd_done"); |
---|
6478 | |
---|
6479 | switch (hw->mac_type) { |
---|
6480 | default: |
---|
6481 | msec_delay(5); |
---|
6482 | break; |
---|
6483 | case em_82573: |
---|
6484 | while(timeout) { |
---|
6485 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; |
---|
6486 | else msec_delay(1); |
---|
6487 | timeout--; |
---|
6488 | } |
---|
6489 | |
---|
6490 | if(!timeout) { |
---|
6491 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
---|
6492 | return -E1000_ERR_RESET; |
---|
6493 | } |
---|
6494 | break; |
---|
6495 | } |
---|
6496 | |
---|
6497 | return E1000_SUCCESS; |
---|
6498 | } |
---|
6499 | |
---|
6500 | /*************************************************************************** |
---|
6501 | * Checks if the PHY configuration is done |
---|
6502 | * |
---|
6503 | * hw: Struct containing variables accessed by shared code |
---|
6504 | * |
---|
6505 | * returns: - E1000_ERR_RESET if fail to reset MAC |
---|
6506 | * E1000_SUCCESS at any other case. |
---|
6507 | * |
---|
6508 | ***************************************************************************/ |
---|
6509 | int32_t |
---|
6510 | em_get_phy_cfg_done(struct em_hw *hw) |
---|
6511 | { |
---|
6512 | DEBUGFUNC("em_get_phy_cfg_done"); |
---|
6513 | |
---|
6514 | /* Simply wait for 10ms */ |
---|
6515 | msec_delay(10); |
---|
6516 | |
---|
6517 | return E1000_SUCCESS; |
---|
6518 | } |
---|
6519 | |
---|
6520 | /*************************************************************************** |
---|
6521 | * |
---|
6522 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
---|
6523 | * adapter or Eeprom access. |
---|
6524 | * |
---|
6525 | * hw: Struct containing variables accessed by shared code |
---|
6526 | * |
---|
6527 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
---|
6528 | * E1000_SUCCESS at any other case. |
---|
6529 | * |
---|
6530 | ***************************************************************************/ |
---|
6531 | int32_t |
---|
6532 | em_get_hw_eeprom_semaphore(struct em_hw *hw) |
---|
6533 | { |
---|
6534 | int32_t timeout; |
---|
6535 | uint32_t swsm; |
---|
6536 | |
---|
6537 | DEBUGFUNC("em_get_hw_eeprom_semaphore"); |
---|
6538 | |
---|
6539 | if(!hw->eeprom_semaphore_present) |
---|
6540 | return E1000_SUCCESS; |
---|
6541 | |
---|
6542 | |
---|
6543 | /* Get the FW semaphore. */ |
---|
6544 | timeout = hw->eeprom.word_size + 1; |
---|
6545 | while(timeout) { |
---|
6546 | swsm = E1000_READ_REG(hw, SWSM); |
---|
6547 | swsm |= E1000_SWSM_SWESMBI; |
---|
6548 | E1000_WRITE_REG(hw, SWSM, swsm); |
---|
6549 | /* if we managed to set the bit we got the semaphore. */ |
---|
6550 | swsm = E1000_READ_REG(hw, SWSM); |
---|
6551 | if(swsm & E1000_SWSM_SWESMBI) |
---|
6552 | break; |
---|
6553 | |
---|
6554 | usec_delay(50); |
---|
6555 | timeout--; |
---|
6556 | } |
---|
6557 | |
---|
6558 | if(!timeout) { |
---|
6559 | /* Release semaphores */ |
---|
6560 | em_put_hw_eeprom_semaphore(hw); |
---|
6561 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); |
---|
6562 | return -E1000_ERR_EEPROM; |
---|
6563 | } |
---|
6564 | |
---|
6565 | return E1000_SUCCESS; |
---|
6566 | } |
---|
6567 | |
---|
6568 | /*************************************************************************** |
---|
6569 | * This function clears HW semaphore bits. |
---|
6570 | * |
---|
6571 | * hw: Struct containing variables accessed by shared code |
---|
6572 | * |
---|
6573 | * returns: - None. |
---|
6574 | * |
---|
6575 | ***************************************************************************/ |
---|
6576 | void |
---|
6577 | em_put_hw_eeprom_semaphore(struct em_hw *hw) |
---|
6578 | { |
---|
6579 | uint32_t swsm; |
---|
6580 | |
---|
6581 | DEBUGFUNC("em_put_hw_eeprom_semaphore"); |
---|
6582 | |
---|
6583 | if(!hw->eeprom_semaphore_present) |
---|
6584 | return; |
---|
6585 | |
---|
6586 | swsm = E1000_READ_REG(hw, SWSM); |
---|
6587 | /* Release both semaphores. */ |
---|
6588 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
---|
6589 | E1000_WRITE_REG(hw, SWSM, swsm); |
---|
6590 | } |
---|
6591 | |
---|
6592 | /****************************************************************************** |
---|
6593 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
---|
6594 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
---|
6595 | * the caller to figure out how to deal with it. |
---|
6596 | * |
---|
6597 | * hw - Struct containing variables accessed by shared code |
---|
6598 | * |
---|
6599 | * returns: - E1000_BLK_PHY_RESET |
---|
6600 | * E1000_SUCCESS |
---|
6601 | * |
---|
6602 | *****************************************************************************/ |
---|
6603 | int32_t |
---|
6604 | em_check_phy_reset_block(struct em_hw *hw) |
---|
6605 | { |
---|
6606 | uint32_t manc = 0; |
---|
6607 | if(hw->mac_type > em_82547_rev_2) |
---|
6608 | manc = E1000_READ_REG(hw, MANC); |
---|
6609 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
---|
6610 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
---|
6611 | } |
---|
6612 | |
---|
6613 | uint8_t |
---|
6614 | em_arc_subsystem_valid(struct em_hw *hw) |
---|
6615 | { |
---|
6616 | uint32_t fwsm; |
---|
6617 | |
---|
6618 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC |
---|
6619 | * may not be provided a DMA clock when no manageability features are |
---|
6620 | * enabled. We do not want to perform any reads/writes to these registers |
---|
6621 | * if this is the case. We read FWSM to determine the manageability mode. |
---|
6622 | */ |
---|
6623 | switch (hw->mac_type) { |
---|
6624 | case em_82573: |
---|
6625 | fwsm = E1000_READ_REG(hw, FWSM); |
---|
6626 | if((fwsm & E1000_FWSM_MODE_MASK) != 0) |
---|
6627 | return TRUE; |
---|
6628 | break; |
---|
6629 | default: |
---|
6630 | break; |
---|
6631 | } |
---|
6632 | return FALSE; |
---|
6633 | } |
---|
6634 | |
---|
6635 | |
---|
6636 | |
---|