[b7a6d23a] | 1 | /* $NetBSD: gti2c.c,v 1.2 2005/02/27 00:27:21 perry Exp $ */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Copyright (c) 2005 Brocade Communcations, inc. |
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| 5 | * All rights reserved. |
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| 6 | * |
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| 7 | * Written by Matt Thomas for Brocade Communcations, Inc. |
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| 8 | * |
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| 9 | * Redistribution and use in source and binary forms, with or without |
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| 10 | * modification, are permitted provided that the following conditions |
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| 11 | * are met: |
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| 12 | * 1. Redistributions of source code must retain the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer. |
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| 14 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 15 | * notice, this list of conditions and the following disclaimer in the |
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| 16 | * documentation and/or other materials provided with the distribution. |
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| 17 | * 3. The name of Brocade Communications, Inc. may not be used to endorse |
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| 18 | * or promote products derived from this software without specific prior |
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| 19 | * written permission. |
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| 20 | * |
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| 21 | * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND |
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| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE |
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| 25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
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| 31 | * OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 32 | */ |
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| 33 | |
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| 34 | /* Fixed many things + ported to RTEMS by Till Straumann, 2005 */ |
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| 35 | |
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| 36 | #include <stdio.h> |
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| 37 | #include <rtems.h> |
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| 38 | #include <libcpu/io.h> |
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| 39 | #include <sys/errno.h> |
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| 40 | #include <rtems/bspIo.h> |
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| 41 | #include <rtems/score/sysstate.h> |
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| 42 | #include <bsp/irq.h> |
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| 43 | #include <rtems/libi2c.h> |
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| 44 | |
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| 45 | #include <sys/cdefs.h> |
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| 46 | |
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| 47 | #include <bsp/gtintrreg.h> |
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| 48 | #include <bsp/gti2creg.h> |
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| 49 | #include <bsp/gti2c_busdrv.h> |
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| 50 | |
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| 51 | #define ENABLE_IRQ_AT_PIC_HACK /* workaround for a bad HW bug */ |
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| 52 | #undef DEBUG |
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| 53 | |
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| 54 | #ifndef BSP_IRQ_MIN_PRIO |
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| 55 | #define BSP_IRQ_MIN_PRIO 1 |
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| 56 | #endif |
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| 57 | |
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| 58 | struct gti2c_softc { |
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| 59 | uint32_t sc_gt; |
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| 60 | uint32_t sc_cntl; |
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| 61 | int sc_inited; |
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| 62 | rtems_id sc_sync; |
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| 63 | int sc_irqs; /* statistics */ |
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| 64 | }; |
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| 65 | |
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| 66 | #ifdef DEBUG |
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| 67 | #define STATIC |
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| 68 | #else |
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| 69 | #define STATIC static |
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| 70 | #endif |
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| 71 | |
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| 72 | typedef struct { |
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| 73 | rtems_libi2c_bus_t bus_desc; |
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| 74 | struct gti2c_softc pvt; |
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| 75 | } gti2c_desc_rec, *gti2c_desc; |
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| 76 | |
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| 77 | STATIC rtems_status_code |
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| 78 | gt_i2c_init(rtems_libi2c_bus_t *bh); |
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| 79 | STATIC rtems_status_code |
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| 80 | gt_i2c_send_start(rtems_libi2c_bus_t *bh); |
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| 81 | STATIC rtems_status_code |
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| 82 | gt_i2c_send_stop(rtems_libi2c_bus_t *bh); |
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| 83 | STATIC rtems_status_code |
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| 84 | gt_i2c_send_addr(rtems_libi2c_bus_t *bh, uint32_t addr, int rw); |
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| 85 | STATIC int |
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| 86 | gt_i2c_read_bytes(rtems_libi2c_bus_t *bh, unsigned char *buf, int len); |
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| 87 | STATIC int |
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| 88 | gt_i2c_write_bytes(rtems_libi2c_bus_t *bh, unsigned char *buf, int len); |
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| 89 | |
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| 90 | static rtems_libi2c_bus_ops_t myops = { |
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| 91 | init: gt_i2c_init, |
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| 92 | send_start: gt_i2c_send_start, |
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| 93 | send_stop: gt_i2c_send_stop, |
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| 94 | send_addr: gt_i2c_send_addr, |
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| 95 | read_bytes: gt_i2c_read_bytes, |
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| 96 | write_bytes: gt_i2c_write_bytes, |
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| 97 | }; |
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| 98 | |
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| 99 | static gti2c_desc_rec my_bus_tbl = { |
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| 100 | { |
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| 101 | ops: &myops, |
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| 102 | size: sizeof(my_bus_tbl), |
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| 103 | },/* public fields */ |
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| 104 | { |
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| 105 | sc_gt: BSP_MV64x60_BASE, |
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| 106 | sc_cntl: I2C_Control_TWSIEn, |
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| 107 | sc_inited: 0, |
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| 108 | sc_sync: 0 |
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| 109 | } /* our private fields */ |
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| 110 | }; |
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| 111 | |
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| 112 | |
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| 113 | static inline uint32_t |
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| 114 | gt_read(uint32_t base, uint32_t off) |
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| 115 | { |
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[2d5c486] | 116 | return in_le32((volatile uint32_t*)(base+off)); |
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[b7a6d23a] | 117 | } |
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| 118 | |
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| 119 | static inline void |
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| 120 | gt_write(uint32_t base, uint32_t off, uint32_t val) |
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| 121 | { |
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[2d5c486] | 122 | out_le32((volatile uint32_t*)(base+off), val); |
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[b7a6d23a] | 123 | } |
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| 124 | |
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| 125 | |
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| 126 | static inline void |
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| 127 | disable_irq(struct gti2c_softc *sc) |
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| 128 | { |
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| 129 | uint32_t v = gt_read(sc->sc_gt, I2C_REG_Control); |
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| 130 | gt_write(sc->sc_gt, I2C_REG_Control, v & ~I2C_Control_IntEn); |
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| 131 | } |
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| 132 | |
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| 133 | |
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| 134 | static rtems_status_code |
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| 135 | gt_i2c_wait(struct gti2c_softc *sc, uint32_t control, uint32_t desired_status) |
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| 136 | { |
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| 137 | uint32_t status; |
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| 138 | rtems_status_code rval; |
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| 139 | |
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| 140 | control |= I2C_Control_IntEn; |
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| 141 | |
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| 142 | gt_write(sc->sc_gt, I2C_REG_Control, control | sc->sc_cntl); |
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| 143 | |
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| 144 | if ( sc->sc_inited ) { |
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| 145 | |
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| 146 | #ifdef ENABLE_IRQ_AT_PIC_HACK |
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| 147 | BSP_enable_irq_at_pic(BSP_IRQ_I2C); |
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| 148 | #endif |
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| 149 | |
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| 150 | rval = rtems_semaphore_obtain(sc->sc_sync, RTEMS_WAIT, 100); |
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| 151 | |
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| 152 | if ( RTEMS_SUCCESSFUL != rval ) |
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| 153 | return rval; |
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| 154 | } else { |
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| 155 | uint32_t then, now; |
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| 156 | |
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| 157 | /* run in polling mode - useful during init */ |
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| 158 | if ( _System_state_Is_up(_System_state_Get()) ) { |
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| 159 | printk("WARNING: gti2c running in polled mode -- should initialize properly!\n"); |
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| 160 | } |
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| 161 | |
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| 162 | asm volatile("mftb %0":"=r"(then)); |
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| 163 | |
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| 164 | do { |
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| 165 | asm volatile("mftb %0":"=r"(now)); |
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| 166 | /* poll timebase for .2 seconds assuming a bus clock of 100MHz */ |
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| 167 | if ( now - then > (uint32_t)100000000/4/5 ) |
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| 168 | return RTEMS_TIMEOUT; |
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| 169 | } while ( ! (I2C_Control_IFlg & gt_read(sc->sc_gt, I2C_REG_Control)) ); |
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| 170 | } |
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| 171 | |
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| 172 | status = gt_read(sc->sc_gt, I2C_REG_Status); |
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| 173 | |
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| 174 | if ( status != desired_status && (status!=I2C_Status_ReStarted || desired_status!=I2C_Status_Started) ) |
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| 175 | return RTEMS_IO_ERROR; |
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| 176 | |
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| 177 | return RTEMS_SUCCESSFUL; |
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| 178 | } |
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| 179 | |
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| 180 | static void |
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| 181 | gt_i2c_intr(void *arg) |
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| 182 | { |
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| 183 | struct gti2c_softc * const sc = &my_bus_tbl.pvt; |
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| 184 | uint32_t v; |
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| 185 | |
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| 186 | v = gt_read(sc->sc_gt, I2C_REG_Control); |
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| 187 | if ((v & I2C_Control_IFlg) == 0) { |
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| 188 | printk("gt_i2c_intr: IRQ but IFlg not set??\n"); |
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| 189 | return; |
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| 190 | } |
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| 191 | gt_write(sc->sc_gt, I2C_REG_Control, v & ~(I2C_Control_IntEn)); |
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| 192 | #if 0 |
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| 193 | gt_read(sc->sc_gt, I2C_REG_Control); |
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| 194 | asm volatile("sync"); |
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| 195 | /* This is how bad it is: after turning off the IntEn bit, the line |
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| 196 | * still remains asserted! (shame on you.) |
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| 197 | * |
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| 198 | * The test below (on MVME6100; the MVME5500 has the same problem |
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| 199 | * but the main cause register address is different; substitute |
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| 200 | * 0xf100000c for 0xf1000c68 on a 5500). |
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| 201 | * |
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| 202 | * The skew was 101 TB ticks or ~3us (bus freq 133MHz) which |
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| 203 | * really sucks. |
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| 204 | * |
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| 205 | * Therefore, we must disable the interrupt at the PIC |
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| 206 | */ |
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| 207 | {unsigned from,to; |
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| 208 | asm volatile("mftb %0":"=r"(from)); |
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[2d5c486] | 209 | while ( in_le32((volatile uint32_t*)0xf100000c) & 0x20 ) |
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[b7a6d23a] | 210 | ; |
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| 211 | asm volatile("mftb %0":"=r"(to)); |
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| 212 | printk("I2C IRQ remained asserted for %i TB ticks!\n",to-from); |
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| 213 | } |
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| 214 | #endif |
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| 215 | #ifdef ENABLE_IRQ_AT_PIC_HACK |
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| 216 | BSP_disable_irq_at_pic(BSP_IRQ_I2C); |
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| 217 | #endif |
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| 218 | |
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| 219 | sc->sc_irqs++; |
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| 220 | |
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| 221 | rtems_semaphore_release(sc->sc_sync); |
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| 222 | } |
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| 223 | |
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| 224 | STATIC rtems_status_code |
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| 225 | gt_i2c_init(rtems_libi2c_bus_t *bh) |
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| 226 | { |
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| 227 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 228 | unsigned m,n,N; |
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| 229 | |
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| 230 | disable_irq(sc); |
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| 231 | |
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| 232 | /* reset */ |
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| 233 | gt_write(sc->sc_gt, I2C_REG_SoftReset, 0); |
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| 234 | gt_write(sc->sc_gt, I2C_REG_SlaveAddr, 0); |
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| 235 | gt_write(sc->sc_gt, I2C_REG_ExtSlaveAddr, 0); |
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| 236 | |
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| 237 | /* Set baud rate; I don't know the details |
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| 238 | * but have to assume that it has to fit into 7 bits |
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| 239 | * (as indicated by some experiment) |
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| 240 | */ |
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| 241 | n = 0, N=1<<n; |
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| 242 | do { |
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| 243 | n++, N<<=1; |
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| 244 | /* increase 2^n until m becomes small enough */ |
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| 245 | m = BSP_bus_frequency / 10 / 62500 / N; |
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| 246 | } while ( m > 16 ); |
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| 247 | |
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| 248 | /* n is at least 1 */ |
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| 249 | if ( n > 8 ) { |
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| 250 | n = 8; m = 16; /* nothing else we can do */ |
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| 251 | } |
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| 252 | if ( 0 == m ) |
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| 253 | m = 1; /* nothing we can do */ |
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| 254 | |
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| 255 | gt_write(sc->sc_gt, I2C_REG_BaudRate, I2C_BaudRate(m-1, n-1)); |
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| 256 | |
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| 257 | if ( !sc->sc_inited ) { |
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| 258 | |
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| 259 | if ( _System_state_Is_up(_System_state_Get()) ) { |
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| 260 | rtems_irq_connect_data ii = { |
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| 261 | name: BSP_IRQ_I2C, |
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| 262 | hdl: gt_i2c_intr, |
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| 263 | on: 0, |
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| 264 | off: 0, |
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| 265 | isOn: 0 |
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| 266 | }; |
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| 267 | rtems_status_code err; |
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| 268 | /* synchronization semaphore */ |
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| 269 | err = rtems_semaphore_create( |
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| 270 | rtems_build_name('g','i','2','c'), |
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| 271 | 0, |
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| 272 | RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_LOCAL, |
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| 273 | 0, |
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| 274 | &sc->sc_sync); |
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| 275 | if ( err ) { |
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| 276 | sc->sc_sync = 0; |
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| 277 | return err; |
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| 278 | } |
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| 279 | if ( !BSP_install_rtems_irq_handler(&ii) ) { |
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| 280 | fprintf(stderr,"Unable to install interrupt handler\n"); |
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| 281 | rtems_semaphore_delete(sc->sc_sync); |
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| 282 | return RTEMS_INTERNAL_ERROR; |
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| 283 | } |
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| 284 | BSP_irq_set_priority(BSP_IRQ_I2C, BSP_IRQ_MIN_PRIO); |
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| 285 | sc->sc_inited = 1; |
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| 286 | } else { |
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| 287 | } |
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| 288 | } else { |
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| 289 | rtems_semaphore_flush(sc->sc_sync); |
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| 290 | } |
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| 291 | return RTEMS_SUCCESSFUL; |
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| 292 | } |
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| 293 | |
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| 294 | STATIC rtems_status_code |
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| 295 | gt_i2c_send_start(rtems_libi2c_bus_t *bh) |
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| 296 | { |
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| 297 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 298 | |
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| 299 | return gt_i2c_wait(sc, I2C_Control_Start, I2C_Status_Started); |
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| 300 | } |
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| 301 | |
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| 302 | STATIC rtems_status_code |
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| 303 | gt_i2c_send_stop(rtems_libi2c_bus_t *bh) |
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| 304 | { |
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| 305 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 306 | uint32_t data; |
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| 307 | |
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| 308 | data = gt_read(sc->sc_gt, I2C_REG_Status); |
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| 309 | if ( I2C_Status_Started == data || I2C_Status_ReStarted == data ) { |
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| 310 | /* According to the spec, a void message (start - stop sequence) |
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| 311 | * is illegal and indeed, the chip plays bad tricks with us, i.e., |
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| 312 | * sometimes it hangs the bus so that it remains idle forever. |
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| 313 | * so we have to address someone... |
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| 314 | */ |
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| 315 | gt_i2c_send_addr(bh, /*just something... */ 8, 1); |
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| 316 | data = gt_read(sc->sc_gt, I2C_REG_Status); |
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| 317 | } |
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| 318 | |
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| 319 | if ( I2C_Status_AddrReadAck == data ) { |
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| 320 | /* Another thing: spec says that the master generates stop only after |
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| 321 | * not acknowledging the last byte. Again, the chip doesn't like |
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| 322 | * to be stopped in this condition - hence we just do it the favor |
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| 323 | * and read a single byte... |
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| 324 | */ |
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| 325 | gt_i2c_read_bytes(bh, (unsigned char *)&data, 1); |
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| 326 | } |
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| 327 | |
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| 328 | gt_write(sc->sc_gt, I2C_REG_Control, I2C_Control_Stop | sc->sc_cntl); |
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| 329 | |
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| 330 | /* should we poll for idle? There seems to be in IRQ when this completes */ |
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| 331 | return RTEMS_SUCCESSFUL; |
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| 332 | } |
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| 333 | |
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| 334 | STATIC rtems_status_code |
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| 335 | gt_i2c_send_addr(rtems_libi2c_bus_t *bh, uint32_t addr, int rw) |
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| 336 | { |
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| 337 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 338 | uint32_t data, wanted_status; |
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| 339 | uint8_t read_mask = rw ? 1 : 0; |
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| 340 | rtems_status_code error; |
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| 341 | |
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| 342 | if (read_mask) { |
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| 343 | wanted_status = I2C_Status_AddrReadAck; |
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| 344 | } else { |
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| 345 | wanted_status = I2C_Status_AddrWriteAck; |
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| 346 | } |
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| 347 | /* |
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| 348 | * First byte contains whether this xfer is a read or write. |
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| 349 | */ |
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| 350 | data = read_mask; |
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| 351 | if (addr > 0x7f) { |
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| 352 | /* |
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| 353 | * If this is a 10bit request, the first address byte is |
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| 354 | * 0b11110<b9><b8><r/w>. |
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| 355 | */ |
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| 356 | data |= 0xf0 | ((addr & 0x300) >> 7); |
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| 357 | gt_write(sc->sc_gt, I2C_REG_Data, data); |
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| 358 | error = gt_i2c_wait(sc, 0, wanted_status); |
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| 359 | if (error) |
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| 360 | return error; |
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| 361 | /* |
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| 362 | * The first address byte has been sent, now to send |
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| 363 | * the second one. |
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| 364 | */ |
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| 365 | if (read_mask) { |
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| 366 | wanted_status = I2C_Status_2ndAddrReadAck; |
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| 367 | } else { |
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| 368 | wanted_status = I2C_Status_2ndAddrWriteAck; |
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| 369 | } |
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| 370 | data = (uint8_t) addr; |
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| 371 | } else { |
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| 372 | data |= (addr << 1); |
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| 373 | } |
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| 374 | |
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| 375 | gt_write(sc->sc_gt, I2C_REG_Data, data); |
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| 376 | return gt_i2c_wait(sc, 0, wanted_status); |
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| 377 | } |
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| 378 | |
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| 379 | STATIC int |
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| 380 | gt_i2c_read_bytes(rtems_libi2c_bus_t *bh, unsigned char *buf, int len) |
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| 381 | { |
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| 382 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 383 | rtems_status_code error; |
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| 384 | register unsigned char *p=buf; |
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| 385 | |
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| 386 | while ( len-- > 0 ) { |
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| 387 | error = gt_i2c_wait( |
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| 388 | sc, |
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| 389 | len ? I2C_Control_ACK : 0, |
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| 390 | len ? I2C_Status_MasterReadAck : I2C_Status_MasterReadNoAck); |
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| 391 | if ( error ) { |
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| 392 | return -error; |
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| 393 | } |
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| 394 | *p++ = gt_read(sc->sc_gt, I2C_REG_Data); |
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| 395 | } |
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| 396 | |
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| 397 | return p-buf; |
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| 398 | } |
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| 399 | |
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| 400 | STATIC int |
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| 401 | gt_i2c_write_bytes(rtems_libi2c_bus_t *bh, unsigned char *buf, int len) |
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| 402 | { |
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| 403 | struct gti2c_softc * const sc = &((gti2c_desc)bh)->pvt; |
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| 404 | int rval = 0; |
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| 405 | rtems_status_code error; |
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| 406 | |
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| 407 | while ( len-- > 0 ) { |
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| 408 | gt_write(sc->sc_gt, I2C_REG_Data, buf[rval]); |
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| 409 | error = gt_i2c_wait(sc, 0, I2C_Status_MasterWriteAck); |
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| 410 | if ( error ) { |
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| 411 | return -error; |
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| 412 | } |
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| 413 | rval++; |
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| 414 | } |
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| 415 | |
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| 416 | return rval; |
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| 417 | } |
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| 418 | |
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| 419 | rtems_libi2c_bus_t *gt64260_i2c_bus_descriptor = &my_bus_tbl.bus_desc; |
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| 420 | |
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| 421 | #ifdef DEBUG_MODULAR |
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| 422 | |
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| 423 | void |
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| 424 | _cexpModuleInitialize(void *arg) |
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| 425 | { |
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| 426 | gt_i2c_init(>64260_i2c_bus_descriptor->bus_desc); |
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| 427 | } |
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| 428 | |
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| 429 | int |
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| 430 | _cexpModuleFinalize(void * arg) |
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| 431 | { |
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| 432 | struct gti2c_softc * const sc = >64260_i2c_bus_descriptor->pvt; |
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| 433 | |
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| 434 | rtems_irq_connect_data ii = { |
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| 435 | name: BSP_IRQ_I2C, |
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| 436 | hdl: gt_i2c_intr, |
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| 437 | on: noop, |
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| 438 | off: noop, |
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| 439 | isOn: inoop |
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| 440 | }; |
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| 441 | |
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| 442 | rtems_semaphore_delete(sc->sc_sync); |
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| 443 | |
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| 444 | return !BSP_remove_rtems_irq_handler(&ii); |
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| 445 | } |
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| 446 | |
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| 447 | #endif |
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