1 | /* Interrupt driver + dispatcher for the discovery host controller */ |
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2 | |
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3 | /* Author: T. Straumann, 2005-2007 |
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4 | * |
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5 | * Acknowledgements: |
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6 | * Valuable information was obtained from the following drivers |
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7 | * netbsd: (C) Allegro Networks Inc; Wasabi Systems Inc. |
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8 | * linux: (C) MontaVista, Software, Inc; Chris Zankel, Mark A. Greer. |
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9 | * rtems: (C) Brookhaven National Laboratory; K. Feng |
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10 | * but this implementation is original work by the author. |
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11 | */ |
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12 | |
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13 | /* |
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14 | * Authorship |
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15 | * ---------- |
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16 | * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was |
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17 | * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, |
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18 | * Stanford Linear Accelerator Center, Stanford University. |
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19 | * |
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20 | * Acknowledgement of sponsorship |
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21 | * ------------------------------ |
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22 | * The 'beatnik' BSP was produced by |
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23 | * the Stanford Linear Accelerator Center, Stanford University, |
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24 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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25 | * |
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26 | * Government disclaimer of liability |
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27 | * ---------------------------------- |
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28 | * Neither the United States nor the United States Department of Energy, |
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29 | * nor any of their employees, makes any warranty, express or implied, or |
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30 | * assumes any legal liability or responsibility for the accuracy, |
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31 | * completeness, or usefulness of any data, apparatus, product, or process |
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32 | * disclosed, or represents that its use would not infringe privately owned |
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33 | * rights. |
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34 | * |
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35 | * Stanford disclaimer of liability |
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36 | * -------------------------------- |
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37 | * Stanford University makes no representations or warranties, express or |
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38 | * implied, nor assumes any liability for the use of this software. |
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39 | * |
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40 | * Stanford disclaimer of copyright |
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41 | * -------------------------------- |
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42 | * Stanford University, owner of the copyright, hereby disclaims its |
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43 | * copyright and all other rights in this software. Hence, anyone may |
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44 | * freely use it for any purpose without restriction. |
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45 | * |
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46 | * Maintenance of notices |
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47 | * ---------------------- |
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48 | * In the interest of clarity regarding the origin and status of this |
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49 | * SLAC software, this and all the preceding Stanford University notices |
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50 | * are to remain affixed to any copy or derivative of this software made |
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51 | * or distributed by the recipient and are to be affixed to any copy of |
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52 | * software made or distributed by the recipient that contains a copy or |
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53 | * derivative of this software. |
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54 | * |
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55 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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56 | */ |
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57 | #include <rtems.h> |
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58 | #include <bsp.h> |
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59 | #include <bsp/irq.h> |
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60 | #include <bsp/gtreg.h> |
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61 | #include <bsp/gtintrreg.h> |
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62 | #include <rtems/bspIo.h> |
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63 | #include <bsp/vectors.h> |
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64 | #include <libcpu/byteorder.h> |
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65 | #include <libcpu/spr.h> |
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66 | |
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67 | /* dont change the order (main_lo, main_hi, gpp) which |
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68 | * matches the interrupt numbers! |
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69 | */ |
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70 | #define MAIN_LO_IDX 0 |
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71 | #define MAIN_HI_IDX 1 |
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72 | #define GPP_IDX 2 |
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73 | #define NUM_INTR_REGS 3 |
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74 | |
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75 | |
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76 | #define SYNC() __asm__ volatile("sync") |
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77 | |
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78 | /* How many times should the ISR dispatcher check for |
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79 | * pending interrupts until it decides that something's |
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80 | * fishy (i.e., a user ISR fails to clear the interrupt |
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81 | * source) |
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82 | */ |
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83 | #define MAX_SPIN_LOOPS 100 |
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84 | |
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85 | /* If FASTER is defined, a few obscure I/O statements found in the linux |
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86 | * driver are removed |
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87 | */ |
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88 | #define FASTER |
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89 | |
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90 | /* Array helper */ |
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91 | #define NumberOf(arr) (sizeof(arr)/sizeof((arr)[0])) |
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92 | |
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93 | |
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94 | /* MVME6100 specific; re-define watchdog NMI pin to be a normal output |
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95 | * so we have a way to raise an interrupt in software (GPP[26] is wired to |
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96 | * GPP[6] on the MVME6100). |
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97 | */ |
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98 | #define MVME6100_IRQ_DEBUG 4 |
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99 | |
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100 | #define GPP_WIRED_OUT_BIT_6100 26 /* CAVEAT: this is bit 26 on the 6100 */ |
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101 | #define GPP_WIRED_OUT_BIT_5500 24 /* CAVEAT: this is bit 24 on the 5500 */ |
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102 | #define GPP_WIRED_IN_BIT 6 |
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103 | |
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104 | /* Ored mask of debugging features to enable */ |
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105 | #define IRQ_DEBUG_BASIC 1 |
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106 | /* This is _very_ lowlevel */ |
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107 | #define IRQ_DEBUG_DISPATCHER 2 |
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108 | /* Record maximal dispatching latency */ |
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109 | #define IRQ_DEBUG_MAXLAT 8 /* PPC only */ |
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110 | |
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111 | #define IRQ_DEBUG (0 /*|(IRQ_DEBUG_BASIC)*/|(MVME6100_IRQ_DEBUG)|(IRQ_DEBUG_MAXLAT)) |
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112 | |
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113 | /********** |
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114 | * Typedefs |
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115 | **********/ |
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116 | |
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117 | /* Set of the three relevant cause registers */ |
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118 | typedef volatile unsigned IrqMask[NUM_INTR_REGS]; |
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119 | |
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120 | #define REGP(x) ((volatile uint32_t *)(x)) |
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121 | |
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122 | /* Information we keep about the PIC */ |
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123 | typedef struct _Mv64x60PicRec { |
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124 | /* base address as seen from CPU */ |
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125 | uintptr_t reg_base; |
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126 | |
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127 | /* addresses of 'cause' registers */ |
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128 | volatile uint32_t *causes[NUM_INTR_REGS]; |
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129 | |
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130 | /* addresses of 'mask' registers */ |
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131 | volatile uint32_t *masks[NUM_INTR_REGS]; |
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132 | |
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133 | /* masks for all priorities. If an |
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134 | * interrupt source has priority X, |
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135 | * its corresponding bit is set |
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136 | * (enabled) in mcache[i] for all |
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137 | * i < X and cleared for i >= X |
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138 | */ |
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139 | volatile IrqMask mcache[BSP_IRQ_MAX_PRIO+1]; |
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140 | |
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141 | /* Priority we're executing at. |
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142 | * Thread-level is priority 0, |
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143 | * ISRs range from 1..MAX_PRIO |
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144 | */ |
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145 | volatile rtems_irq_prio current_priority; |
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146 | } Mv64x60PicRec, *Mv64x60Pic; |
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147 | |
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148 | /********** |
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149 | * Globals |
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150 | **********/ |
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151 | |
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152 | |
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153 | /* Copy of the configuration */ |
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154 | static rtems_irq_global_settings theConfig; |
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155 | /* PIC description */ |
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156 | static Mv64x60PicRec thePic; |
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157 | |
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158 | #if (IRQ_DEBUG) & MVME6100_IRQ_DEBUG |
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159 | static unsigned long gpp_out_bit = 0; |
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160 | #endif |
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161 | |
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162 | #if (IRQ_DEBUG) & IRQ_DEBUG_MAXLAT |
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163 | unsigned long discovery_pic_max_dispatching_latency = 0; |
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164 | #ifdef __PPC__ |
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165 | static inline unsigned long mftb(void) |
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166 | { |
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167 | unsigned long rval; |
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168 | asm volatile("mftb %0":"=r"(rval)); |
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169 | return rval; |
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170 | } |
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171 | #else |
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172 | #define mftb() 0 |
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173 | #endif |
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174 | #endif |
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175 | |
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176 | /********** |
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177 | * Functions |
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178 | **********/ |
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179 | |
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180 | /* Debugging helper routines */ |
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181 | static void pregs(volatile uint32_t **p) |
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182 | { |
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183 | int i; |
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184 | for (i=NUM_INTR_REGS-1; i>=0; i--) { |
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185 | printk(" 0x%08x", ld_le32(p[i])); |
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186 | printk( i ? " --":"\n"); |
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187 | } |
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188 | } |
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189 | |
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190 | static void pmsks(volatile IrqMask p) |
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191 | { |
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192 | int i; |
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193 | for (i=NUM_INTR_REGS-1; i>=0; i--) { |
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194 | printk(" 0x%08x", p[i]); |
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195 | printk( i ? " --":"\n"); |
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196 | } |
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197 | } |
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198 | |
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199 | static void discovery_dump_picregs(void) |
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200 | { |
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201 | printk(" ..GPP_IRQ. -- ..MAIN_HI. -- ..MAIN_LO.\n"); |
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202 | printk("Cause:"); pregs(thePic.causes); |
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203 | printk("Mask: "); pregs(thePic.masks); |
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204 | } |
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205 | |
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206 | /* Small inline helpers */ |
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207 | |
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208 | /* return 0 if this PIC is not 'responsible' for a given irq number |
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209 | * we also 'ignore' the GPP summary bits - these must always remain |
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210 | * enabled. |
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211 | */ |
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212 | static inline int |
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213 | validIrqNo(rtems_irq_number irq) |
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214 | { |
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215 | return |
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216 | irq >= BSP_PCI_IRQ_LOWEST_OFFSET |
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217 | && irq <= BSP_PCI_IRQ_MAX_OFFSET |
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218 | && ! (IMH_GPP_SUM & (1<<(irq-32))); |
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219 | } |
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220 | |
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221 | /* return 0 if a given priority is outside the valid range */ |
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222 | static inline int |
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223 | validPri(rtems_irq_prio pri) |
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224 | { |
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225 | /* silence compiler warning about limited range of type; |
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226 | * hope it never changes... |
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227 | */ |
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228 | return /* pri>=0 && */ pri <=BSP_IRQ_MAX_PRIO; |
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229 | } |
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230 | |
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231 | /* Return position of the most significant bit that is set in 'x' */ |
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232 | static inline int |
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233 | __ilog2(unsigned x) |
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234 | { |
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235 | asm volatile("cntlzw %0, %0":"=&r"(x):"0"(x)); |
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236 | return 31-x; |
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237 | } |
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238 | |
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239 | /* Convert irq number to cause register index |
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240 | * (array of handles in the PicRec). |
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241 | * ASSUMES: 'irq' within valid range. |
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242 | */ |
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243 | static inline unsigned |
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244 | irqDiv32(unsigned irq) |
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245 | { |
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246 | return (irq-BSP_PCI_IRQ_LOWEST_OFFSET)>>5; |
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247 | } |
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248 | |
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249 | /* Convert irq number to cause/mask bit number. |
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250 | * ASSUMES: 'irq' within valid range. |
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251 | */ |
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252 | |
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253 | static inline unsigned |
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254 | irqMod32(unsigned irq) |
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255 | { |
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256 | return (irq-BSP_PCI_IRQ_LOWEST_OFFSET)&31; |
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257 | } |
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258 | |
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259 | /* NON-ATOMICALLY set/clear bits in a MV64x60 register |
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260 | * |
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261 | * register contents at offset 'off' are ANDed with |
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262 | * complement of the 'clr' mask and ORed with 'set' mask: |
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263 | * |
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264 | * *off = (*off & ~clr) | set |
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265 | * |
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266 | * ASSUMES: executed from IRQ-disabled section |
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267 | */ |
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268 | static inline void |
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269 | gt_bitmod(unsigned off, unsigned set, unsigned clr) |
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270 | { |
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271 | st_le32(REGP(thePic.reg_base + off), |
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272 | (ld_le32(REGP(thePic.reg_base+off)) & ~clr) | set); |
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273 | } |
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274 | |
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275 | static inline unsigned |
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276 | gt_read(unsigned off) |
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277 | { |
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278 | return ld_le32(REGP(thePic.reg_base + off)); |
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279 | } |
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280 | |
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281 | static inline void |
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282 | gt_write(unsigned off, unsigned val) |
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283 | { |
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284 | st_le32(REGP(thePic.reg_base + off), val); |
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285 | } |
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286 | |
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287 | /* Enable interrupt number 'irq' at the PIC. |
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288 | * |
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289 | * Checks for valid arguments but has no way of |
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290 | * communicating violation; prints to console |
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291 | * if illegal arguments are given. |
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292 | * |
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293 | * This routine may be called from ISR level. |
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294 | * |
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295 | * Algorithm: set corresponding bit in masks |
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296 | * for all priorities lower than the |
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297 | * target irq's priority and push |
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298 | * mask for the currently executing |
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299 | * priority out to the PIC. |
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300 | */ |
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301 | |
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302 | void |
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303 | BSP_enable_irq_at_pic(rtems_irq_number irq) |
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304 | { |
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305 | unsigned i,j; |
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306 | unsigned long flags; |
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307 | volatile uint32_t *p; |
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308 | uint32_t v,m; |
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309 | |
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310 | if ( !validIrqNo(irq) ) { |
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311 | /* API change - must silently ignore... |
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312 | printk("BSP_enable_irq_at_pic: Invalid argument (irq #%i)\n",irq); |
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313 | */ |
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314 | return; |
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315 | } |
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316 | |
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317 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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318 | printk("IRQ: Enable #%i;",irq); |
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319 | #endif |
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320 | |
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321 | if ( (i=irqDiv32(irq)) > NUM_INTR_REGS ) { |
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322 | /* This is probably a more serious error; don't ignore silently */ |
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323 | printk("BSP_enable_irq_at_pic: illegal argument\n"); |
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324 | return; |
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325 | } |
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326 | /* compute register pointer and bit mask */ |
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327 | p = thePic.masks[i]; |
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328 | m = 1<<irqMod32(irq); |
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329 | |
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330 | rtems_interrupt_disable(flags); |
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331 | { |
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332 | /* access table from protected section to be thread-safe */ |
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333 | rtems_irq_prio pri = theConfig.irqPrioTbl[irq]; |
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334 | for ( j=0; j<pri; j++ ) { |
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335 | thePic.mcache[j][i] |= m; |
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336 | } |
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337 | st_le32(p, (v=thePic.mcache[thePic.current_priority][i])); |
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338 | /* linux driver reads back GPP mask; maybe it's wise to do the same */ |
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339 | (void)ld_le32(thePic.masks[GPP_IDX]); |
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340 | } |
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341 | SYNC(); |
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342 | rtems_interrupt_enable(flags); |
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343 | |
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344 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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345 | printk(" Mask[%i]: 0x%08x -> 0x%08x\n",i,v,ld_le32(p)); |
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346 | |
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347 | #endif |
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348 | } |
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349 | |
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350 | /* Disable interrupt number 'irq' at the PIC. |
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351 | * |
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352 | * Checks for valid arguments but has no way of |
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353 | * communicating violation; prints to console |
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354 | * if illegal arguments are given. |
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355 | * |
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356 | * This routine may be called from ISR level. |
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357 | * |
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358 | * Algorithm: clear corresponding bit in masks |
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359 | * for all priorities and push the |
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360 | * mask for the currently executing |
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361 | * priority out to the PIC. |
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362 | */ |
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363 | |
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364 | int |
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365 | BSP_disable_irq_at_pic(rtems_irq_number irq) |
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366 | { |
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367 | unsigned i,j; |
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368 | unsigned long flags; |
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369 | volatile uint32_t *p; |
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370 | uint32_t v,m; |
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371 | int rval; |
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372 | |
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373 | if ( !validIrqNo(irq) ) { |
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374 | /* API change - must silently ignore... |
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375 | printk("BSP_disable_irq_at_pic: Invalid argument (irq #%i)\n",irq); |
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376 | */ |
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377 | return -1; |
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378 | } |
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379 | |
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380 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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381 | printk("IRQ: Disable #%i;",irq); |
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382 | #endif |
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383 | |
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384 | if ( (i=irqDiv32(irq)) > NUM_INTR_REGS ) { |
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385 | /* This is probably a more serious error; don't ignore silently */ |
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386 | printk("BSP_enable_irq_at_pic: illegal argument\n"); |
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387 | return -1; |
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388 | } |
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389 | |
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390 | /* compute register pointer and bit mask */ |
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391 | p = thePic.masks[i]; |
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392 | m = (1<<irqMod32(irq)); |
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393 | |
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394 | rtems_interrupt_disable(flags); |
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395 | { |
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396 | rval = thePic.mcache[thePic.current_priority][i] & m; |
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397 | for (j=0; j<=BSP_IRQ_MAX_PRIO; j++) |
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398 | thePic.mcache[j][i] &= ~m; |
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399 | st_le32(p, (v=thePic.mcache[thePic.current_priority][i])); |
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400 | /* linux driver reads back GPP mask; maybe it's wise to do the same */ |
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401 | (void)ld_le32(thePic.masks[GPP_IDX]); |
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402 | } |
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403 | SYNC(); |
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404 | rtems_interrupt_enable(flags); |
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405 | |
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406 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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407 | printk(" Mask[%i]: 0x%08x -> 0x%08x\n",i,v,ld_le32(p)); |
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408 | #endif |
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409 | |
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410 | return rval ? 1 : 0; |
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411 | } |
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412 | |
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413 | int |
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414 | BSP_irq_is_enabled_at_pic(rtems_irq_number irq) |
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415 | { |
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416 | unsigned i; |
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417 | if ( !validIrqNo(irq) ) { |
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418 | printk("BSP_irq_is_enabled_at_pic: Invalid argument (irq #%i)\n",irq); |
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419 | return -1; |
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420 | } |
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421 | |
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422 | if ( (i=irqDiv32(irq)) > NUM_INTR_REGS ) { |
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423 | printk("BSP_enable_irq_at_pic: illegal argument\n"); |
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424 | return -1; |
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425 | } |
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426 | return ld_le32(thePic.masks[i]) & (1<<irqMod32(irq)) ? 1 : 0; |
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427 | } |
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428 | |
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429 | |
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430 | /* Change priority of interrupt number 'irq' to 'pri' |
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431 | * |
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432 | * RETURNS: 0 on success, nonzero on failure (illegal args) |
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433 | * |
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434 | * NOTE: This routine must not be called from ISR level. |
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435 | * |
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436 | * Algorithm: Set bit corresponding to 'irq' in the masks for |
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437 | * all priorities < pri and clear in all masks |
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438 | * for priorities >=pri |
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439 | */ |
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440 | int |
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441 | BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri) |
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442 | { |
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443 | unsigned long flags; |
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444 | volatile uint32_t *p; |
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445 | uint32_t v,m; |
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446 | unsigned i,j; |
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447 | |
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448 | if ( thePic.current_priority > 0 ) { |
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449 | printk("BSP_irq_set_priority: must not be called from ISR level\n"); |
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450 | return -1; |
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451 | } |
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452 | |
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453 | if ( !validPri(pri) ) { |
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454 | printk("BSP_irq_set_priority: invalid argument (pri #%i)\n",pri); |
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455 | return -1; |
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456 | } |
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457 | |
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458 | if ( BSP_DECREMENTER != irq ) { |
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459 | if ( !validIrqNo(irq) ) { |
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460 | printk("BSP_irq_set_priority: invalid argument (irq #%i)\n",irq); |
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461 | return -1; |
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462 | } |
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463 | |
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464 | if ( (i=irqDiv32(irq)) > NUM_INTR_REGS ) { |
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465 | printk("BSP_irq_set_priority: illegal argument (irq #%i not PCI?)\n", irq); |
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466 | return -1; |
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467 | } |
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468 | } |
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469 | |
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470 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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471 | printk("IRQ: Set Priority #%i -> %i;",irq,pri); |
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472 | #endif |
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473 | |
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474 | if ( BSP_DECREMENTER == irq ) { |
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475 | theConfig.irqPrioTbl[irq] = pri; |
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476 | return 0; |
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477 | } |
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478 | |
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479 | /* compute register pointer and bit mask */ |
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480 | p = thePic.masks[i]; |
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481 | m = 1<<irqMod32(irq); |
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482 | |
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483 | rtems_interrupt_disable(flags); |
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484 | { |
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485 | for (j=0; j<=BSP_IRQ_MAX_PRIO; j++) { |
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486 | if ( j<pri ) |
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487 | thePic.mcache[j][i] |= m; |
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488 | else |
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489 | thePic.mcache[j][i] &= ~m; |
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490 | } |
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491 | theConfig.irqPrioTbl[irq] = pri; |
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492 | st_le32(p, (v=thePic.mcache[thePic.current_priority][i])); |
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493 | /* linux driver reads back GPP mask; maybe it's wise to do the same */ |
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494 | (void)ld_le32(thePic.masks[GPP_IDX]); |
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495 | } |
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496 | SYNC(); |
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497 | rtems_interrupt_enable(flags); |
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498 | |
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499 | #if (IRQ_DEBUG) & IRQ_DEBUG_BASIC |
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500 | printk(" Mask[%i]: 0x%08x -> 0x%08x\n",i,v,ld_le32(p)); |
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501 | #endif |
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502 | |
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503 | return 0; |
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504 | } |
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505 | |
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506 | /* Initialize the PIC; routine needed by BSP framework |
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507 | * |
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508 | * RETURNS: NONZERO on SUCCESS, 0 on error! |
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509 | */ |
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510 | int |
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511 | BSP_setup_the_pic(rtems_irq_global_settings* config) |
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512 | { |
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513 | int i; |
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514 | /* |
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515 | * Store copy of configuration |
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516 | */ |
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517 | theConfig = *config; |
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518 | |
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519 | /* check config */ |
---|
520 | if ( theConfig.irqNb <= BSP_PCI_IRQ_MAX_OFFSET ) { |
---|
521 | printk("BSP_setup_the_pic: FATAL ERROR: configured IRQ table too small???\n"); |
---|
522 | return 0; |
---|
523 | } |
---|
524 | |
---|
525 | for ( i=0; i<theConfig.irqNb; i++ ) { |
---|
526 | if ( !validPri(theConfig.irqPrioTbl[i]) ) { |
---|
527 | printk("BSP_setup_the_pic: invalid priority (%i) for irg #%i; setting to 1\n", theConfig.irqPrioTbl[i], i); |
---|
528 | theConfig.irqPrioTbl[i]=1; |
---|
529 | } |
---|
530 | } |
---|
531 | |
---|
532 | /* TODO: Detect; Switch wired-out bit; */ |
---|
533 | thePic.reg_base = BSP_MV64x60_BASE; |
---|
534 | |
---|
535 | thePic.current_priority = 0; |
---|
536 | |
---|
537 | #if (IRQ_DEBUG) & MVME6100_IRQ_DEBUG |
---|
538 | #endif |
---|
539 | |
---|
540 | switch ( BSP_getDiscoveryVersion(/* assert */ 1) ) { |
---|
541 | case MV_64360: |
---|
542 | thePic.causes[MAIN_LO_IDX] = REGP(thePic.reg_base + ICR_360_MIC_LO); |
---|
543 | thePic.causes[MAIN_HI_IDX] = REGP(thePic.reg_base + ICR_360_MIC_HI); |
---|
544 | thePic.masks[MAIN_LO_IDX] = REGP(thePic.reg_base + ICR_360_C0IM_LO); |
---|
545 | thePic.masks[MAIN_HI_IDX] = REGP(thePic.reg_base + ICR_360_C0IM_HI); |
---|
546 | break; |
---|
547 | |
---|
548 | case GT_64260_A: |
---|
549 | case GT_64260_B: |
---|
550 | thePic.causes[MAIN_LO_IDX] = REGP(thePic.reg_base + ICR_260_MIC_LO); |
---|
551 | thePic.causes[MAIN_HI_IDX] = REGP(thePic.reg_base + ICR_260_MIC_HI); |
---|
552 | thePic.masks[MAIN_LO_IDX] = REGP(thePic.reg_base + ICR_260_CIM_LO); |
---|
553 | thePic.masks[MAIN_HI_IDX] = REGP(thePic.reg_base + ICR_260_CIM_HI); |
---|
554 | break; |
---|
555 | |
---|
556 | default: |
---|
557 | rtems_panic("Unable to initialize interrupt controller; unknown chip"); |
---|
558 | break; |
---|
559 | } |
---|
560 | |
---|
561 | thePic.causes[GPP_IDX] = REGP(thePic.reg_base + GT_GPP_Interrupt_Cause); |
---|
562 | thePic.masks[GPP_IDX] = REGP(thePic.reg_base + GT_GPP_Interrupt_Mask); |
---|
563 | |
---|
564 | /* Initialize mask cache */ |
---|
565 | for ( i=0; i<=BSP_IRQ_MAX_PRIO; i++ ) { |
---|
566 | thePic.mcache[i][MAIN_LO_IDX] = 0; |
---|
567 | /* Always enable the summary bits. Otherwise, GPP interrupts dont |
---|
568 | * make it 'through' to the GPP cause |
---|
569 | */ |
---|
570 | thePic.mcache[i][MAIN_HI_IDX] = IMH_GPP_SUM; |
---|
571 | thePic.mcache[i][GPP_IDX] = 0; |
---|
572 | } |
---|
573 | |
---|
574 | /* mask and clear everything */ |
---|
575 | for ( i=0; i<NUM_INTR_REGS; i++ ) { |
---|
576 | st_le32(thePic.causes[i], 0); |
---|
577 | st_le32(thePic.masks[i], 0); |
---|
578 | } |
---|
579 | |
---|
580 | /* make sure GPP Irqs are level sensitive */ |
---|
581 | gt_bitmod( |
---|
582 | GT_CommUnitArb_Ctrl, /* reg */ |
---|
583 | GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive, /* set */ |
---|
584 | 0); /* clr */ |
---|
585 | |
---|
586 | /* enable summaries */ |
---|
587 | st_le32(thePic.masks[MAIN_LO_IDX], thePic.mcache[thePic.current_priority][MAIN_LO_IDX]); |
---|
588 | st_le32(thePic.masks[MAIN_HI_IDX], thePic.mcache[thePic.current_priority][MAIN_HI_IDX]); |
---|
589 | st_le32(thePic.masks[GPP_IDX ], thePic.mcache[thePic.current_priority][GPP_IDX ]); |
---|
590 | |
---|
591 | /* believe the interrupts are all level sensitive (which is good); we leave all the |
---|
592 | * inputs configured they way the are by MotLoad... |
---|
593 | */ |
---|
594 | |
---|
595 | /* Finally, enable all interrupts for which the configuration table has already |
---|
596 | * a handler installed. |
---|
597 | */ |
---|
598 | for ( i=BSP_PCI_IRQ_LOWEST_OFFSET; i<=BSP_PCI_IRQ_MAX_OFFSET; i++ ) { |
---|
599 | if ( theConfig.irqHdlTbl[i].hdl != theConfig.defaultEntry.hdl ) { |
---|
600 | BSP_enable_irq_at_pic(i); |
---|
601 | } |
---|
602 | } |
---|
603 | |
---|
604 | return 1; |
---|
605 | } |
---|
606 | |
---|
607 | int discovery_pic_max_loops = 0; |
---|
608 | |
---|
609 | |
---|
610 | /* Change the priority level we're executing at and mask all interrupts of |
---|
611 | * the same and lower priorities |
---|
612 | * |
---|
613 | * RETURNS old priority; |
---|
614 | */ |
---|
615 | |
---|
616 | static inline rtems_irq_prio |
---|
617 | change_executing_prio_level(rtems_irq_prio pri) |
---|
618 | { |
---|
619 | register rtems_irq_prio rval = thePic.current_priority; |
---|
620 | thePic.current_priority = pri; |
---|
621 | st_le32(thePic.masks[MAIN_LO_IDX], thePic.mcache[pri][MAIN_LO_IDX]); |
---|
622 | st_le32(thePic.masks[MAIN_HI_IDX], thePic.mcache[pri][MAIN_HI_IDX]); |
---|
623 | st_le32(thePic.masks[GPP_IDX ], thePic.mcache[pri][GPP_IDX ]); |
---|
624 | /* this DOES seem to be necessary */ |
---|
625 | (void)ld_le32(thePic.masks[GPP_IDX]); |
---|
626 | return rval; |
---|
627 | } |
---|
628 | |
---|
629 | /* Scan the three cause register and find the pending interrupt with |
---|
630 | * the highest priority. |
---|
631 | * |
---|
632 | * Two facts make this quite efficient |
---|
633 | * a) the PPC has an opcode for finding the number of leading zero-bits |
---|
634 | * in a register (__ilog2()). |
---|
635 | * b) as we proceed we mask all sources of equal or lower priorites; they won't be |
---|
636 | * seen while scanning: |
---|
637 | * |
---|
638 | * maxpri = 0; |
---|
639 | * bits = in_le32(cause); |
---|
640 | * while ( bits &= mask[maxpri] ) { |
---|
641 | * irq_no = __ilog2(bits); |
---|
642 | * maxpri = priority[irq_no]; |
---|
643 | * } |
---|
644 | * |
---|
645 | * a) __ilog() is 1-2 machine instructions |
---|
646 | * b) while loop is only executed as many times as interrupts of different |
---|
647 | * priorities are pending at the same time (and only if lower-priority |
---|
648 | * ones are found first; otherwise, the iteration terminates quicker). |
---|
649 | * |
---|
650 | * ==> highest priority source is found quickly. It takes at most |
---|
651 | * |
---|
652 | * BSP_IRQ_MAX_PRIO * ( ~3 reg-only instructions + 2 memory access ) |
---|
653 | * + 2 reg-only instructions + 1 I/O + 1 memory access. |
---|
654 | * |
---|
655 | * |
---|
656 | */ |
---|
657 | |
---|
658 | static unsigned mlc, mhc, gpc; |
---|
659 | |
---|
660 | static int decrementerPending = 0; |
---|
661 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
662 | int decrementerIrqs = 0; |
---|
663 | #endif |
---|
664 | |
---|
665 | static inline unsigned |
---|
666 | find_highest_priority_pending_irq(rtems_irq_prio *ppri) |
---|
667 | { |
---|
668 | register int rval = -1; |
---|
669 | register rtems_irq_prio *pt = theConfig.irqPrioTbl + BSP_PCI_IRQ_LOWEST_OFFSET; |
---|
670 | register rtems_irq_prio pmax = *ppri; |
---|
671 | register unsigned cse,ocse; |
---|
672 | |
---|
673 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
674 | discovery_dump_picregs(); |
---|
675 | #endif |
---|
676 | |
---|
677 | if ( decrementerPending ) { |
---|
678 | /* Don't flood |
---|
679 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
680 | printk("Decrementer IRQ pending\n"); |
---|
681 | #endif |
---|
682 | */ |
---|
683 | if ( theConfig.irqPrioTbl[BSP_DECREMENTER] > pmax ) { |
---|
684 | pmax = theConfig.irqPrioTbl[BSP_DECREMENTER]; |
---|
685 | rval = BSP_DECREMENTER; |
---|
686 | } |
---|
687 | } |
---|
688 | |
---|
689 | mlc = cse = ld_le32(thePic.causes[MAIN_LO_IDX]); |
---|
690 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
691 | printk("MAIN_LO; cse: 0x%08x, msk 0x%08x\n", cse ,thePic.mcache[pmax][MAIN_LO_IDX]); |
---|
692 | #endif |
---|
693 | while ( cse &= thePic.mcache[pmax][MAIN_LO_IDX] ) { |
---|
694 | rval = __ilog2(cse); |
---|
695 | pmax = pt[rval]; |
---|
696 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
697 | printk("Max pri IRQ now %i\n",rval); |
---|
698 | #endif |
---|
699 | } |
---|
700 | mhc = cse = ocse = ld_le32(thePic.causes[MAIN_HI_IDX]); |
---|
701 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
702 | printk("MAIN_HI; cse: 0x%08x, msk 0x%08x\n", cse, thePic.mcache[pmax][MAIN_HI_IDX]); |
---|
703 | #endif |
---|
704 | /* don't look at the GPP summary; only check for 'real' MAIN_HI sources */ |
---|
705 | cse &= ~IMH_GPP_SUM; |
---|
706 | while ( cse &= thePic.mcache[pmax][MAIN_HI_IDX] ) { |
---|
707 | rval = __ilog2(cse) + 32; |
---|
708 | pmax = pt[rval]; |
---|
709 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
710 | printk("Max pri IRQ now %i\n",rval); |
---|
711 | #endif |
---|
712 | } |
---|
713 | gpc = cse = ld_le32(thePic.causes[GPP_IDX ]); |
---|
714 | /* if there were GPP ints, scan the GPP cause now */ |
---|
715 | if ( ocse & IMH_GPP_SUM ) { |
---|
716 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
717 | printk("GPP; cse: 0x%08x, msk 0x%08x\n", cse, thePic.mcache[pmax][GPP_IDX ]); |
---|
718 | #endif |
---|
719 | cse &= thePic.mcache[pmax][GPP_IDX ]; |
---|
720 | ocse = cse; |
---|
721 | while ( cse ) { |
---|
722 | rval = __ilog2(cse) + 64; |
---|
723 | pmax = pt[rval]; |
---|
724 | cse &= thePic.mcache[pmax][GPP_IDX ]; |
---|
725 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
726 | printk("Max pri IRQ now %i\n",rval); |
---|
727 | #endif |
---|
728 | } |
---|
729 | #ifndef FASTER |
---|
730 | /* this doesn't seem to be necessary -- however, the linux people do it... */ |
---|
731 | out_le32(thePic.causes[GPP_IDX], ~ocse); |
---|
732 | #endif |
---|
733 | } |
---|
734 | #ifndef FASTER |
---|
735 | /* this doesn't seem to be necessary -- however, the linux people do it... */ |
---|
736 | (void)in_le32(thePic.causes[GPP_IDX]); |
---|
737 | #endif |
---|
738 | |
---|
739 | *ppri = pmax; |
---|
740 | |
---|
741 | if ( BSP_DECREMENTER == rval ) { |
---|
742 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
743 | decrementerIrqs++; |
---|
744 | #endif |
---|
745 | decrementerPending = 0; |
---|
746 | } |
---|
747 | |
---|
748 | return rval; |
---|
749 | } |
---|
750 | |
---|
751 | #if 0 /* TODO: should this be cleaned up ? */ |
---|
752 | #define _IRQ_DEBUG IRQ_DEBUG_DISPATCHER |
---|
753 | static inline unsigned |
---|
754 | ffind_highest_priority_pending_irq(rtems_irq_prio *ppri) |
---|
755 | { |
---|
756 | register int rval = -1; |
---|
757 | register rtems_irq_prio *pt = theConfig.irqPrioTbl + BSP_PCI_IRQ_LOWEST_OFFSET; |
---|
758 | register rtems_irq_prio pmax = *ppri; |
---|
759 | register unsigned cse,ocse; |
---|
760 | |
---|
761 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
762 | discovery_dump_picregs(); |
---|
763 | #endif |
---|
764 | |
---|
765 | cse = in_le32(thePic.causes[MAIN_LO_IDX]); |
---|
766 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
767 | printk("MAIN_LO; cse: 0x%08x, msk 0x%08x\n", cse ,thePic.mcache[pmax][MAIN_LO_IDX]); |
---|
768 | #endif |
---|
769 | while ( cse &= thePic.mcache[pmax][MAIN_LO_IDX] ) { |
---|
770 | rval = __ilog2(cse); |
---|
771 | pmax = pt[rval]; |
---|
772 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
773 | printk("Max pri IRQ now %i\n",rval); |
---|
774 | #endif |
---|
775 | } |
---|
776 | cse = ocse = in_le32(thePic.causes[MAIN_HI_IDX]); |
---|
777 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
778 | printk("MAIN_HI; cse: 0x%08x, msk 0x%08x\n", cse, thePic.mcache[pmax][MAIN_HI_IDX]); |
---|
779 | #endif |
---|
780 | /* don't look at the GPP summary; only check for 'real' MAIN_HI sources */ |
---|
781 | cse &= ~IMH_GPP_SUM; |
---|
782 | while ( cse &= thePic.mcache[pmax][MAIN_HI_IDX] ) { |
---|
783 | rval = __ilog2(cse) + 32; |
---|
784 | pmax = pt[rval]; |
---|
785 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
786 | printk("Max pri IRQ now %i\n",rval); |
---|
787 | #endif |
---|
788 | } |
---|
789 | /* if there were GPP ints, scan the GPP cause now */ |
---|
790 | if ( ocse & IMH_GPP_SUM ) { |
---|
791 | cse = in_le32(thePic.causes[GPP_IDX ]); |
---|
792 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
793 | printk("GPP; cse: 0x%08x, msk 0x%08x\n", cse, thePic.mcache[pmax][GPP_IDX ]); |
---|
794 | #endif |
---|
795 | cse &= thePic.mcache[pmax][GPP_IDX ]; |
---|
796 | ocse = cse; |
---|
797 | while ( cse ) { |
---|
798 | rval = __ilog2(cse) + 64; |
---|
799 | pmax = pt[rval]; |
---|
800 | cse &= thePic.mcache[pmax][GPP_IDX ]; |
---|
801 | #if (_IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
802 | printk("Max pri IRQ now %i\n",rval); |
---|
803 | #endif |
---|
804 | } |
---|
805 | /* this doesn't seem to be necessary -- however, the linux people do it... */ |
---|
806 | out_le32(thePic.causes[GPP_IDX], ~ocse); |
---|
807 | } |
---|
808 | /* this doesn't seem to be necessary -- however, the linux people do it... */ |
---|
809 | (void)in_le32(thePic.causes[GPP_IDX]); |
---|
810 | |
---|
811 | *ppri = pmax; |
---|
812 | return rval; |
---|
813 | } |
---|
814 | #endif |
---|
815 | |
---|
816 | |
---|
817 | /* Here's our dispatcher; the BSP framework uses the same one for EE and decrementer |
---|
818 | * exceptions... |
---|
819 | */ |
---|
820 | int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) |
---|
821 | { |
---|
822 | register int irq; |
---|
823 | int loop, last_irq; |
---|
824 | rtems_irq_prio pri; |
---|
825 | #if (IRQ_DEBUG) & IRQ_DEBUG_MAXLAT |
---|
826 | unsigned long diff; |
---|
827 | #endif |
---|
828 | |
---|
829 | #if (IRQ_DEBUG) & IRQ_DEBUG_MAXLAT |
---|
830 | diff = mftb(); |
---|
831 | #endif |
---|
832 | |
---|
833 | if (excNum == ASM_DEC_VECTOR) { |
---|
834 | decrementerPending = 1; |
---|
835 | } |
---|
836 | |
---|
837 | /* Tradeoff: EITHER we loop as long as interrupts are pending |
---|
838 | * incurring the overhead of one extra run of the 'find_pending_irq' routine. |
---|
839 | * OR we do rely on the handler just being invoked again if multiple |
---|
840 | * interrupts are pending. |
---|
841 | * |
---|
842 | * The first solution gives better worst-case behavior |
---|
843 | * the second slightly better average performance. |
---|
844 | * --> we go for the first solution. This also enables us to catch |
---|
845 | * runaway interrupts, i.e., bad drivers that don't clear interrupts |
---|
846 | * at the device. Can be very handy during driver development... |
---|
847 | */ |
---|
848 | for ( loop=0, last_irq=-1, pri = thePic.current_priority; |
---|
849 | (irq=find_highest_priority_pending_irq(&pri)) >=0; |
---|
850 | loop++, last_irq = irq ) { |
---|
851 | |
---|
852 | /* raise priority level and remember current one */ |
---|
853 | pri = change_executing_prio_level(pri); |
---|
854 | |
---|
855 | SYNC(); |
---|
856 | |
---|
857 | #if (IRQ_DEBUG) & IRQ_DEBUG_MAXLAT |
---|
858 | if ( 0 == loop ) { |
---|
859 | diff = mftb()-diff; |
---|
860 | if ( diff > discovery_pic_max_dispatching_latency ) |
---|
861 | discovery_pic_max_dispatching_latency = diff; |
---|
862 | } |
---|
863 | #endif |
---|
864 | |
---|
865 | #if (IRQ_DEBUG) & IRQ_DEBUG_DISPATCHER |
---|
866 | if ( BSP_DECREMENTER == irq ) { |
---|
867 | printk("IRQ: dispatching DECREMENTER\n"); |
---|
868 | } else { |
---|
869 | int idx = irqDiv32(irq); |
---|
870 | printk("IRQ: dispatching #%i; causes[%i]=0x%08x\n", irq, idx, ld_le32(thePic.causes[idx])); |
---|
871 | } |
---|
872 | #endif |
---|
873 | |
---|
874 | bsp_irq_dispatch_list( theConfig.irqHdlTbl, irq, theConfig.defaultEntry.hdl ); |
---|
875 | |
---|
876 | /* restore executing priority level */ |
---|
877 | (void)change_executing_prio_level(pri); |
---|
878 | |
---|
879 | if ( (loop > MAX_SPIN_LOOPS) && (last_irq == irq) ) { |
---|
880 | /* try to catch run-away interrupts without disabling a 'legal' one; |
---|
881 | * this should never happen with the decrementer (and |
---|
882 | * BSP_disable_irq_at_pic(BSP_DECREMENTER) would fail) |
---|
883 | */ |
---|
884 | printk("Runaway IRQ #%i; disabling\n", irq); |
---|
885 | BSP_disable_irq_at_pic(irq); |
---|
886 | loop = 0; |
---|
887 | } |
---|
888 | } |
---|
889 | |
---|
890 | if (!loop) { |
---|
891 | if ( decrementerPending && pri >= theConfig.irqPrioTbl[BSP_DECREMENTER] ) { |
---|
892 | /* we cannot mask the decrementer interrupt so it is possible that it |
---|
893 | * gets delivered even though it has a lower priority than what we're |
---|
894 | * currently executing at. |
---|
895 | * In this case, we ignore the zero loop count and return; |
---|
896 | * the interrupted instance of C_dispatch_irq_handler() will eventually |
---|
897 | * lower the executing priority and catch the 'decrementerPending' flag |
---|
898 | * we just set. |
---|
899 | */ |
---|
900 | } else { |
---|
901 | printk("Discovery: Spurious interrupt; causes were gpp: 0x%x, mhc: 0x%x, mlc: 0x%x\n", gpc, mhc, mlc); |
---|
902 | printk("Current priority level %i, decrementerPending %i\n", pri, decrementerPending); |
---|
903 | { |
---|
904 | rtems_irq_prio p=pri; |
---|
905 | printk("PIC register dump:\n"); |
---|
906 | discovery_dump_picregs(); |
---|
907 | printk("Current Priority: %i, found %i\n",pri,find_highest_priority_pending_irq(&p)); |
---|
908 | discovery_dump_picregs(); |
---|
909 | for (p=0; p<=BSP_IRQ_MAX_PRIO; p++) { |
---|
910 | printk("M[%i] :",p);pmsks(thePic.mcache[p]); |
---|
911 | } |
---|
912 | } |
---|
913 | } |
---|
914 | } |
---|
915 | else if (loop>discovery_pic_max_loops) |
---|
916 | discovery_pic_max_loops = loop; |
---|
917 | |
---|
918 | return 0; |
---|
919 | } |
---|
920 | |
---|
921 | |
---|
922 | #if (IRQ_DEBUG) & MVME6100_IRQ_DEBUG |
---|
923 | void |
---|
924 | discovery_pic_install_debug_irq(void) |
---|
925 | { |
---|
926 | switch ( BSP_getBoardType() ) { |
---|
927 | case MVME6100: gpp_out_bit = GPP_WIRED_OUT_BIT_6100; break; |
---|
928 | case MVME5500: gpp_out_bit = GPP_WIRED_OUT_BIT_5500; break; |
---|
929 | default: |
---|
930 | gpp_out_bit = 0; break; |
---|
931 | break; |
---|
932 | } |
---|
933 | if ( gpp_out_bit ) { |
---|
934 | unsigned mppoff; |
---|
935 | switch (gpp_out_bit / 8) { |
---|
936 | default: /* silence warning; this is never reached */ |
---|
937 | case 0: mppoff = GT_MPP_Control0; break; |
---|
938 | case 1: mppoff = GT_MPP_Control1; break; |
---|
939 | case 2: mppoff = GT_MPP_Control2; break; |
---|
940 | case 3: mppoff = GT_MPP_Control3; break; |
---|
941 | } |
---|
942 | |
---|
943 | /* switch GPP pin allocated to watchdog (value 4) to |
---|
944 | * GPP I/O (value 0 ??; have no doc, found out by experimenting) |
---|
945 | */ |
---|
946 | gt_bitmod(mppoff, 0, (0xf<<(4*(gpp_out_bit % 8)))); |
---|
947 | |
---|
948 | /* make it an output */ |
---|
949 | gt_bitmod(GT_GPP_IO_Control, (1<<gpp_out_bit), 0); |
---|
950 | |
---|
951 | /* don't invert levels */ |
---|
952 | gt_bitmod(GT_GPP_Level_Control, 0, (1<<GPP_WIRED_IN_BIT) | (1<<gpp_out_bit)); |
---|
953 | |
---|
954 | /* clear output */ |
---|
955 | gt_bitmod(GT_GPP_Value, 0, 1<<gpp_out_bit); |
---|
956 | |
---|
957 | printk("GPP levelctl now 0x%08x\n", gt_read(GT_GPP_Level_Control)); |
---|
958 | printk("GPP value now 0x%08x\n", gt_read(GT_GPP_Value)); |
---|
959 | printk("MPP ctl 0 now 0x%08x\n", gt_read(GT_MPP_Control0)); |
---|
960 | printk("MPP ctl 1 now 0x%08x\n", gt_read(GT_MPP_Control1)); |
---|
961 | printk("MPP ctl 2 now 0x%08x\n", gt_read(GT_MPP_Control2)); |
---|
962 | printk("MPP ctl 3 now 0x%08x\n", gt_read(GT_MPP_Control3)); |
---|
963 | |
---|
964 | } |
---|
965 | } |
---|
966 | |
---|
967 | /* Control the state of the external 'wire' that connects the |
---|
968 | * GPP_WIRED_OUT --> GPP_WIRED_IN pins |
---|
969 | */ |
---|
970 | void |
---|
971 | discovery_pic_set_debug_irq(int on) |
---|
972 | { |
---|
973 | unsigned long flags, clr; |
---|
974 | if ( !gpp_out_bit ) { |
---|
975 | printk("discovery_pic_set_debug_irq(): unknown wire output\n"); |
---|
976 | return; |
---|
977 | } |
---|
978 | if (on) { |
---|
979 | on = 1<<gpp_out_bit; |
---|
980 | clr = 0; |
---|
981 | } else { |
---|
982 | clr = 1<<gpp_out_bit; |
---|
983 | on = 0; |
---|
984 | } |
---|
985 | rtems_interrupt_disable(flags); |
---|
986 | gt_bitmod(GT_GPP_Value, on, clr); |
---|
987 | rtems_interrupt_enable(flags); |
---|
988 | } |
---|
989 | #endif |
---|
990 | |
---|
991 | #if 0 |
---|
992 | /* Here's some code for testing */ |
---|
993 | #endif |
---|