source: rtems/bsps/powerpc/beatnik/include/bsp/irq.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 5.3 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by rtems to write interrupt handlers.
5 *
6 *  CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 *
18 * Modified by T. Straumann for the beatnik BSP, 2005-2007
19 * Some information may be based on mvme5500/irq/irq.h by K. Feng.
20 */
21
22#ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H
23#define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H
24
25#define BSP_SHARED_HANDLER_SUPPORT      1
26#include <rtems/irq.h>
27#include <bsp/vectors.h>
28
29/* This BSP also passes a pointer to the interrupt frame to the handler.
30 * The PPC ABI guarantees that this will not mess up handlers written
31 * without knowledge of this feature.
32 */
33
34typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*);
35
36
37/* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */
38#define BSP_IRQ_MAX_PRIO                4
39#define BSP_IRQ_MIN_PRIO                1
40
41/* Note that priorites are only honoured for 'PCI' interrupt numbers.
42 * The discovery pic has no support for hardware priorites; hence they
43 * are handled in software
44 */
45#define BSP_IRQ_DEFAULT_PRIORITY 2
46
47
48#define BSP_PCI_IRQ_LOWEST_OFFSET       0       /* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */
49#define BSP_IRQ_DEV                     1       /* device interface interrupt */
50#define BSP_IRQ_DMA                     2       /* DMA addres error interrupt (260) */
51#define BSP_IRQ_CPU                     3       /* CPU interface interrupt */
52#define BSP_IRQ_IDMA0_1                 4       /* IDMA ch. 0..1 complete interrupt (260) */
53#define BSP_IRQ_IDMA2_3                 5       /* IDMA ch. 2..3 complete interrupt (260) */
54#define BSP_IRQ_IDMA4_5                 6       /* IDMA ch. 4..5 complete interrupt (260) */
55#define BSP_IRQ_IDMA6_7                 7       /* IDMA ch. 6..7 complete interrupt (260) */
56#define BSP_IRQ_TIME0_1                 8       /* Timer 0..1 interrupt; Timer 0 on 64360 */
57#define BSP_IRQ_TIME2_3                 9       /* Timer 2..3 interrupt; Timer 1 on 64360 */
58#define BSP_IRQ_TIME4_5                 10      /* Timer 4..5 interrupt; Timer 2 on 64360 */
59#define BSP_IRQ_TIME6_7                 11      /* Timer 6..7 interrupt; Timer 3 on 64360 */
60#define BSP_IRQ_PCI0_0                  12      /* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */
61#define BSP_IRQ_PCI0_1                  13      /* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360)          */
62#define BSP_IRQ_PCI0_2                  14      /* PCI 0 interrupt 2 summary */
63#define BSP_IRQ_PCI0_3                  15      /* PCI 0 interrupt 3 summary */
64#define BSP_IRQ_PCI1_0                  16      /* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */
65#define BSP_IRQ_ECC                         17  /* ECC error interrupt */
66#define BSP_IRQ_PCI1_1                  18      /* PCI 1 interrupt 1 summary */
67#define BSP_IRQ_PCI1_2                  19      /* PCI 1 interrupt 2 summary */
68#define BSP_IRQ_PCI1_3                  20      /* PCI 1 interrupt 3 summary */
69#define BSP_IRQ_PCI0OUT_LO              21      /* PCI 0 outbound interrupt summary */
70#define BSP_IRQ_PCI0OUT_HI              22      /* PCI 0 outbound interrupt summary */
71#define BSP_IRQ_PCI1OUT_LO              23      /* PCI 1 outbound interrupt summary */
72#define BSP_IRQ_PCI1OUT_HI              24      /* PCI 1 outbound interrupt summary */
73#define BSP_IRQ_PCI0IN_LO               26      /* PCI 0 inbound interrupt summary */
74#define BSP_IRQ_PCI0IN_HI               27      /* PCI 0 inbound interrupt summary */
75#define BSP_IRQ_PCI1IN_LO               28      /* PCI 1 inbound interrupt summary */
76#define BSP_IRQ_PCI1IN_HI               29      /* PCI 1 inbound interrupt summary */
77#define BSP_IRQ_ETH0                    (32+0)  /* Ethernet controller 0 interrupt */
78#define BSP_IRQ_ETH1                    (32+1)  /* Ethernet controller 1 interrupt */
79#define BSP_IRQ_ETH2                    (32+2)  /* Ethernet controller 2 interrupt */
80#define BSP_IRQ_SDMA                    (32+4)  /* SDMA interrupt */
81#define BSP_IRQ_I2C                     (32+5)  /* I2C interrupt */
82#define BSP_IRQ_BRG                     (32+7)  /* Baud Rate Generator interrupt */
83#define BSP_IRQ_MPSC0                   (32+8)  /* MPSC 0 interrupt */
84#define BSP_IRQ_MPSC1                   (32+10) /* MPSC 1 interrupt */
85#define BSP_IRQ_COMM                    (32+11) /* Comm unit interrupt */
86#define BSP_IRQ_GPP7_0                  (32+24) /* GPP[7..0] interrupt summary */
87#define BSP_IRQ_GPP15_8                 (32+25) /* GPP[15..8] interrupt summary */
88#define BSP_IRQ_GPP23_16                (32+26) /* GPP[23..16] interrupt summary */
89#define BSP_IRQ_GPP31_24                (32+27) /* GPP[31..24] interrupt summary */
90#define BSP_IRQ_GPP_0                   64
91
92#define BSP_PCI_IRQ_NUMBER              (64+32)
93#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
94
95#define BSP_PROCESSOR_IRQ_NUMBER        1
96#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1)
97#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
98
99/* summary */
100
101#define BSP_IRQ_NUMBER                  (BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER)
102#define BSP_LOWEST_OFFSET               0
103#define BSP_MAX_OFFSET                  (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1)
104#define BSP_DECREMENTER                 BSP_PROCESSOR_IRQ_LOWEST_OFFSET
105
106#define BSP_UART_COM1_IRQ               BSP_IRQ_GPP_0
107#define BSP_UART_COM2_IRQ               BSP_IRQ_GPP_0
108
109#ifndef ASM
110
111#ifdef __cplusplus
112extern "C" {
113#endif
114
115
116#include <bsp/irq_supp.h>
117
118int  BSP_irq_is_enabled_at_pic(rtems_irq_number irq);
119
120/* set priority of an interrupt; must not be called from ISR level */
121int  BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri);
122
123/* Not for public use */
124void BSP_rtems_irq_mng_init(unsigned cpuId);
125
126#ifdef __cplusplus
127}
128#endif
129
130
131#endif
132
133#endif
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