[b7a6d23a] | 1 | /* irq.h |
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| 2 | * |
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| 3 | * This include file describe the data structure and the functions implemented |
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| 4 | * by rtems to write interrupt handlers. |
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| 5 | * |
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| 6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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| 7 | * |
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| 8 | * This code is heavilly inspired by the public specification of STREAM V2 |
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| 9 | * that can be found at : |
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| 10 | * |
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| 11 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 12 | * the STREAM API Specification Document link. |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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[0c875c6a] | 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[b7a6d23a] | 17 | * |
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| 18 | * Modified by T. Straumann for the beatnik BSP, 2005-2007 |
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| 19 | * Some information may be based on mvme5500/irq/irq.h by K. Feng. |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H |
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| 23 | #define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H |
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| 24 | |
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| 25 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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| 26 | #include <rtems/irq.h> |
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| 27 | #include <bsp/vectors.h> |
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| 28 | |
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| 29 | /* This BSP also passes a pointer to the interrupt frame to the handler. |
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| 30 | * The PPC ABI guarantees that this will not mess up handlers written |
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| 31 | * without knowledge of this feature. |
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| 32 | */ |
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| 33 | |
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| 34 | typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*); |
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| 35 | |
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| 36 | |
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| 37 | /* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */ |
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| 38 | #define BSP_IRQ_MAX_PRIO 4 |
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| 39 | #define BSP_IRQ_MIN_PRIO 1 |
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| 40 | |
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| 41 | /* Note that priorites are only honoured for 'PCI' interrupt numbers. |
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| 42 | * The discovery pic has no support for hardware priorites; hence they |
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| 43 | * are handled in software |
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| 44 | */ |
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| 45 | #define BSP_IRQ_DEFAULT_PRIORITY 2 |
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| 46 | |
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| 47 | |
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| 48 | #define BSP_PCI_IRQ_LOWEST_OFFSET 0 /* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */ |
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| 49 | #define BSP_IRQ_DEV 1 /* device interface interrupt */ |
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| 50 | #define BSP_IRQ_DMA 2 /* DMA addres error interrupt (260) */ |
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| 51 | #define BSP_IRQ_CPU 3 /* CPU interface interrupt */ |
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| 52 | #define BSP_IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt (260) */ |
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| 53 | #define BSP_IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt (260) */ |
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| 54 | #define BSP_IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt (260) */ |
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| 55 | #define BSP_IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt (260) */ |
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| 56 | #define BSP_IRQ_TIME0_1 8 /* Timer 0..1 interrupt; Timer 0 on 64360 */ |
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| 57 | #define BSP_IRQ_TIME2_3 9 /* Timer 2..3 interrupt; Timer 1 on 64360 */ |
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| 58 | #define BSP_IRQ_TIME4_5 10 /* Timer 4..5 interrupt; Timer 2 on 64360 */ |
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| 59 | #define BSP_IRQ_TIME6_7 11 /* Timer 6..7 interrupt; Timer 3 on 64360 */ |
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| 60 | #define BSP_IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */ |
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| 61 | #define BSP_IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360) */ |
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| 62 | #define BSP_IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ |
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| 63 | #define BSP_IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ |
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| 64 | #define BSP_IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */ |
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| 65 | #define BSP_IRQ_ECC 17 /* ECC error interrupt */ |
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| 66 | #define BSP_IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ |
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| 67 | #define BSP_IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ |
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| 68 | #define BSP_IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ |
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| 69 | #define BSP_IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ |
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| 70 | #define BSP_IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ |
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| 71 | #define BSP_IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ |
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| 72 | #define BSP_IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ |
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| 73 | #define BSP_IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ |
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| 74 | #define BSP_IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ |
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| 75 | #define BSP_IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ |
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| 76 | #define BSP_IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ |
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| 77 | #define BSP_IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ |
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| 78 | #define BSP_IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ |
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| 79 | #define BSP_IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ |
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| 80 | #define BSP_IRQ_SDMA (32+4) /* SDMA interrupt */ |
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| 81 | #define BSP_IRQ_I2C (32+5) /* I2C interrupt */ |
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| 82 | #define BSP_IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ |
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| 83 | #define BSP_IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ |
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| 84 | #define BSP_IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ |
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| 85 | #define BSP_IRQ_COMM (32+11) /* Comm unit interrupt */ |
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| 86 | #define BSP_IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt summary */ |
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| 87 | #define BSP_IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt summary */ |
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| 88 | #define BSP_IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt summary */ |
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| 89 | #define BSP_IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt summary */ |
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| 90 | #define BSP_IRQ_GPP_0 64 |
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| 91 | |
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| 92 | #define BSP_PCI_IRQ_NUMBER (64+32) |
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| 93 | #define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) |
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| 94 | |
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| 95 | #define BSP_PROCESSOR_IRQ_NUMBER 1 |
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| 96 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1) |
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| 97 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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| 98 | |
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| 99 | /* summary */ |
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| 100 | |
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| 101 | #define BSP_IRQ_NUMBER (BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) |
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| 102 | #define BSP_LOWEST_OFFSET 0 |
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| 103 | #define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) |
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| 104 | #define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET |
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| 105 | |
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| 106 | #define BSP_UART_COM1_IRQ BSP_IRQ_GPP_0 |
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| 107 | #define BSP_UART_COM2_IRQ BSP_IRQ_GPP_0 |
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| 108 | |
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| 109 | #ifndef ASM |
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| 110 | |
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| 111 | #ifdef __cplusplus |
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| 112 | extern "C" { |
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| 113 | #endif |
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| 114 | |
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| 115 | |
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| 116 | #include <bsp/irq_supp.h> |
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| 117 | |
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| 118 | int BSP_irq_is_enabled_at_pic(rtems_irq_number irq); |
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| 119 | |
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| 120 | /* set priority of an interrupt; must not be called from ISR level */ |
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| 121 | int BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri); |
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| 122 | |
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| 123 | /* Not for public use */ |
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| 124 | void BSP_rtems_irq_mng_init(unsigned cpuId); |
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| 125 | |
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| 126 | #ifdef __cplusplus |
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| 127 | } |
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| 128 | #endif |
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| 129 | |
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| 130 | |
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| 131 | #endif |
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| 132 | |
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| 133 | #endif |
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