| 1 | /* $NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $ */ |
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| 2 | |
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| 3 | /* |
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| 4 | * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. |
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| 5 | * All rights reserved. |
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| 6 | * |
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| 7 | * Redistribution and use in source and binary forms, with or without |
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| 8 | * modification, are permitted provided that the following conditions |
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| 9 | * are met: |
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| 10 | * 1. Redistributions of source code must retain the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer. |
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| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in the |
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| 14 | * documentation and/or other materials provided with the distribution. |
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| 15 | * 3. All advertising materials mentioning features or use of this software |
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| 16 | * must display the following acknowledgement: |
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| 17 | * This product includes software developed for the NetBSD Project by |
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| 18 | * Allegro Networks, Inc., and Wasabi Systems, Inc. |
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| 19 | * 4. The name of Allegro Networks, Inc. may not be used to endorse |
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| 20 | * or promote products derived from this software without specific prior |
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| 21 | * written permission. |
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| 22 | * 5. The name of Wasabi Systems, Inc. may not be used to endorse |
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| 23 | * or promote products derived from this software without specific prior |
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| 24 | * written permission. |
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| 25 | * |
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| 26 | * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND |
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| 27 | * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, |
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| 28 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY |
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| 29 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 30 | * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. |
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| 31 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 37 | * POSSIBILITY OF SUCH DAMAGE. |
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| 38 | */ |
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| 39 | |
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| 40 | /* |
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| 41 | * gt64260intr.h: defines for GT-64260 system controller interrupts |
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| 42 | * |
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| 43 | * creation Sun Jan 7 18:05:59 PST 2001 cliff |
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| 44 | * |
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| 45 | * NOTE: |
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| 46 | * Galileo GT-64260 manual bit defines assume Little Endian |
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| 47 | * ordering of bits within bytes, i.e. |
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| 48 | * bit #0 --> 0x01 |
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| 49 | * vs. Motorola Big Endian bit numbering where |
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| 50 | * bit #0 --> 0x80 |
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| 51 | * Consequently we define bits in Little Endian format and plan |
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| 52 | * to swizzle bytes during programmed I/O by using lwbrx/swbrx |
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| 53 | * to load/store GT-64260 registers. |
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| 54 | */ |
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| 55 | |
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| 56 | |
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| 57 | #ifndef _DISCOVERY_GT64260INTR_H |
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| 58 | #define _DISCOVERY_GT64260INTR_H |
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| 59 | |
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| 60 | #define BIT(n) (1<<(n)) |
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| 61 | |
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| 62 | |
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| 63 | /* |
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| 64 | * GT-64260 Interrupt Controller Register Map |
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| 65 | */ |
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| 66 | #define ICR_260_MIC_LO 0xc18 /* main interrupt cause low */ |
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| 67 | #define ICR_260_MIC_HI 0xc68 /* main interrupt cause high */ |
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| 68 | #define ICR_260_CIM_LO 0xc1c /* CPU interrupt mask low */ |
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| 69 | #define ICR_260_CIM_HI 0xc6c /* CPU interrupt mask high */ |
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| 70 | #define ICR_260_CSC 0xc70 /* CPU select cause */ |
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| 71 | #define ICR_260_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ |
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| 72 | #define ICR_260_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ |
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| 73 | #define ICR_260_P0SC 0xc74 /* PCI_0 select cause */ |
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| 74 | #define ICR_260_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ |
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| 75 | #define ICR_260_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ |
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| 76 | #define ICR_260_P1SC 0xcf4 /* PCI_1 select cause */ |
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| 77 | #define ICR_260_CI0M 0xe60 /* CPU int[0] mask */ |
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| 78 | #define ICR_260_CI1M 0xe64 /* CPU int[1] mask */ |
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| 79 | #define ICR_260_CI2M 0xe68 /* CPU int[2] mask */ |
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| 80 | #define ICR_260_CI3M 0xe6c /* CPU int[3] mask */ |
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| 81 | |
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| 82 | /* |
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| 83 | * MV64360 Interrupt Controller Register Map |
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| 84 | */ |
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| 85 | #define ICR_360_MIC_LO 0x004 /* main interrupt cause low */ |
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| 86 | #define ICR_360_MIC_HI 0x00c /* main interrupt cause high */ |
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| 87 | #define ICR_360_C0IM_LO 0x014 /* CPU 0 interrupt mask low */ |
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| 88 | #define ICR_360_C0IM_HI 0x01c /* CPU 0 interrupt mask high */ |
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| 89 | #define ICR_360_C0SC 0x024 /* CPU 0 select cause */ |
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| 90 | #define ICR_360_C1IM_LO 0x034 /* CPU 1 interrupt mask low */ |
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| 91 | #define ICR_360_C1IM_HI 0x03c /* CPU 1 interrupt mask high */ |
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| 92 | #define ICR_360_C1SC 0x044 /* CPU 1 select cause */ |
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| 93 | #define ICR_360_I0M_LO 0x014 /* Int 0 mask low */ |
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| 94 | #define ICR_360_I0M_HI 0x01c /* Int 0 mask high */ |
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| 95 | #define ICR_360_I0SC 0x024 /* Int 0 select cause */ |
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| 96 | #define ICR_360_I1M_LO 0x034 /* Int 1 mask low */ |
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| 97 | #define ICR_360_I1M_HI 0x03c /* Int 1 mask high */ |
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| 98 | #define ICR_360_C1SC 0x044 /* Int 1 select cause */ |
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| 99 | |
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| 100 | |
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| 101 | /* |
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| 102 | * IRQs: |
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| 103 | * we define IRQs based on bit number in the |
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| 104 | * ICU_LEN dimensioned hardware portion of the imask_t bit vector |
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| 105 | * which consists of 64 bits of Main Cause and Mask register pairs |
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| 106 | * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI) |
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| 107 | * as well as 32 bits in GPP registers (see intr.h): |
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| 108 | * |
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| 109 | * IRQs: |
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| 110 | * 31.............................0 63.............................32 |
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| 111 | * | | | |
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| 112 | * imask_t index: | | | |
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| 113 | * | | | | |
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| 114 | * ^--------- IM_PIC_LO ----------^ ^------ IM_PIC_HI ------------^ |
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| 115 | * | | | |
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| 116 | * Bitmasks: | | | |
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| 117 | * | | | | |
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| 118 | * ^--------- IML_* --------------^ ^------ IMH_* ----------------^ |
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| 119 | * | | | |
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| 120 | * Registers: | | | |
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| 121 | * | | | | |
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| 122 | * ^--------- ICR_MIC_LO ---------^ ^------ ICR_MIC_HI -----------^ |
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| 123 | * ^--------- ICR_CIM_LO ---------^ ^------ ICR_CIM_HI -----------^ |
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| 124 | * |
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| 125 | * IRQs: |
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| 126 | * 95............................64 127............................96 |
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| 127 | * | | | |
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| 128 | * imask_t index: | | | |
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| 129 | * | | | | |
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| 130 | * ^-------- IMASK_GPP ----------^ ^----- IMASK_SOFTINT --------^ |
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| 131 | * | | | |
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| 132 | * Bitmasks: | | | |
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| 133 | * | | | | |
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| 134 | * ^--------- GPP_* --------------^ ^------ SIBIT(irq) -----------^ |
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| 135 | * | | | |
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| 136 | * Registers: | | | |
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| 137 | * | | | | |
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| 138 | * ^--- GT_GPP_Interrupt_Cause ---^ ^------- (none) -----------^ |
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| 139 | * ^--- GT_GPP_Interrupt_Mask ---^ |
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| 140 | * |
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| 141 | * |
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| 142 | * Note that GPP interrupts are summarized in the Main Cause Register. |
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| 143 | * |
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| 144 | * Some IRQs are "resvered" undefined due to gaps in HW register utilization. |
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| 145 | */ |
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| 146 | #define IRQ_DEV 1 /* device interface interrupt */ |
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| 147 | #define IRQ_DMA 2 /* DMA addres error interrupt */ |
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| 148 | #define IRQ_CPU 3 /* CPU interface interrupt */ |
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| 149 | #define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ |
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| 150 | #define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ |
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| 151 | #define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ |
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| 152 | #define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ |
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| 153 | #define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ |
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| 154 | #define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ |
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| 155 | #define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ |
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| 156 | #define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ |
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| 157 | #define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ |
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| 158 | #define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ |
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| 159 | #define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ |
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| 160 | #define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ |
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| 161 | #define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ |
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| 162 | #define IRQ_ECC 17 /* ECC error interrupt */ |
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| 163 | #define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ |
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| 164 | #define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ |
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| 165 | #define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ |
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| 166 | #define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ |
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| 167 | #define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ |
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| 168 | #define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ |
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| 169 | #define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ |
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| 170 | #define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ |
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| 171 | #define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ |
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| 172 | #define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ |
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| 173 | #define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ |
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| 174 | #define IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ |
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| 175 | #define IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ |
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| 176 | #define IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ |
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| 177 | #define IRQ_SDMA (32+4) /* SDMA interrupt */ |
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| 178 | #define IRQ_I2C (32+5) /* I2C interrupt */ |
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| 179 | #define IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ |
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| 180 | #define IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ |
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| 181 | #define IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ |
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| 182 | #define IRQ_COMM (32+11) /* Comm unit interrupt */ |
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| 183 | #define IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt */ |
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| 184 | #define IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt */ |
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| 185 | #define IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt */ |
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| 186 | #define IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt */ |
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| 187 | |
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| 188 | /* |
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| 189 | * low word interrupt mask register bits |
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| 190 | */ |
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| 191 | #define IML_SUM BIT(0) |
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| 192 | #define IML_DEV BIT(IRQ_DEV) |
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| 193 | #define IML_DMA BIT(IRQ_DMA) |
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| 194 | #define IML_CPU BIT(IRQ_CPU) |
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| 195 | #define IML_IDMA0_1 BIT(IRQ_IDMA0_1) |
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| 196 | #define IML_IDMA2_3 BIT(IRQ_IDMA2_3) |
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| 197 | #define IML_IDMA4_5 BIT(IRQ_IDMA4_5) |
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| 198 | #define IML_IDMA6_7 BIT(IRQ_IDMA6_7) |
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| 199 | #define IML_TIME0_1 BIT(IRQ_TIME0_1) |
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| 200 | #define IML_TIME2_3 BIT(IRQ_TIME2_3) |
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| 201 | #define IML_TIME4_5 BIT(IRQ_TIME4_5) |
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| 202 | #define IML_TIME6_7 BIT(IRQ_TIME6_7) |
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| 203 | #define IML_PCI0_0 BIT(IRQ_PCI0_0) |
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| 204 | #define IML_PCI0_1 BIT(IRQ_PCI0_1) |
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| 205 | #define IML_PCI0_2 BIT(IRQ_PCI0_2) |
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| 206 | #define IML_PCI0_3 BIT(IRQ_PCI0_3) |
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| 207 | #define IML_PCI1_0 BIT(IRQ_PCI1_0) |
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| 208 | #define IML_ECC BIT(IRQ_ECC) |
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| 209 | #define IML_PCI1_1 BIT(IRQ_PCI1_1) |
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| 210 | #define IML_PCI1_2 BIT(IRQ_PCI1_2) |
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| 211 | #define IML_PCI1_3 BIT(IRQ_PCI1_3) |
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| 212 | #define IML_PCI0OUT_LO BIT(IRQ_PCI0OUT_LO) |
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| 213 | #define IML_PCI0OUT_HI BIT(IRQ_PCI0OUT_HI) |
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| 214 | #define IML_PCI1OUT_LO BIT(IRQ_PCI1OUT_LO) |
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| 215 | #define IML_PCI1OUT_HI BIT(IRQ_PCI1OUT_HI) |
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| 216 | #define IML_PCI0IN_LO BIT(IRQ_PCI0IN_LO) |
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| 217 | #define IML_PCI0IN_HI BIT(IRQ_PCI0IN_HI) |
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| 218 | #define IML_PCI1IN_LO BIT(IRQ_PCI1IN_LO) |
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| 219 | #define IML_PCI1IN_HI BIT(IRQ_PCI1IN_HI) |
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| 220 | #define IML_RES (BIT(25)|BIT(30)|BIT(31)) |
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| 221 | |
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| 222 | /* |
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| 223 | * high word interrupt mask register bits |
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| 224 | */ |
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| 225 | #define IMH_ETH0 BIT(IRQ_ETH0-32) |
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| 226 | #define IMH_ETH1 BIT(IRQ_ETH1-32) |
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| 227 | #define IMH_ETH2 BIT(IRQ_ETH2-32) |
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| 228 | #define IMH_SDMA BIT(IRQ_SDMA-32) |
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| 229 | #define IMH_I2C BIT(IRQ_I2C-32) |
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| 230 | #define IMH_BRG BIT(IRQ_BRG-32) |
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| 231 | #define IMH_MPSC0 BIT(IRQ_MPSC0-32) |
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| 232 | #define IMH_MPSC1 BIT(IRQ_MPSC1-32) |
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| 233 | #define IMH_COMM BIT(IRQ_COMM-32) |
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| 234 | #define IMH_GPP7_0 BIT(IRQ_GPP7_0-32) |
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| 235 | #define IMH_GPP15_8 BIT(IRQ_GPP15_8-32) |
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| 236 | #define IMH_GPP23_16 BIT(IRQ_GPP23_16-32) |
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| 237 | #define IMH_GPP31_24 BIT(IRQ_GPP31_24-32) |
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| 238 | #define IMH_GPP_SUM (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24) |
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| 239 | #define IMH_RES (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \ |
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| 240 | |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \ |
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| 241 | |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \ |
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| 242 | |BIT(31)) |
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| 243 | |
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| 244 | /* |
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| 245 | * ICR_CSC "Select Cause" register bits |
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| 246 | */ |
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| 247 | #define CSC_SEL BIT(30) /* HI/LO select */ |
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| 248 | #define CSC_STAT BIT(31) /* ? "irq active" : "irq none" */ |
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| 249 | #define CSC_CAUSE ~(CSC_SEL|CSC_STAT) |
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| 250 | |
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| 251 | |
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| 252 | /* |
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| 253 | * CPU Int[n] Mask bit(s) |
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| 254 | */ |
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| 255 | #define CPUINT_SEL 0x80000000 /* HI/LO select */ |
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| 256 | |
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| 257 | #endif /* _DISCOVERY_GT64260INTR_H */ |
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