[c080c343] | 1 | /* |
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[3b4ddaf] | 2 | * COPYRIGHT (c) 2014, 2016 Ã
AC Microtec AB <www.aacmicrotec.com> |
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[e639c026] | 3 | * Contributor(s): |
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| 4 | * Karol Gugala <kgugala@antmicro.com> |
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[3b4ddaf] | 5 | * Martin Werner <martin.werner@aacmicrotec.com> |
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[e639c026] | 6 | * |
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[c080c343] | 7 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1989-2006 |
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| 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.org/license/LICENSE. |
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| 15 | */ |
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| 16 | |
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| 17 | #include <rtems/score/cpu.h> |
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| 18 | #include <rtems/score/interr.h> |
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| 19 | #include <rtems/score/or1k-utility.h> |
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[48fed9a] | 20 | #include <rtems/score/percpu.h> |
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[4cf93658] | 21 | |
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| 22 | #define CPU_DATA_CACHE_ALIGNMENT 32 |
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| 23 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 |
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| 24 | |
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| 25 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1 |
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| 26 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1 |
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| 27 | |
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| 28 | static inline size_t |
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| 29 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
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| 30 | { |
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| 31 | return (level == 0 || level == 1)? 8192 : 0; |
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| 32 | } |
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| 33 | |
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| 34 | static inline size_t |
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| 35 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
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| 36 | { |
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| 37 | return (level == 0 || level == 1)? 8192 : 0; |
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| 38 | } |
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[c080c343] | 39 | |
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| 40 | static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) |
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| 41 | { |
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| 42 | ISR_Level level; |
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| 43 | |
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[24713163] | 44 | _ISR_Local_disable (level); |
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[c080c343] | 45 | |
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[37885d5d] | 46 | _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr); |
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[c080c343] | 47 | |
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[24713163] | 48 | _ISR_Local_enable(level); |
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[c080c343] | 49 | } |
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| 50 | |
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| 51 | static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) |
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| 52 | { |
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[4dcaa48] | 53 | ISR_Level level; |
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| 54 | |
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[24713163] | 55 | _ISR_Local_disable (level); |
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[c080c343] | 56 | |
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[37885d5d] | 57 | _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr); |
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[c080c343] | 58 | |
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[24713163] | 59 | _ISR_Local_enable(level); |
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[c080c343] | 60 | } |
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| 61 | |
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| 62 | static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) |
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| 63 | { |
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[4dcaa48] | 64 | ISR_Level level; |
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| 65 | |
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[24713163] | 66 | _ISR_Local_disable (level); |
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[c080c343] | 67 | |
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[37885d5d] | 68 | _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr); |
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[c080c343] | 69 | |
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[24713163] | 70 | _ISR_Local_enable(level); |
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[c080c343] | 71 | } |
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| 72 | |
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| 73 | static inline void _CPU_OR1K_Cache_instruction_block_prefetch |
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| 74 | (const void *d_addr) |
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| 75 | { |
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[4dcaa48] | 76 | ISR_Level level; |
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| 77 | |
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[24713163] | 78 | _ISR_Local_disable (level); |
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[c080c343] | 79 | |
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[37885d5d] | 80 | _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr); |
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[c080c343] | 81 | |
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[24713163] | 82 | _ISR_Local_enable(level); |
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[c080c343] | 83 | } |
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| 84 | |
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| 85 | static inline void _CPU_OR1K_Cache_instruction_block_lock |
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| 86 | (const void *d_addr) |
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| 87 | { |
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[4dcaa48] | 88 | ISR_Level level; |
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| 89 | |
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[24713163] | 90 | _ISR_Local_disable (level); |
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[c080c343] | 91 | |
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[37885d5d] | 92 | _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr); |
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[c080c343] | 93 | |
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[24713163] | 94 | _ISR_Local_enable(level); |
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[c080c343] | 95 | } |
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| 96 | |
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| 97 | /* Implement RTEMS cache manager functions */ |
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| 98 | |
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[4cf93658] | 99 | static void _CPU_cache_flush_1_data_line(const void *d_addr) |
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[c080c343] | 100 | { |
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[4dcaa48] | 101 | ISR_Level level; |
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| 102 | |
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[24713163] | 103 | _ISR_Local_disable (level); |
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[c080c343] | 104 | |
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[3b4ddaf] | 105 | _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); |
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[c080c343] | 106 | |
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[4dcaa48] | 107 | //__asm__ volatile("l.csync"); |
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[c080c343] | 108 | |
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[24713163] | 109 | _ISR_Local_enable(level); |
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[c080c343] | 110 | } |
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| 111 | |
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[4cf93658] | 112 | static void _CPU_cache_invalidate_1_data_line(const void *d_addr) |
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[c080c343] | 113 | { |
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[4dcaa48] | 114 | ISR_Level level; |
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| 115 | |
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[24713163] | 116 | _ISR_Local_disable (level); |
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[c080c343] | 117 | |
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[3b4ddaf] | 118 | _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); |
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[c080c343] | 119 | |
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[24713163] | 120 | _ISR_Local_enable(level); |
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[c080c343] | 121 | } |
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| 122 | |
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[4cf93658] | 123 | static void _CPU_cache_freeze_data(void) |
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[c080c343] | 124 | { |
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| 125 | /* Do nothing */ |
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| 126 | } |
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| 127 | |
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[4cf93658] | 128 | static void _CPU_cache_unfreeze_data(void) |
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[c080c343] | 129 | { |
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| 130 | /* Do nothing */ |
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| 131 | } |
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| 132 | |
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[4cf93658] | 133 | static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) |
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[c080c343] | 134 | { |
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[4dcaa48] | 135 | ISR_Level level; |
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| 136 | |
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[24713163] | 137 | _ISR_Local_disable (level); |
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[c080c343] | 138 | |
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[3b4ddaf] | 139 | _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr); |
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[c080c343] | 140 | |
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[24713163] | 141 | _ISR_Local_enable(level); |
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[c080c343] | 142 | } |
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| 143 | |
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[4cf93658] | 144 | static void _CPU_cache_freeze_instruction(void) |
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[c080c343] | 145 | { |
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| 146 | /* Do nothing */ |
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| 147 | } |
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| 148 | |
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[4cf93658] | 149 | static void _CPU_cache_unfreeze_instruction(void) |
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[c080c343] | 150 | { |
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| 151 | /* Do nothing */ |
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| 152 | } |
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| 153 | |
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[4cf93658] | 154 | static void _CPU_cache_flush_entire_data(void) |
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[c080c343] | 155 | { |
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[3b4ddaf] | 156 | size_t addr; |
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| 157 | ISR_Level level; |
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| 158 | |
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| 159 | _ISR_Local_disable (level); |
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[e639c026] | 160 | |
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| 161 | /* We have only 0 level cache so we do not need to invalidate others */ |
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| 162 | for ( |
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| 163 | addr = _CPU_cache_get_data_cache_size(0); |
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| 164 | addr > 0; |
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| 165 | addr -= CPU_DATA_CACHE_ALIGNMENT |
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| 166 | ) { |
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[3b4ddaf] | 167 | _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) addr); |
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[e639c026] | 168 | } |
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[3b4ddaf] | 169 | |
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| 170 | _ISR_Local_enable (level); |
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[c080c343] | 171 | } |
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| 172 | |
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[4cf93658] | 173 | static void _CPU_cache_invalidate_entire_data(void) |
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[c080c343] | 174 | { |
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[3b4ddaf] | 175 | size_t addr; |
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| 176 | ISR_Level level; |
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| 177 | |
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| 178 | _ISR_Local_disable (level); |
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[e639c026] | 179 | |
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| 180 | /* We have only 0 level cache so we do not need to invalidate others */ |
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| 181 | for ( |
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| 182 | addr = _CPU_cache_get_data_cache_size(0); |
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| 183 | addr > 0; |
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| 184 | addr -= CPU_DATA_CACHE_ALIGNMENT |
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| 185 | ) { |
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[3b4ddaf] | 186 | _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) addr); |
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[e639c026] | 187 | } |
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[3b4ddaf] | 188 | |
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| 189 | _ISR_Local_enable (level); |
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[c080c343] | 190 | } |
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| 191 | |
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[4cf93658] | 192 | static void _CPU_cache_invalidate_entire_instruction(void) |
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[c080c343] | 193 | { |
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[3b4ddaf] | 194 | size_t addr; |
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| 195 | ISR_Level level; |
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| 196 | |
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| 197 | _ISR_Local_disable (level); |
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[e639c026] | 198 | |
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| 199 | /* We have only 0 level cache so we do not need to invalidate others */ |
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| 200 | for ( |
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| 201 | addr = _CPU_cache_get_instruction_cache_size(0); |
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| 202 | addr > 0; |
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| 203 | addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT |
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| 204 | ) { |
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[3b4ddaf] | 205 | _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) addr); |
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[e639c026] | 206 | } |
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| 207 | |
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| 208 | /* Flush instructions out of instruction buffer */ |
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| 209 | __asm__ volatile("l.nop"); |
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| 210 | __asm__ volatile("l.nop"); |
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| 211 | __asm__ volatile("l.nop"); |
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| 212 | __asm__ volatile("l.nop"); |
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| 213 | __asm__ volatile("l.nop"); |
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[3b4ddaf] | 214 | |
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| 215 | _ISR_Local_enable (level); |
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| 216 | } |
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| 217 | |
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| 218 | /* |
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| 219 | * The range functions are copied almost verbatim from the generic |
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| 220 | * implementations in c/src/lib/libcpu/shared/src/cache_manager.c. The main |
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| 221 | * modification here is avoiding reapeated off/on toggling of the ISR for each |
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| 222 | * cache line operation. |
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| 223 | */ |
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| 224 | |
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[4cf93658] | 225 | static void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes) |
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[3b4ddaf] | 226 | { |
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| 227 | const void * final_address; |
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| 228 | ISR_Level level; |
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| 229 | |
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| 230 | /* |
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| 231 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 232 | * the last address_t which needs to be pushed. Increment d_addr and push |
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| 233 | * the resulting line until final_address is passed. |
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| 234 | */ |
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| 235 | |
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| 236 | if( n_bytes == 0 ) |
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| 237 | /* Do nothing if number of bytes to flush is zero */ |
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| 238 | return; |
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| 239 | |
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| 240 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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| 241 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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| 242 | |
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[9bf9068] | 243 | if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { |
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| 244 | /* |
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| 245 | * Avoid iterating over the whole cache multiple times if the range is |
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| 246 | * larger than the cache size. |
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| 247 | */ |
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| 248 | _CPU_cache_flush_entire_data(); |
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| 249 | return; |
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| 250 | } |
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| 251 | |
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[3b4ddaf] | 252 | _ISR_Local_disable (level); |
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| 253 | |
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| 254 | while( d_addr <= final_address ) { |
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| 255 | _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); |
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| 256 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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| 257 | } |
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| 258 | |
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| 259 | _ISR_Local_enable (level); |
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| 260 | } |
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| 261 | |
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[4cf93658] | 262 | static void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes) |
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[3b4ddaf] | 263 | { |
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| 264 | const void * final_address; |
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| 265 | ISR_Level level; |
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| 266 | |
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| 267 | /* |
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| 268 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 269 | * the last address_t which needs to be pushed. Increment d_addr and push |
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| 270 | * the resulting line until final_address is passed. |
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| 271 | */ |
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| 272 | |
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| 273 | if( n_bytes == 0 ) |
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| 274 | /* Do nothing if number of bytes to flush is zero */ |
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| 275 | return; |
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| 276 | |
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| 277 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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| 278 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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| 279 | |
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[9bf9068] | 280 | if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { |
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| 281 | /* |
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| 282 | * Avoid iterating over the whole cache multiple times if the range is |
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| 283 | * larger than the cache size. |
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| 284 | */ |
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| 285 | _CPU_cache_invalidate_entire_data(); |
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| 286 | return; |
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| 287 | } |
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| 288 | |
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[3b4ddaf] | 289 | _ISR_Local_disable (level); |
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| 290 | |
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| 291 | while( d_addr <= final_address ) { |
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| 292 | _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); |
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| 293 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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| 294 | } |
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| 295 | |
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| 296 | _ISR_Local_enable (level); |
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| 297 | } |
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| 298 | |
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[4cf93658] | 299 | static void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes) |
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[3b4ddaf] | 300 | { |
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| 301 | const void * final_address; |
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| 302 | ISR_Level level; |
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| 303 | |
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| 304 | /* |
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| 305 | * Set i_addr to the beginning of the cache line; final_address indicates |
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| 306 | * the last address_t which needs to be pushed. Increment i_addr and push |
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| 307 | * the resulting line until final_address is passed. |
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| 308 | */ |
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| 309 | |
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| 310 | if( n_bytes == 0 ) |
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| 311 | /* Do nothing if number of bytes to flush is zero */ |
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| 312 | return; |
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| 313 | |
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| 314 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
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| 315 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
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| 316 | |
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[9bf9068] | 317 | if( final_address - i_addr > _CPU_cache_get_data_cache_size(0) ) { |
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| 318 | /* |
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| 319 | * Avoid iterating over the whole cache multiple times if the range is |
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| 320 | * larger than the cache size. |
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| 321 | */ |
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| 322 | _CPU_cache_invalidate_entire_instruction(); |
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| 323 | return; |
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| 324 | } |
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| 325 | |
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[3b4ddaf] | 326 | _ISR_Local_disable (level); |
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| 327 | |
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| 328 | while( i_addr <= final_address ) { |
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| 329 | _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) i_addr); |
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| 330 | i_addr = (void *)((size_t)i_addr + CPU_DATA_CACHE_ALIGNMENT); |
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| 331 | } |
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| 332 | |
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| 333 | _ISR_Local_enable (level); |
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[c080c343] | 334 | } |
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| 335 | |
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[4cf93658] | 336 | static void _CPU_cache_enable_data(void) |
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[c080c343] | 337 | { |
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[a59dd5c] | 338 | uint32_t sr; |
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| 339 | ISR_Level level; |
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| 340 | |
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| 341 | _ISR_Local_disable (level); |
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| 342 | |
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| 343 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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| 344 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE); |
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| 345 | |
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| 346 | _ISR_Local_enable(level); |
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[c080c343] | 347 | } |
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| 348 | |
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[4cf93658] | 349 | static void _CPU_cache_disable_data(void) |
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[c080c343] | 350 | { |
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[a59dd5c] | 351 | uint32_t sr; |
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| 352 | ISR_Level level; |
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[c080c343] | 353 | |
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[a59dd5c] | 354 | _ISR_Local_disable (level); |
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| 355 | |
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| 356 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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| 357 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE)); |
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| 358 | |
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| 359 | _ISR_Local_enable(level); |
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[c080c343] | 360 | } |
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| 361 | |
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[4cf93658] | 362 | static void _CPU_cache_enable_instruction(void) |
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[c080c343] | 363 | { |
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[a59dd5c] | 364 | uint32_t sr; |
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| 365 | ISR_Level level; |
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| 366 | |
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| 367 | _ISR_Local_disable (level); |
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| 368 | |
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| 369 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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| 370 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE); |
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[c080c343] | 371 | |
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[a59dd5c] | 372 | _ISR_Local_enable(level); |
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[c080c343] | 373 | } |
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| 374 | |
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[4cf93658] | 375 | static void _CPU_cache_disable_instruction(void) |
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[c080c343] | 376 | { |
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[a59dd5c] | 377 | uint32_t sr; |
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| 378 | ISR_Level level; |
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| 379 | |
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| 380 | _ISR_Local_disable (level); |
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| 381 | |
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| 382 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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| 383 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE)); |
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| 384 | |
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| 385 | _ISR_Local_enable(level); |
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[c080c343] | 386 | } |
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[4cf93658] | 387 | |
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| 388 | #include "../../../shared/cache/cacheimpl.h" |
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