1 | /* |
---|
2 | * COPYRIGHT (c) 2014, 2016 Ã
AC Microtec AB <www.aacmicrotec.com> |
---|
3 | * Contributor(s): |
---|
4 | * Karol Gugala <kgugala@antmicro.com> |
---|
5 | * Martin Werner <martin.werner@aacmicrotec.com> |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
---|
8 | * |
---|
9 | * COPYRIGHT (c) 1989-2006 |
---|
10 | * On-Line Applications Research Corporation (OAR). |
---|
11 | * |
---|
12 | * The license and distribution terms for this file may be |
---|
13 | * found in the file LICENSE in this distribution or at |
---|
14 | * http://www.rtems.org/license/LICENSE. |
---|
15 | */ |
---|
16 | |
---|
17 | #include <rtems/score/cpu.h> |
---|
18 | #include <rtems/score/interr.h> |
---|
19 | #include <rtems/score/or1k-utility.h> |
---|
20 | #include <rtems/score/percpu.h> |
---|
21 | |
---|
22 | #define CPU_DATA_CACHE_ALIGNMENT 32 |
---|
23 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 |
---|
24 | |
---|
25 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1 |
---|
26 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1 |
---|
27 | |
---|
28 | static inline size_t |
---|
29 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
---|
30 | { |
---|
31 | return (level == 0 || level == 1)? 8192 : 0; |
---|
32 | } |
---|
33 | |
---|
34 | static inline size_t |
---|
35 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
---|
36 | { |
---|
37 | return (level == 0 || level == 1)? 8192 : 0; |
---|
38 | } |
---|
39 | |
---|
40 | static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr) |
---|
41 | { |
---|
42 | ISR_Level level; |
---|
43 | |
---|
44 | _ISR_Local_disable (level); |
---|
45 | |
---|
46 | _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr); |
---|
47 | |
---|
48 | _ISR_Local_enable(level); |
---|
49 | } |
---|
50 | |
---|
51 | static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr) |
---|
52 | { |
---|
53 | ISR_Level level; |
---|
54 | |
---|
55 | _ISR_Local_disable (level); |
---|
56 | |
---|
57 | _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr); |
---|
58 | |
---|
59 | _ISR_Local_enable(level); |
---|
60 | } |
---|
61 | |
---|
62 | static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr) |
---|
63 | { |
---|
64 | ISR_Level level; |
---|
65 | |
---|
66 | _ISR_Local_disable (level); |
---|
67 | |
---|
68 | _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr); |
---|
69 | |
---|
70 | _ISR_Local_enable(level); |
---|
71 | } |
---|
72 | |
---|
73 | static inline void _CPU_OR1K_Cache_instruction_block_prefetch |
---|
74 | (const void *d_addr) |
---|
75 | { |
---|
76 | ISR_Level level; |
---|
77 | |
---|
78 | _ISR_Local_disable (level); |
---|
79 | |
---|
80 | _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr); |
---|
81 | |
---|
82 | _ISR_Local_enable(level); |
---|
83 | } |
---|
84 | |
---|
85 | static inline void _CPU_OR1K_Cache_instruction_block_lock |
---|
86 | (const void *d_addr) |
---|
87 | { |
---|
88 | ISR_Level level; |
---|
89 | |
---|
90 | _ISR_Local_disable (level); |
---|
91 | |
---|
92 | _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr); |
---|
93 | |
---|
94 | _ISR_Local_enable(level); |
---|
95 | } |
---|
96 | |
---|
97 | /* Implement RTEMS cache manager functions */ |
---|
98 | |
---|
99 | static void _CPU_cache_freeze_data(void) |
---|
100 | { |
---|
101 | /* Do nothing */ |
---|
102 | } |
---|
103 | |
---|
104 | static void _CPU_cache_unfreeze_data(void) |
---|
105 | { |
---|
106 | /* Do nothing */ |
---|
107 | } |
---|
108 | |
---|
109 | static void _CPU_cache_freeze_instruction(void) |
---|
110 | { |
---|
111 | /* Do nothing */ |
---|
112 | } |
---|
113 | |
---|
114 | static void _CPU_cache_unfreeze_instruction(void) |
---|
115 | { |
---|
116 | /* Do nothing */ |
---|
117 | } |
---|
118 | |
---|
119 | static void _CPU_cache_flush_entire_data(void) |
---|
120 | { |
---|
121 | size_t addr; |
---|
122 | ISR_Level level; |
---|
123 | |
---|
124 | _ISR_Local_disable (level); |
---|
125 | |
---|
126 | /* We have only 0 level cache so we do not need to invalidate others */ |
---|
127 | for ( |
---|
128 | addr = _CPU_cache_get_data_cache_size(0); |
---|
129 | addr > 0; |
---|
130 | addr -= CPU_DATA_CACHE_ALIGNMENT |
---|
131 | ) { |
---|
132 | _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) addr); |
---|
133 | } |
---|
134 | |
---|
135 | _ISR_Local_enable (level); |
---|
136 | } |
---|
137 | |
---|
138 | static void _CPU_cache_invalidate_entire_data(void) |
---|
139 | { |
---|
140 | size_t addr; |
---|
141 | ISR_Level level; |
---|
142 | |
---|
143 | _ISR_Local_disable (level); |
---|
144 | |
---|
145 | /* We have only 0 level cache so we do not need to invalidate others */ |
---|
146 | for ( |
---|
147 | addr = _CPU_cache_get_data_cache_size(0); |
---|
148 | addr > 0; |
---|
149 | addr -= CPU_DATA_CACHE_ALIGNMENT |
---|
150 | ) { |
---|
151 | _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) addr); |
---|
152 | } |
---|
153 | |
---|
154 | _ISR_Local_enable (level); |
---|
155 | } |
---|
156 | |
---|
157 | static void _CPU_cache_invalidate_entire_instruction(void) |
---|
158 | { |
---|
159 | size_t addr; |
---|
160 | ISR_Level level; |
---|
161 | |
---|
162 | _ISR_Local_disable (level); |
---|
163 | |
---|
164 | /* We have only 0 level cache so we do not need to invalidate others */ |
---|
165 | for ( |
---|
166 | addr = _CPU_cache_get_instruction_cache_size(0); |
---|
167 | addr > 0; |
---|
168 | addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT |
---|
169 | ) { |
---|
170 | _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) addr); |
---|
171 | } |
---|
172 | |
---|
173 | /* Flush instructions out of instruction buffer */ |
---|
174 | __asm__ volatile("l.nop"); |
---|
175 | __asm__ volatile("l.nop"); |
---|
176 | __asm__ volatile("l.nop"); |
---|
177 | __asm__ volatile("l.nop"); |
---|
178 | __asm__ volatile("l.nop"); |
---|
179 | |
---|
180 | _ISR_Local_enable (level); |
---|
181 | } |
---|
182 | |
---|
183 | /* |
---|
184 | * The range functions are copied almost verbatim from the generic |
---|
185 | * implementations in c/src/lib/libcpu/shared/src/cache_manager.c. The main |
---|
186 | * modification here is avoiding reapeated off/on toggling of the ISR for each |
---|
187 | * cache line operation. |
---|
188 | */ |
---|
189 | |
---|
190 | static void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes) |
---|
191 | { |
---|
192 | const void * final_address; |
---|
193 | ISR_Level level; |
---|
194 | |
---|
195 | /* |
---|
196 | * Set d_addr to the beginning of the cache line; final_address indicates |
---|
197 | * the last address_t which needs to be pushed. Increment d_addr and push |
---|
198 | * the resulting line until final_address is passed. |
---|
199 | */ |
---|
200 | |
---|
201 | if( n_bytes == 0 ) |
---|
202 | /* Do nothing if number of bytes to flush is zero */ |
---|
203 | return; |
---|
204 | |
---|
205 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
---|
206 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
---|
207 | |
---|
208 | if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { |
---|
209 | /* |
---|
210 | * Avoid iterating over the whole cache multiple times if the range is |
---|
211 | * larger than the cache size. |
---|
212 | */ |
---|
213 | _CPU_cache_flush_entire_data(); |
---|
214 | return; |
---|
215 | } |
---|
216 | |
---|
217 | _ISR_Local_disable (level); |
---|
218 | |
---|
219 | while( d_addr <= final_address ) { |
---|
220 | _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr); |
---|
221 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
---|
222 | } |
---|
223 | |
---|
224 | _ISR_Local_enable (level); |
---|
225 | } |
---|
226 | |
---|
227 | static void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes) |
---|
228 | { |
---|
229 | const void * final_address; |
---|
230 | ISR_Level level; |
---|
231 | |
---|
232 | /* |
---|
233 | * Set d_addr to the beginning of the cache line; final_address indicates |
---|
234 | * the last address_t which needs to be pushed. Increment d_addr and push |
---|
235 | * the resulting line until final_address is passed. |
---|
236 | */ |
---|
237 | |
---|
238 | if( n_bytes == 0 ) |
---|
239 | /* Do nothing if number of bytes to flush is zero */ |
---|
240 | return; |
---|
241 | |
---|
242 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
---|
243 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
---|
244 | |
---|
245 | if( final_address - d_addr > _CPU_cache_get_data_cache_size(0) ) { |
---|
246 | /* |
---|
247 | * Avoid iterating over the whole cache multiple times if the range is |
---|
248 | * larger than the cache size. |
---|
249 | */ |
---|
250 | _CPU_cache_invalidate_entire_data(); |
---|
251 | return; |
---|
252 | } |
---|
253 | |
---|
254 | _ISR_Local_disable (level); |
---|
255 | |
---|
256 | while( d_addr <= final_address ) { |
---|
257 | _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr); |
---|
258 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
---|
259 | } |
---|
260 | |
---|
261 | _ISR_Local_enable (level); |
---|
262 | } |
---|
263 | |
---|
264 | static void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes) |
---|
265 | { |
---|
266 | const void * final_address; |
---|
267 | ISR_Level level; |
---|
268 | |
---|
269 | /* |
---|
270 | * Set i_addr to the beginning of the cache line; final_address indicates |
---|
271 | * the last address_t which needs to be pushed. Increment i_addr and push |
---|
272 | * the resulting line until final_address is passed. |
---|
273 | */ |
---|
274 | |
---|
275 | if( n_bytes == 0 ) |
---|
276 | /* Do nothing if number of bytes to flush is zero */ |
---|
277 | return; |
---|
278 | |
---|
279 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
---|
280 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
---|
281 | |
---|
282 | if( final_address - i_addr > _CPU_cache_get_data_cache_size(0) ) { |
---|
283 | /* |
---|
284 | * Avoid iterating over the whole cache multiple times if the range is |
---|
285 | * larger than the cache size. |
---|
286 | */ |
---|
287 | _CPU_cache_invalidate_entire_instruction(); |
---|
288 | return; |
---|
289 | } |
---|
290 | |
---|
291 | _ISR_Local_disable (level); |
---|
292 | |
---|
293 | while( i_addr <= final_address ) { |
---|
294 | _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) i_addr); |
---|
295 | i_addr = (void *)((size_t)i_addr + CPU_DATA_CACHE_ALIGNMENT); |
---|
296 | } |
---|
297 | |
---|
298 | _ISR_Local_enable (level); |
---|
299 | } |
---|
300 | |
---|
301 | static void _CPU_cache_enable_data(void) |
---|
302 | { |
---|
303 | uint32_t sr; |
---|
304 | ISR_Level level; |
---|
305 | |
---|
306 | _ISR_Local_disable (level); |
---|
307 | |
---|
308 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
---|
309 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE); |
---|
310 | |
---|
311 | _ISR_Local_enable(level); |
---|
312 | } |
---|
313 | |
---|
314 | static void _CPU_cache_disable_data(void) |
---|
315 | { |
---|
316 | uint32_t sr; |
---|
317 | ISR_Level level; |
---|
318 | |
---|
319 | _ISR_Local_disable (level); |
---|
320 | |
---|
321 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
---|
322 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE)); |
---|
323 | |
---|
324 | _ISR_Local_enable(level); |
---|
325 | } |
---|
326 | |
---|
327 | static void _CPU_cache_enable_instruction(void) |
---|
328 | { |
---|
329 | uint32_t sr; |
---|
330 | ISR_Level level; |
---|
331 | |
---|
332 | _ISR_Local_disable (level); |
---|
333 | |
---|
334 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
---|
335 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE); |
---|
336 | |
---|
337 | _ISR_Local_enable(level); |
---|
338 | } |
---|
339 | |
---|
340 | static void _CPU_cache_disable_instruction(void) |
---|
341 | { |
---|
342 | uint32_t sr; |
---|
343 | ISR_Level level; |
---|
344 | |
---|
345 | _ISR_Local_disable (level); |
---|
346 | |
---|
347 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
---|
348 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE)); |
---|
349 | |
---|
350 | _ISR_Local_enable(level); |
---|
351 | } |
---|
352 | |
---|
353 | #include "../../../shared/cache/cacheimpl.h" |
---|