1 | SYSTEM Nios2_system |
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2 | { |
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3 | System_Wizard_Version = "4.10"; |
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4 | System_Wizard_Build = "181"; |
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5 | WIZARD_SCRIPT_ARGUMENTS |
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6 | { |
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7 | device_family = "STRATIX"; |
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8 | clock_freq = "50000000"; |
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9 | generate_hdl = "0"; |
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10 | generate_sdk = "0"; |
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11 | do_build_sim = "0"; |
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12 | hdl_language = "vhdl"; |
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13 | view_master_columns = "1"; |
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14 | view_master_priorities = "0"; |
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15 | board_class = ""; |
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16 | name_column_width = "75"; |
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17 | desc_column_width = "75"; |
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18 | bustype_column_width = "0"; |
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19 | base_column_width = "75"; |
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20 | end_column_width = "75"; |
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21 | view_frame_window = "170:208:1280:900"; |
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22 | do_log_history = "0"; |
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23 | device_family_id = "STRATIX"; |
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24 | BOARD_INFO |
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25 | { |
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26 | device_is_engineering_sample = ""; |
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27 | } |
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28 | } |
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29 | MODULE cpu_0 |
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30 | { |
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31 | class = "altera_nios2"; |
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32 | class_version = "1.0"; |
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33 | iss_model_name = "altera_nios2"; |
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34 | HDL_INFO |
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35 | { |
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36 | PLI_Files = ""; |
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37 | Simulation_HDL_Files = ""; |
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38 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd"; |
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39 | Precompiled_Simulation_Library_Files = ""; |
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40 | Synthesis_Only_Files = ""; |
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41 | } |
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42 | MASTER instruction_master |
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43 | { |
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44 | PORT_WIRING |
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45 | { |
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46 | PORT i_address |
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47 | { |
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48 | direction = "output"; |
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49 | type = "address"; |
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50 | width = "28"; |
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51 | } |
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52 | PORT i_read |
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53 | { |
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54 | direction = "output"; |
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55 | type = "read"; |
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56 | width = "1"; |
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57 | } |
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58 | PORT i_readdata |
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59 | { |
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60 | direction = "input"; |
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61 | type = "readdata"; |
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62 | width = "32"; |
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63 | } |
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64 | PORT i_readdatavalid |
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65 | { |
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66 | direction = "input"; |
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67 | type = "readdatavalid"; |
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68 | width = "1"; |
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69 | } |
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70 | PORT i_waitrequest |
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71 | { |
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72 | direction = "input"; |
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73 | type = "waitrequest"; |
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74 | width = "1"; |
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75 | } |
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76 | } |
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77 | SYSTEM_BUILDER_INFO |
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78 | { |
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79 | Bus_Type = "avalon"; |
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80 | Data_Width = "32"; |
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81 | Max_Address_Width = "32"; |
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82 | Address_Width = "8"; |
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83 | Is_Instruction_Master = "1"; |
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84 | Has_IRQ = "0"; |
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85 | Irq_Scheme = "individual_requests"; |
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86 | Interrupt_Range = "0-0"; |
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87 | Is_Enabled = "1"; |
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88 | } |
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89 | } |
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90 | MASTER data_master |
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91 | { |
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92 | PORT_WIRING |
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93 | { |
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94 | PORT clk |
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95 | { |
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96 | direction = "input"; |
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97 | type = "clk"; |
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98 | width = "1"; |
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99 | } |
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100 | PORT d_address |
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101 | { |
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102 | direction = "output"; |
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103 | type = "address"; |
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104 | width = "28"; |
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105 | } |
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106 | PORT d_byteenable |
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107 | { |
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108 | direction = "output"; |
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109 | type = "byteenable"; |
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110 | width = "4"; |
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111 | } |
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112 | PORT d_irq |
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113 | { |
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114 | direction = "input"; |
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115 | type = "irq"; |
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116 | width = "32"; |
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117 | } |
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118 | PORT d_read |
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119 | { |
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120 | direction = "output"; |
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121 | type = "read"; |
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122 | width = "1"; |
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123 | } |
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124 | PORT d_readdata |
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125 | { |
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126 | direction = "input"; |
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127 | type = "readdata"; |
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128 | width = "32"; |
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129 | } |
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130 | PORT d_waitrequest |
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131 | { |
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132 | direction = "input"; |
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133 | type = "waitrequest"; |
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134 | width = "1"; |
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135 | } |
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136 | PORT d_write |
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137 | { |
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138 | direction = "output"; |
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139 | type = "write"; |
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140 | width = "1"; |
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141 | } |
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142 | PORT d_writedata |
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143 | { |
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144 | direction = "output"; |
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145 | type = "writedata"; |
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146 | width = "32"; |
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147 | } |
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148 | PORT jtag_debug_module_debugaccess_to_roms |
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149 | { |
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150 | direction = "output"; |
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151 | type = "debugaccess"; |
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152 | width = "1"; |
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153 | } |
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154 | } |
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155 | SYSTEM_BUILDER_INFO |
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156 | { |
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157 | Register_Incoming_Signals = "1"; |
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158 | Bus_Type = "avalon"; |
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159 | Data_Width = "32"; |
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160 | Max_Address_Width = "32"; |
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161 | Address_Width = "8"; |
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162 | Is_Data_Master = "1"; |
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163 | Has_IRQ = "1"; |
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164 | Irq_Scheme = "individual_requests"; |
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165 | Interrupt_Range = "0-31"; |
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166 | Is_Enabled = "1"; |
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167 | } |
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168 | } |
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169 | SLAVE oci_core |
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170 | { |
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171 | PORT_WIRING |
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172 | { |
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173 | PORT byteenable |
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174 | { |
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175 | direction = "input"; |
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176 | type = "byteenable"; |
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177 | width = "4"; |
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178 | } |
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179 | PORT oci_core_address |
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180 | { |
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181 | direction = "input"; |
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182 | type = "address"; |
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183 | width = "9"; |
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184 | } |
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185 | PORT oci_core_begintransfer |
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186 | { |
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187 | direction = "input"; |
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188 | type = "begintransfer"; |
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189 | width = "1"; |
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190 | } |
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191 | PORT oci_core_clk |
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192 | { |
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193 | direction = "input"; |
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194 | type = "clk"; |
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195 | width = "1"; |
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196 | } |
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197 | PORT oci_core_readdata |
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198 | { |
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199 | direction = "output"; |
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200 | type = "readdata"; |
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201 | width = "32"; |
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202 | } |
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203 | PORT oci_core_reset |
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204 | { |
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205 | direction = "input"; |
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206 | type = "reset"; |
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207 | width = "1"; |
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208 | } |
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209 | PORT oci_core_resetrequest |
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210 | { |
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211 | direction = "output"; |
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212 | type = "resetrequest"; |
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213 | width = "1"; |
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214 | } |
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215 | PORT oci_core_select |
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216 | { |
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217 | direction = "input"; |
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218 | type = "chipselect"; |
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219 | width = "1"; |
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220 | } |
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221 | PORT oci_core_write |
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222 | { |
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223 | direction = "input"; |
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224 | type = "write"; |
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225 | width = "1"; |
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226 | } |
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227 | PORT oci_core_writedata |
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228 | { |
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229 | direction = "input"; |
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230 | type = "writedata"; |
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231 | width = "32"; |
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232 | } |
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233 | PORT reset_n |
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234 | { |
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235 | direction = "input"; |
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236 | type = "reset_n"; |
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237 | width = "1"; |
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238 | } |
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239 | } |
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240 | SYSTEM_BUILDER_INFO |
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241 | { |
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242 | Read_Wait_States = "1"; |
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243 | Write_Wait_States = "1"; |
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244 | Register_Incoming_Signals = "1"; |
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245 | Bus_Type = "avalon"; |
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246 | Data_Width = "32"; |
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247 | Address_Width = "9"; |
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248 | Accepts_Internal_Connections = "1"; |
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249 | Requires_Internal_Connections = "instruction_master,data_master"; |
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250 | Accepts_External_Connections = "0"; |
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251 | Is_Enabled = "1"; |
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252 | Address_Alignment = "dynamic"; |
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253 | Base_Address = "0x08100000"; |
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254 | Is_Memory_Device = "1"; |
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255 | Is_Printable_Device = "1"; |
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256 | Uses_Tri_State_Data_Bus = "0"; |
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257 | Has_IRQ = "0"; |
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258 | JTAG_Hub_Base_Id = "69702"; |
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259 | JTAG_Hub_Instance_Id = "0"; |
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260 | MASTERED_BY cpu_0/instruction_master |
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261 | { |
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262 | priority = "1"; |
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263 | } |
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264 | MASTERED_BY cpu_0/data_master |
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265 | { |
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266 | priority = "1"; |
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267 | } |
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268 | IRQ_MASTER cpu_0/data_master |
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269 | { |
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270 | IRQ_Number = "NC"; |
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271 | } |
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272 | } |
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273 | } |
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274 | WIZARD_SCRIPT_ARGUMENTS |
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275 | { |
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276 | CPU_Architecture = "nios2"; |
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277 | do_generate = "1"; |
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278 | cpu_selection = "f"; |
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279 | CPU_Implementation = "fast"; |
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280 | cache_has_dcache = "1"; |
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281 | cache_has_icache = "1"; |
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282 | cache_dcache_size = "2048"; |
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283 | cache_icache_size = "4096"; |
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284 | include_debug = "0"; |
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285 | include_trace = "0"; |
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286 | include_oci = "1"; |
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287 | debug_level = "2"; |
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288 | oci_offchip_trace = "0"; |
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289 | oci_onchip_trace = "0"; |
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290 | oci_trace_addr_width = "7"; |
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291 | oci_num_xbrk = "0"; |
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292 | oci_num_dbrk = "0"; |
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293 | oci_dbrk_trace = "0"; |
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294 | oci_dbrk_pairs = "0"; |
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295 | oci_debugreq_signals = "0"; |
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296 | oci_instance_number = "1"; |
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297 | hardware_multiply_present = "1"; |
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298 | hardware_divide_present = "0"; |
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299 | bht_ptr_sz = "8"; |
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300 | reset_slave = "onchip_memory_0/s1"; |
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301 | reset_offset = "0x00000000"; |
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302 | exc_slave = "onchip_memory_0/s1"; |
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303 | exc_offset = "0x00000600"; |
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304 | break_slave = "cpu_0/jtag_debug_module"; |
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305 | break_offset = "0x00000020"; |
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306 | altera_internal_test = "0"; |
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307 | full_waveform_signals = "0"; |
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308 | activate_model_checker = "0"; |
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309 | bit_31_bypass_dcache = "1"; |
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310 | always_bypass_dcache = "0"; |
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311 | always_unsigned_mul = "0"; |
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312 | consistent_synthesis = "0"; |
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313 | ibuf_ptr_sz = "4"; |
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314 | jtb_ptr_sz = "5"; |
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315 | performance_counters_present = "0"; |
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316 | performance_counters_width = "32"; |
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317 | ras_ptr_sz = "4"; |
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318 | inst_decode_in_submodule = "0"; |
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319 | register_dependency_in_submodule = "0"; |
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320 | source_operands_in_submodule = "0"; |
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321 | alu_in_submodule = "0"; |
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322 | stdata_in_submodule = "0"; |
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323 | shift_rot_2N_in_submodule = "0"; |
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324 | control_regs_in_submodule = "0"; |
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325 | mult_cell_in_submodule = "0"; |
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326 | M_inst_result_mux_in_submodule = "0"; |
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327 | dcache_load_aligner_in_submodule = "0"; |
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328 | hardware_divide_in_submodule = "0"; |
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329 | mult_result_mux_in_submodule = "0"; |
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330 | shift_rotate_in_submodule = "0"; |
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331 | register_file_write_data_mux_in_submodule = "0"; |
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332 | avalon_imaster_in_submodule = "0"; |
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333 | avalon_dmaster_in_submodule = "0"; |
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334 | avalon_load_aligner_in_submodule = "0"; |
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335 | hbreak_test = "0"; |
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336 | iss_trace_on = "0"; |
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337 | iss_trace_warning = "1"; |
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338 | iss_trace_info = "1"; |
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339 | iss_trace_disassembly = "0"; |
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340 | iss_trace_registers = "0"; |
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341 | iss_trace_instr_count = "0"; |
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342 | iss_software_debug = "0"; |
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343 | iss_software_debug_port = "9996"; |
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344 | iss_memory_dump_start = ""; |
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345 | iss_memory_dump_end = ""; |
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346 | CONSTANTS |
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347 | { |
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348 | CONSTANT __nios_catch_irqs__ |
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349 | { |
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350 | value = "1"; |
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351 | comment = "Include panic handler for all irqs (needs uart)"; |
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352 | } |
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353 | CONSTANT __nios_use_constructors__ |
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354 | { |
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355 | value = "1"; |
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356 | comment = "Call c++ static constructors"; |
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357 | } |
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358 | CONSTANT __nios_use_small_printf__ |
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359 | { |
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360 | value = "1"; |
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361 | comment = "Smaller non-ANSI printf, with no floating point"; |
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362 | } |
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363 | CONSTANT nasys_has_icache |
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364 | { |
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365 | value = "0"; |
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366 | comment = "True if instruction cache present"; |
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367 | } |
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368 | CONSTANT nasys_icache_size |
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369 | { |
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370 | value = "4096"; |
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371 | comment = "Size in bytes of instruction cache"; |
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372 | } |
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373 | CONSTANT nasys_icache_line_size |
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374 | { |
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375 | value = "32"; |
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376 | comment = "Size in bytes of each icache line"; |
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377 | } |
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378 | CONSTANT nasys_icache_line_size_log2 |
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379 | { |
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380 | value = "5"; |
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381 | comment = "Log2 size in bytes of each icache line"; |
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382 | } |
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383 | CONSTANT nasys_has_dcache |
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384 | { |
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385 | value = "0"; |
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386 | comment = "True if instruction cache present"; |
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387 | } |
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388 | CONSTANT nasys_dcache_size |
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389 | { |
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390 | value = "2048"; |
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391 | comment = "Size in bytes of data cache"; |
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392 | } |
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393 | CONSTANT nasys_dcache_line_size |
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394 | { |
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395 | value = "4"; |
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396 | comment = "Size in bytes of each dcache line"; |
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397 | } |
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398 | CONSTANT nasys_dcache_line_size_log2 |
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399 | { |
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400 | value = "2"; |
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401 | comment = "Log2 size in bytes of each dcache line"; |
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402 | } |
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403 | } |
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404 | mainmem_slave = ""; |
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405 | datamem_slave = ""; |
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406 | maincomm_slave = ""; |
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407 | debugcomm_slave = ""; |
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408 | germs_monitor_id = ""; |
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409 | asp_debug = "0"; |
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410 | asp_core_debug = "0"; |
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411 | include_third_party_debug_port = "0"; |
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412 | oci_data_trace = "0"; |
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413 | oci_num_pm = "0"; |
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414 | oci_pm_width = "40"; |
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415 | oci_trigger_arming = "1"; |
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416 | break_slave_override = ""; |
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417 | break_offset_override = "0x20"; |
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418 | legacy_sdk_support = "0"; |
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419 | altera_show_unreleased_features = "0"; |
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420 | illegal_instructions_trap = "0"; |
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421 | remove_hardware_multiplier = "0"; |
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422 | large_dcache_allow_mram = "0"; |
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423 | cache_omit_dcache = "0"; |
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424 | cache_omit_icache = "0"; |
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425 | omit_instruction_master = "0"; |
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426 | omit_data_master = "0"; |
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427 | num_local_data_masters = "0"; |
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428 | num_local_instruction_masters = "0"; |
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429 | gui_branch_prediction_type = "Automatic"; |
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430 | branch_prediction_type = "Dynamic"; |
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431 | bht_index_pc_only = "0"; |
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432 | mmu_present = "0"; |
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433 | process_id_num_bits = "10"; |
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434 | dtlb_ptr_sz = "7"; |
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435 | dtlb_num_ways = "4"; |
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436 | udtlb_num_entries = "6"; |
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437 | itlb_ptr_sz = "7"; |
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438 | itlb_num_ways = "4"; |
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439 | uitlb_num_entries = "4"; |
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440 | fast_tlb_miss_exc_slave = "onchip_memory_0/s1"; |
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441 | fast_tlb_miss_exc_offset = "0x00000000"; |
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442 | always_encrypt = "1"; |
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443 | activate_monitors = "1"; |
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444 | activate_test_end_checker = "0"; |
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445 | activate_trace = "1"; |
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446 | clear_x_bits_ld_non_bypass = "1"; |
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447 | hdl_sim_caches_cleared = "1"; |
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448 | allow_full_address_range = "0"; |
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449 | Boot_Copier = "boot_loader_cfi.srec"; |
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450 | Boot_Copier_EPCS = "boot_loader_epcs.srec"; |
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451 | license_status = "ocp"; |
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452 | } |
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453 | SYSTEM_BUILDER_INFO |
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454 | { |
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455 | Parameters_Signature = ""; |
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456 | Is_CPU = "1"; |
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457 | Is_Enabled = "1"; |
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458 | Instantiate_In_System_Module = "1"; |
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459 | Default_Module_Name = "cpu"; |
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460 | View |
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461 | { |
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462 | MESSAGES |
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463 | { |
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464 | } |
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465 | Is_Collapsed = "0"; |
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466 | Settings_Summary = "Nios II/f |
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467 | <br> 4-Kbyte Instruction Cache |
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468 | <br> 2-Kbyte Data Cache |
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469 | <br> JTAG Debug Module |
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470 | "; |
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471 | } |
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472 | Required_Device_Family = "STRATIX,STRATIXII,CYCLONE"; |
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473 | } |
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474 | SOFTWARE_COMPONENT altera_hal |
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475 | { |
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476 | class = "altera_hal"; |
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477 | class_version = "1.0"; |
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478 | WIZARD_SCRIPT_ARGUMENTS |
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479 | { |
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480 | } |
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481 | SYSTEM_BUILDER_INFO |
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482 | { |
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483 | Is_Enabled = "1"; |
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484 | } |
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485 | } |
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486 | SOFTWARE_COMPONENT altera_nios2_test |
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487 | { |
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488 | class = "altera_nios2_test"; |
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489 | class_version = "2.0"; |
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490 | WIZARD_SCRIPT_ARGUMENTS |
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491 | { |
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492 | CONSTANTS |
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493 | { |
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494 | CONSTANT debug_on |
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495 | { |
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496 | value = "0"; |
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497 | comment = "Enable debug features"; |
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498 | } |
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499 | } |
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500 | } |
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501 | SYSTEM_BUILDER_INFO |
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502 | { |
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503 | Is_Enabled = "0"; |
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504 | } |
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505 | } |
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506 | SOFTWARE_COMPONENT altera_plugs_library |
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507 | { |
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508 | class = "altera_plugs_library"; |
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509 | class_version = "2.1"; |
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510 | WIZARD_SCRIPT_ARGUMENTS |
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511 | { |
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512 | CONSTANTS |
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513 | { |
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514 | CONSTANT PLUGS_PLUG_COUNT |
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515 | { |
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516 | value = "5"; |
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517 | comment = "Maximum number of plugs"; |
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518 | } |
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519 | CONSTANT PLUGS_ADAPTER_COUNT |
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520 | { |
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521 | value = "2"; |
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522 | comment = "Maximum number of adapters"; |
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523 | } |
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524 | CONSTANT PLUGS_DNS |
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525 | { |
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526 | value = "1"; |
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527 | comment = "Have routines for DNS lookups"; |
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528 | } |
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529 | CONSTANT PLUGS_PING |
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530 | { |
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531 | value = "1"; |
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532 | comment = "Respond to icmp echo (ping) messages"; |
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533 | } |
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534 | CONSTANT PLUGS_TCP |
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535 | { |
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536 | value = "1"; |
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537 | comment = "Support tcp in/out connections"; |
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538 | } |
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539 | CONSTANT PLUGS_IRQ |
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540 | { |
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541 | value = "1"; |
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542 | comment = "Run at interrupte level"; |
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543 | } |
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544 | CONSTANT PLUGS_DEBUG |
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545 | { |
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546 | value = "1"; |
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547 | comment = "Support debug routines"; |
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548 | } |
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549 | } |
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550 | } |
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551 | SYSTEM_BUILDER_INFO |
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552 | { |
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553 | Is_Enabled = "1"; |
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554 | } |
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555 | } |
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556 | PORT_WIRING |
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557 | { |
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558 | } |
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559 | SIMULATION |
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560 | { |
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561 | DISPLAY |
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562 | { |
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563 | SIGNAL aaa |
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564 | { |
---|
565 | format = "Logic"; |
---|
566 | name = "i_readdata"; |
---|
567 | radix = "hexadecimal"; |
---|
568 | } |
---|
569 | SIGNAL aab |
---|
570 | { |
---|
571 | format = "Logic"; |
---|
572 | name = "i_readdatavalid"; |
---|
573 | radix = "hexadecimal"; |
---|
574 | } |
---|
575 | SIGNAL aac |
---|
576 | { |
---|
577 | format = "Logic"; |
---|
578 | name = "i_waitrequest"; |
---|
579 | radix = "hexadecimal"; |
---|
580 | } |
---|
581 | SIGNAL aad |
---|
582 | { |
---|
583 | format = "Logic"; |
---|
584 | name = "i_address"; |
---|
585 | radix = "hexadecimal"; |
---|
586 | } |
---|
587 | SIGNAL aae |
---|
588 | { |
---|
589 | format = "Logic"; |
---|
590 | name = "i_read"; |
---|
591 | radix = "hexadecimal"; |
---|
592 | } |
---|
593 | SIGNAL aaf |
---|
594 | { |
---|
595 | format = "Logic"; |
---|
596 | name = "clk"; |
---|
597 | radix = "hexadecimal"; |
---|
598 | } |
---|
599 | SIGNAL aag |
---|
600 | { |
---|
601 | format = "Logic"; |
---|
602 | name = "reset_n"; |
---|
603 | radix = "hexadecimal"; |
---|
604 | } |
---|
605 | SIGNAL aah |
---|
606 | { |
---|
607 | format = "Logic"; |
---|
608 | name = "d_readdata"; |
---|
609 | radix = "hexadecimal"; |
---|
610 | } |
---|
611 | SIGNAL aai |
---|
612 | { |
---|
613 | format = "Logic"; |
---|
614 | name = "d_waitrequest"; |
---|
615 | radix = "hexadecimal"; |
---|
616 | } |
---|
617 | SIGNAL aaj |
---|
618 | { |
---|
619 | format = "Logic"; |
---|
620 | name = "d_irq"; |
---|
621 | radix = "hexadecimal"; |
---|
622 | } |
---|
623 | SIGNAL aak |
---|
624 | { |
---|
625 | format = "Logic"; |
---|
626 | name = "d_address"; |
---|
627 | radix = "hexadecimal"; |
---|
628 | } |
---|
629 | SIGNAL aal |
---|
630 | { |
---|
631 | format = "Logic"; |
---|
632 | name = "d_byteenable"; |
---|
633 | radix = "hexadecimal"; |
---|
634 | } |
---|
635 | SIGNAL aam |
---|
636 | { |
---|
637 | format = "Logic"; |
---|
638 | name = "d_read"; |
---|
639 | radix = "hexadecimal"; |
---|
640 | } |
---|
641 | SIGNAL aan |
---|
642 | { |
---|
643 | format = "Logic"; |
---|
644 | name = "d_write"; |
---|
645 | radix = "hexadecimal"; |
---|
646 | } |
---|
647 | SIGNAL aao |
---|
648 | { |
---|
649 | format = "Logic"; |
---|
650 | name = "d_writedata"; |
---|
651 | radix = "hexadecimal"; |
---|
652 | } |
---|
653 | SIGNAL aap |
---|
654 | { |
---|
655 | format = "Divider"; |
---|
656 | name = "base pipeline"; |
---|
657 | radix = ""; |
---|
658 | } |
---|
659 | SIGNAL aaq |
---|
660 | { |
---|
661 | format = "Logic"; |
---|
662 | name = "clk"; |
---|
663 | radix = "hexadecimal"; |
---|
664 | } |
---|
665 | SIGNAL aar |
---|
666 | { |
---|
667 | format = "Logic"; |
---|
668 | name = "reset_n"; |
---|
669 | radix = "hexadecimal"; |
---|
670 | } |
---|
671 | SIGNAL aas |
---|
672 | { |
---|
673 | format = "Logic"; |
---|
674 | name = "D_stall"; |
---|
675 | radix = "hexadecimal"; |
---|
676 | } |
---|
677 | SIGNAL aat |
---|
678 | { |
---|
679 | format = "Logic"; |
---|
680 | name = "A_stall"; |
---|
681 | radix = "hexadecimal"; |
---|
682 | } |
---|
683 | SIGNAL aau |
---|
684 | { |
---|
685 | format = "Logic"; |
---|
686 | name = "F_pcb_nxt"; |
---|
687 | radix = "hexadecimal"; |
---|
688 | } |
---|
689 | SIGNAL aav |
---|
690 | { |
---|
691 | format = "Logic"; |
---|
692 | name = "F_pcb"; |
---|
693 | radix = "hexadecimal"; |
---|
694 | } |
---|
695 | SIGNAL aaw |
---|
696 | { |
---|
697 | format = "Logic"; |
---|
698 | name = "D_pcb"; |
---|
699 | radix = "hexadecimal"; |
---|
700 | } |
---|
701 | SIGNAL aax |
---|
702 | { |
---|
703 | format = "Logic"; |
---|
704 | name = "E_pcb"; |
---|
705 | radix = "hexadecimal"; |
---|
706 | } |
---|
707 | SIGNAL aay |
---|
708 | { |
---|
709 | format = "Logic"; |
---|
710 | name = "M_pcb"; |
---|
711 | radix = "hexadecimal"; |
---|
712 | } |
---|
713 | SIGNAL aaz |
---|
714 | { |
---|
715 | format = "Logic"; |
---|
716 | name = "A_pcb"; |
---|
717 | radix = "hexadecimal"; |
---|
718 | } |
---|
719 | SIGNAL aba |
---|
720 | { |
---|
721 | format = "Logic"; |
---|
722 | name = "W_pcb"; |
---|
723 | radix = "hexadecimal"; |
---|
724 | } |
---|
725 | SIGNAL abb |
---|
726 | { |
---|
727 | format = "Logic"; |
---|
728 | name = "F_vinst"; |
---|
729 | radix = "ascii"; |
---|
730 | } |
---|
731 | SIGNAL abc |
---|
732 | { |
---|
733 | format = "Logic"; |
---|
734 | name = "D_vinst"; |
---|
735 | radix = "ascii"; |
---|
736 | } |
---|
737 | SIGNAL abd |
---|
738 | { |
---|
739 | format = "Logic"; |
---|
740 | name = "E_vinst"; |
---|
741 | radix = "ascii"; |
---|
742 | } |
---|
743 | SIGNAL abe |
---|
744 | { |
---|
745 | format = "Logic"; |
---|
746 | name = "M_vinst"; |
---|
747 | radix = "ascii"; |
---|
748 | } |
---|
749 | SIGNAL abf |
---|
750 | { |
---|
751 | format = "Logic"; |
---|
752 | name = "A_vinst"; |
---|
753 | radix = "ascii"; |
---|
754 | } |
---|
755 | SIGNAL abg |
---|
756 | { |
---|
757 | format = "Logic"; |
---|
758 | name = "W_vinst"; |
---|
759 | radix = "ascii"; |
---|
760 | } |
---|
761 | SIGNAL abh |
---|
762 | { |
---|
763 | format = "Logic"; |
---|
764 | name = "F_inst_ram_hit"; |
---|
765 | radix = "hexadecimal"; |
---|
766 | } |
---|
767 | SIGNAL abi |
---|
768 | { |
---|
769 | format = "Logic"; |
---|
770 | name = "F_issue"; |
---|
771 | radix = "hexadecimal"; |
---|
772 | } |
---|
773 | SIGNAL abj |
---|
774 | { |
---|
775 | format = "Logic"; |
---|
776 | name = "F_kill"; |
---|
777 | radix = "hexadecimal"; |
---|
778 | } |
---|
779 | SIGNAL abk |
---|
780 | { |
---|
781 | format = "Logic"; |
---|
782 | name = "D_kill"; |
---|
783 | radix = "hexadecimal"; |
---|
784 | } |
---|
785 | SIGNAL abl |
---|
786 | { |
---|
787 | format = "Logic"; |
---|
788 | name = "D_refetch"; |
---|
789 | radix = "hexadecimal"; |
---|
790 | } |
---|
791 | SIGNAL abm |
---|
792 | { |
---|
793 | format = "Logic"; |
---|
794 | name = "D_issue"; |
---|
795 | radix = "hexadecimal"; |
---|
796 | } |
---|
797 | SIGNAL abn |
---|
798 | { |
---|
799 | format = "Logic"; |
---|
800 | name = "D_valid"; |
---|
801 | radix = "hexadecimal"; |
---|
802 | } |
---|
803 | SIGNAL abo |
---|
804 | { |
---|
805 | format = "Logic"; |
---|
806 | name = "E_valid"; |
---|
807 | radix = "hexadecimal"; |
---|
808 | } |
---|
809 | SIGNAL abp |
---|
810 | { |
---|
811 | format = "Logic"; |
---|
812 | name = "M_valid"; |
---|
813 | radix = "hexadecimal"; |
---|
814 | } |
---|
815 | SIGNAL abq |
---|
816 | { |
---|
817 | format = "Logic"; |
---|
818 | name = "A_valid"; |
---|
819 | radix = "hexadecimal"; |
---|
820 | } |
---|
821 | SIGNAL abr |
---|
822 | { |
---|
823 | format = "Logic"; |
---|
824 | name = "W_valid"; |
---|
825 | radix = "hexadecimal"; |
---|
826 | } |
---|
827 | SIGNAL abs |
---|
828 | { |
---|
829 | format = "Logic"; |
---|
830 | name = "W_wr_dst_reg"; |
---|
831 | radix = "hexadecimal"; |
---|
832 | } |
---|
833 | SIGNAL abt |
---|
834 | { |
---|
835 | format = "Logic"; |
---|
836 | name = "W_dst_regnum"; |
---|
837 | radix = "hexadecimal"; |
---|
838 | } |
---|
839 | SIGNAL abu |
---|
840 | { |
---|
841 | format = "Logic"; |
---|
842 | name = "W_wr_data"; |
---|
843 | radix = "hexadecimal"; |
---|
844 | } |
---|
845 | SIGNAL abv |
---|
846 | { |
---|
847 | format = "Logic"; |
---|
848 | name = "D_en"; |
---|
849 | radix = "hexadecimal"; |
---|
850 | } |
---|
851 | SIGNAL abw |
---|
852 | { |
---|
853 | format = "Logic"; |
---|
854 | name = "E_en"; |
---|
855 | radix = "hexadecimal"; |
---|
856 | } |
---|
857 | SIGNAL abx |
---|
858 | { |
---|
859 | format = "Logic"; |
---|
860 | name = "M_en"; |
---|
861 | radix = "hexadecimal"; |
---|
862 | } |
---|
863 | SIGNAL aby |
---|
864 | { |
---|
865 | format = "Logic"; |
---|
866 | name = "A_en"; |
---|
867 | radix = "hexadecimal"; |
---|
868 | } |
---|
869 | SIGNAL abz |
---|
870 | { |
---|
871 | format = "Logic"; |
---|
872 | name = "F_iw"; |
---|
873 | radix = "hexadecimal"; |
---|
874 | } |
---|
875 | SIGNAL aca |
---|
876 | { |
---|
877 | format = "Logic"; |
---|
878 | name = "D_iw"; |
---|
879 | radix = "hexadecimal"; |
---|
880 | } |
---|
881 | SIGNAL acb |
---|
882 | { |
---|
883 | format = "Logic"; |
---|
884 | name = "E_iw"; |
---|
885 | radix = "hexadecimal"; |
---|
886 | } |
---|
887 | SIGNAL acc |
---|
888 | { |
---|
889 | format = "Logic"; |
---|
890 | name = "E_cancel"; |
---|
891 | radix = "hexadecimal"; |
---|
892 | } |
---|
893 | SIGNAL acd |
---|
894 | { |
---|
895 | format = "Logic"; |
---|
896 | name = "E_pipe_flush"; |
---|
897 | radix = "hexadecimal"; |
---|
898 | } |
---|
899 | SIGNAL ace |
---|
900 | { |
---|
901 | format = "Logic"; |
---|
902 | name = "E_pipe_flush_baddr"; |
---|
903 | radix = "hexadecimal"; |
---|
904 | } |
---|
905 | SIGNAL acf |
---|
906 | { |
---|
907 | format = "Logic"; |
---|
908 | name = "A_status_reg_pie"; |
---|
909 | radix = "hexadecimal"; |
---|
910 | } |
---|
911 | SIGNAL acg |
---|
912 | { |
---|
913 | format = "Logic"; |
---|
914 | name = "A_ienable_reg"; |
---|
915 | radix = "hexadecimal"; |
---|
916 | } |
---|
917 | SIGNAL ach |
---|
918 | { |
---|
919 | format = "Logic"; |
---|
920 | name = "intr_req"; |
---|
921 | radix = "hexadecimal"; |
---|
922 | } |
---|
923 | } |
---|
924 | } |
---|
925 | MASTER data_master2 |
---|
926 | { |
---|
927 | PORT_WIRING |
---|
928 | { |
---|
929 | } |
---|
930 | SYSTEM_BUILDER_INFO |
---|
931 | { |
---|
932 | Register_Incoming_Signals = "1"; |
---|
933 | Bus_Type = "avalon"; |
---|
934 | Data_Width = "32"; |
---|
935 | Max_Address_Width = "31"; |
---|
936 | Address_Width = "8"; |
---|
937 | Is_Data_Master = "1"; |
---|
938 | Has_IRQ = "0"; |
---|
939 | Is_Enabled = "0"; |
---|
940 | } |
---|
941 | } |
---|
942 | MASTER local_data_master_0 |
---|
943 | { |
---|
944 | PORT_WIRING |
---|
945 | { |
---|
946 | } |
---|
947 | SYSTEM_BUILDER_INFO |
---|
948 | { |
---|
949 | Register_Incoming_Signals = "0"; |
---|
950 | Bus_Type = "avalon"; |
---|
951 | Data_Width = "32"; |
---|
952 | Max_Address_Width = "31"; |
---|
953 | Address_Width = "8"; |
---|
954 | Is_Data_Master = "1"; |
---|
955 | Has_IRQ = "0"; |
---|
956 | Is_Enabled = "0"; |
---|
957 | } |
---|
958 | } |
---|
959 | MASTER local_data_master_1 |
---|
960 | { |
---|
961 | PORT_WIRING |
---|
962 | { |
---|
963 | } |
---|
964 | SYSTEM_BUILDER_INFO |
---|
965 | { |
---|
966 | Register_Incoming_Signals = "0"; |
---|
967 | Bus_Type = "avalon"; |
---|
968 | Data_Width = "32"; |
---|
969 | Max_Address_Width = "31"; |
---|
970 | Address_Width = "8"; |
---|
971 | Is_Data_Master = "1"; |
---|
972 | Has_IRQ = "0"; |
---|
973 | Is_Enabled = "0"; |
---|
974 | } |
---|
975 | } |
---|
976 | MASTER local_data_master_2 |
---|
977 | { |
---|
978 | PORT_WIRING |
---|
979 | { |
---|
980 | } |
---|
981 | SYSTEM_BUILDER_INFO |
---|
982 | { |
---|
983 | Register_Incoming_Signals = "0"; |
---|
984 | Bus_Type = "avalon"; |
---|
985 | Data_Width = "32"; |
---|
986 | Max_Address_Width = "31"; |
---|
987 | Address_Width = "8"; |
---|
988 | Is_Data_Master = "1"; |
---|
989 | Has_IRQ = "0"; |
---|
990 | Is_Enabled = "0"; |
---|
991 | } |
---|
992 | } |
---|
993 | MASTER local_data_master_3 |
---|
994 | { |
---|
995 | PORT_WIRING |
---|
996 | { |
---|
997 | } |
---|
998 | SYSTEM_BUILDER_INFO |
---|
999 | { |
---|
1000 | Register_Incoming_Signals = "0"; |
---|
1001 | Bus_Type = "avalon"; |
---|
1002 | Data_Width = "32"; |
---|
1003 | Max_Address_Width = "31"; |
---|
1004 | Address_Width = "8"; |
---|
1005 | Is_Data_Master = "1"; |
---|
1006 | Has_IRQ = "0"; |
---|
1007 | Is_Enabled = "0"; |
---|
1008 | } |
---|
1009 | } |
---|
1010 | MASTER local_instruction_master_0 |
---|
1011 | { |
---|
1012 | PORT_WIRING |
---|
1013 | { |
---|
1014 | } |
---|
1015 | SYSTEM_BUILDER_INFO |
---|
1016 | { |
---|
1017 | Register_Incoming_Signals = "0"; |
---|
1018 | Bus_Type = "avalon"; |
---|
1019 | Data_Width = "32"; |
---|
1020 | Max_Address_Width = "31"; |
---|
1021 | Address_Width = "8"; |
---|
1022 | Is_Instruction_Master = "1"; |
---|
1023 | Has_IRQ = "0"; |
---|
1024 | Is_Enabled = "0"; |
---|
1025 | } |
---|
1026 | } |
---|
1027 | MASTER custom_instruction_master |
---|
1028 | { |
---|
1029 | PORT_WIRING |
---|
1030 | { |
---|
1031 | } |
---|
1032 | SYSTEM_BUILDER_INFO |
---|
1033 | { |
---|
1034 | Bus_Type = "nios_custom_instruction"; |
---|
1035 | Data_Width = "32"; |
---|
1036 | Address_Width = "8"; |
---|
1037 | Max_Address_Width = "8"; |
---|
1038 | Base_Address = "N/A"; |
---|
1039 | Is_Visible = "0"; |
---|
1040 | Is_Custom_Instruction = "0"; |
---|
1041 | Is_Enabled = "0"; |
---|
1042 | } |
---|
1043 | } |
---|
1044 | SLAVE jtag_debug_module |
---|
1045 | { |
---|
1046 | PORT_WIRING |
---|
1047 | { |
---|
1048 | PORT jtag_debug_module_address |
---|
1049 | { |
---|
1050 | direction = "input"; |
---|
1051 | type = "address"; |
---|
1052 | width = "9"; |
---|
1053 | } |
---|
1054 | PORT jtag_debug_module_begintransfer |
---|
1055 | { |
---|
1056 | direction = "input"; |
---|
1057 | type = "begintransfer"; |
---|
1058 | width = "1"; |
---|
1059 | } |
---|
1060 | PORT jtag_debug_module_byteenable |
---|
1061 | { |
---|
1062 | direction = "input"; |
---|
1063 | type = "byteenable"; |
---|
1064 | width = "4"; |
---|
1065 | } |
---|
1066 | PORT jtag_debug_module_clk |
---|
1067 | { |
---|
1068 | direction = "input"; |
---|
1069 | type = "clk"; |
---|
1070 | width = "1"; |
---|
1071 | } |
---|
1072 | PORT jtag_debug_module_debugaccess |
---|
1073 | { |
---|
1074 | direction = "input"; |
---|
1075 | type = "debugaccess"; |
---|
1076 | width = "1"; |
---|
1077 | } |
---|
1078 | PORT jtag_debug_module_readdata |
---|
1079 | { |
---|
1080 | direction = "output"; |
---|
1081 | type = "readdata"; |
---|
1082 | width = "32"; |
---|
1083 | } |
---|
1084 | PORT jtag_debug_module_reset |
---|
1085 | { |
---|
1086 | direction = "input"; |
---|
1087 | type = "reset"; |
---|
1088 | width = "1"; |
---|
1089 | } |
---|
1090 | PORT jtag_debug_module_resetrequest |
---|
1091 | { |
---|
1092 | direction = "output"; |
---|
1093 | type = "resetrequest"; |
---|
1094 | width = "1"; |
---|
1095 | } |
---|
1096 | PORT jtag_debug_module_select |
---|
1097 | { |
---|
1098 | direction = "input"; |
---|
1099 | type = "chipselect"; |
---|
1100 | width = "1"; |
---|
1101 | } |
---|
1102 | PORT jtag_debug_module_write |
---|
1103 | { |
---|
1104 | direction = "input"; |
---|
1105 | type = "write"; |
---|
1106 | width = "1"; |
---|
1107 | } |
---|
1108 | PORT jtag_debug_module_writedata |
---|
1109 | { |
---|
1110 | direction = "input"; |
---|
1111 | type = "writedata"; |
---|
1112 | width = "32"; |
---|
1113 | } |
---|
1114 | PORT reset_n |
---|
1115 | { |
---|
1116 | direction = "input"; |
---|
1117 | type = "reset_n"; |
---|
1118 | width = "1"; |
---|
1119 | } |
---|
1120 | } |
---|
1121 | SYSTEM_BUILDER_INFO |
---|
1122 | { |
---|
1123 | Read_Wait_States = "1"; |
---|
1124 | Write_Wait_States = "1"; |
---|
1125 | Register_Incoming_Signals = "1"; |
---|
1126 | Bus_Type = "avalon"; |
---|
1127 | Data_Width = "32"; |
---|
1128 | Address_Width = "9"; |
---|
1129 | Accepts_Internal_Connections = "1"; |
---|
1130 | Requires_Internal_Connections = "instruction_master,data_master"; |
---|
1131 | Accepts_External_Connections = "0"; |
---|
1132 | Is_Enabled = "1"; |
---|
1133 | Address_Alignment = "dynamic"; |
---|
1134 | Base_Address = "0x08200800"; |
---|
1135 | Is_Memory_Device = "1"; |
---|
1136 | Is_Printable_Device = "0"; |
---|
1137 | Uses_Tri_State_Data_Bus = "0"; |
---|
1138 | Has_IRQ = "0"; |
---|
1139 | JTAG_Hub_Base_Id = "593990"; |
---|
1140 | JTAG_Hub_Instance_Id = "0"; |
---|
1141 | MASTERED_BY cpu_0/instruction_master |
---|
1142 | { |
---|
1143 | priority = "1"; |
---|
1144 | } |
---|
1145 | MASTERED_BY cpu_0/data_master |
---|
1146 | { |
---|
1147 | priority = "1"; |
---|
1148 | } |
---|
1149 | IRQ_MASTER cpu_0/data_master |
---|
1150 | { |
---|
1151 | IRQ_Number = "NC"; |
---|
1152 | } |
---|
1153 | } |
---|
1154 | } |
---|
1155 | } |
---|
1156 | MODULE onchip_memory_0 |
---|
1157 | { |
---|
1158 | class = "altera_avalon_onchip_memory2"; |
---|
1159 | class_version = "4.0"; |
---|
1160 | iss_model_name = "altera_memory"; |
---|
1161 | HDL_INFO |
---|
1162 | { |
---|
1163 | Precompiled_Simulation_Library_Files = ""; |
---|
1164 | Simulation_HDL_Files = ""; |
---|
1165 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory_1.vhd"; |
---|
1166 | Synthesis_Only_Files = ""; |
---|
1167 | } |
---|
1168 | WIZARD_SCRIPT_ARGUMENTS |
---|
1169 | { |
---|
1170 | allow_mram_sim_contents_only_file = "0"; |
---|
1171 | ram_block_type = "M-RAM"; |
---|
1172 | gui_ram_block_type = "Automatic"; |
---|
1173 | Writeable = "1"; |
---|
1174 | dual_port = "0"; |
---|
1175 | Size_Value = "8192"; |
---|
1176 | Size_Multiple = "1024"; |
---|
1177 | MAKE |
---|
1178 | { |
---|
1179 | TARGET delete_placeholder_warning |
---|
1180 | { |
---|
1181 | onchip_memory_1 |
---|
1182 | { |
---|
1183 | Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; |
---|
1184 | Is_Phony = "1"; |
---|
1185 | Target_File = "do_delete_placeholder_warning"; |
---|
1186 | } |
---|
1187 | } |
---|
1188 | TARGET hex |
---|
1189 | { |
---|
1190 | onchip_memory_1 |
---|
1191 | { |
---|
1192 | Command1 = "@echo Post-processing to create $(notdir $@)"; |
---|
1193 | Command2 = "elf2hex $(ELF) 0x00000000 0x7FF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex --create-lanes=0"; |
---|
1194 | Dependency = "$(ELF)"; |
---|
1195 | Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex"; |
---|
1196 | } |
---|
1197 | } |
---|
1198 | TARGET sim |
---|
1199 | { |
---|
1200 | onchip_memory_1 |
---|
1201 | { |
---|
1202 | Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; |
---|
1203 | Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \(Note: This does not affect the instruction set simulator.\)"; |
---|
1204 | Command3 = "touch $(SIMDIR)/dummy_file"; |
---|
1205 | Dependency = "$(ELF)"; |
---|
1206 | Target_File = "$(SIMDIR)/dummy_file"; |
---|
1207 | } |
---|
1208 | } |
---|
1209 | } |
---|
1210 | contents_info = "QUARTUS_PROJECT_DIR/onchip_memory_1.hex 1092402177 "; |
---|
1211 | } |
---|
1212 | SYSTEM_BUILDER_INFO |
---|
1213 | { |
---|
1214 | Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM"; |
---|
1215 | Instantiate_In_System_Module = "1"; |
---|
1216 | Is_Enabled = "1"; |
---|
1217 | Default_Module_Name = "onchip_memory"; |
---|
1218 | View |
---|
1219 | { |
---|
1220 | MESSAGES |
---|
1221 | { |
---|
1222 | } |
---|
1223 | Is_Collapsed = "1"; |
---|
1224 | } |
---|
1225 | } |
---|
1226 | SLAVE s1 |
---|
1227 | { |
---|
1228 | PORT_WIRING |
---|
1229 | { |
---|
1230 | PORT address |
---|
1231 | { |
---|
1232 | direction = "input"; |
---|
1233 | type = "address"; |
---|
1234 | width = "9"; |
---|
1235 | } |
---|
1236 | PORT byteenable |
---|
1237 | { |
---|
1238 | direction = "input"; |
---|
1239 | type = "byteenable"; |
---|
1240 | width = "4"; |
---|
1241 | } |
---|
1242 | PORT chipselect |
---|
1243 | { |
---|
1244 | direction = "input"; |
---|
1245 | type = "chipselect"; |
---|
1246 | width = "1"; |
---|
1247 | } |
---|
1248 | PORT clk |
---|
1249 | { |
---|
1250 | direction = "input"; |
---|
1251 | type = "clk"; |
---|
1252 | width = "1"; |
---|
1253 | } |
---|
1254 | PORT readdata |
---|
1255 | { |
---|
1256 | direction = "output"; |
---|
1257 | type = "readdata"; |
---|
1258 | width = "32"; |
---|
1259 | } |
---|
1260 | PORT write |
---|
1261 | { |
---|
1262 | direction = "input"; |
---|
1263 | type = "write"; |
---|
1264 | width = "1"; |
---|
1265 | } |
---|
1266 | PORT writedata |
---|
1267 | { |
---|
1268 | direction = "input"; |
---|
1269 | type = "writedata"; |
---|
1270 | width = "32"; |
---|
1271 | } |
---|
1272 | } |
---|
1273 | SYSTEM_BUILDER_INFO |
---|
1274 | { |
---|
1275 | Bus_Type = "avalon"; |
---|
1276 | Is_Memory_Device = "1"; |
---|
1277 | Address_Alignment = "dynamic"; |
---|
1278 | Address_Width = "21"; |
---|
1279 | Data_Width = "32"; |
---|
1280 | Has_IRQ = "0"; |
---|
1281 | Read_Wait_States = "0"; |
---|
1282 | Write_Wait_States = "0"; |
---|
1283 | Address_Span = "134217728"; |
---|
1284 | Read_Latency = "1"; |
---|
1285 | MASTERED_BY cpu_0/instruction_master |
---|
1286 | { |
---|
1287 | priority = "1"; |
---|
1288 | } |
---|
1289 | MASTERED_BY cpu_0/data_master |
---|
1290 | { |
---|
1291 | priority = "1"; |
---|
1292 | } |
---|
1293 | Base_Address = "0x00000000"; |
---|
1294 | IRQ_MASTER cpu_0/data_master |
---|
1295 | { |
---|
1296 | IRQ_Number = "NC"; |
---|
1297 | } |
---|
1298 | } |
---|
1299 | } |
---|
1300 | SLAVE s2 |
---|
1301 | { |
---|
1302 | PORT_WIRING |
---|
1303 | { |
---|
1304 | } |
---|
1305 | SYSTEM_BUILDER_INFO |
---|
1306 | { |
---|
1307 | Bus_Type = "avalon"; |
---|
1308 | Is_Memory_Device = "1"; |
---|
1309 | Address_Alignment = "dynamic"; |
---|
1310 | Address_Width = "21"; |
---|
1311 | Data_Width = "32"; |
---|
1312 | Has_IRQ = "0"; |
---|
1313 | Read_Wait_States = "0"; |
---|
1314 | Write_Wait_States = "0"; |
---|
1315 | Address_Span = "8388608"; |
---|
1316 | Read_Latency = "1"; |
---|
1317 | Is_Enabled = "0"; |
---|
1318 | } |
---|
1319 | } |
---|
1320 | SIMULATION |
---|
1321 | { |
---|
1322 | DISPLAY |
---|
1323 | { |
---|
1324 | SIGNAL a |
---|
1325 | { |
---|
1326 | name = "chipselect"; |
---|
1327 | conditional = "1"; |
---|
1328 | } |
---|
1329 | SIGNAL b |
---|
1330 | { |
---|
1331 | name = "write"; |
---|
1332 | conditional = "1"; |
---|
1333 | } |
---|
1334 | SIGNAL c |
---|
1335 | { |
---|
1336 | name = "address"; |
---|
1337 | radix = "hexadecimal"; |
---|
1338 | } |
---|
1339 | SIGNAL d |
---|
1340 | { |
---|
1341 | name = "byteenable"; |
---|
1342 | radix = "binary"; |
---|
1343 | conditional = "1"; |
---|
1344 | } |
---|
1345 | SIGNAL e |
---|
1346 | { |
---|
1347 | name = "readdata"; |
---|
1348 | radix = "hexadecimal"; |
---|
1349 | } |
---|
1350 | SIGNAL f |
---|
1351 | { |
---|
1352 | name = "writedata"; |
---|
1353 | radix = "hexadecimal"; |
---|
1354 | conditional = "1"; |
---|
1355 | } |
---|
1356 | } |
---|
1357 | } |
---|
1358 | PORT_WIRING |
---|
1359 | { |
---|
1360 | } |
---|
1361 | } |
---|
1362 | MODULE jtag_uart_0 |
---|
1363 | { |
---|
1364 | class = "altera_avalon_jtag_uart"; |
---|
1365 | class_version = "1.0"; |
---|
1366 | iss_model_name = "altera_avalon_jtag_uart"; |
---|
1367 | SLAVE avalon_jtag_slave |
---|
1368 | { |
---|
1369 | SYSTEM_BUILDER_INFO |
---|
1370 | { |
---|
1371 | Bus_Type = "avalon"; |
---|
1372 | Is_Printable_Device = "1"; |
---|
1373 | Address_Alignment = "native"; |
---|
1374 | Address_Width = "1"; |
---|
1375 | Data_Width = "32"; |
---|
1376 | Has_IRQ = "1"; |
---|
1377 | Read_Wait_States = "peripheral_controlled"; |
---|
1378 | Write_Wait_States = "peripheral_controlled"; |
---|
1379 | JTAG_Hub_Base_Id = "0x04006E"; |
---|
1380 | JTAG_Hub_Instance_Id = "0"; |
---|
1381 | MASTERED_BY cpu_0/data_master |
---|
1382 | { |
---|
1383 | priority = "1"; |
---|
1384 | } |
---|
1385 | IRQ_MASTER cpu_0/data_master |
---|
1386 | { |
---|
1387 | IRQ_Number = "2"; |
---|
1388 | } |
---|
1389 | Base_Address = "0x08000000"; |
---|
1390 | } |
---|
1391 | PORT_WIRING |
---|
1392 | { |
---|
1393 | PORT clk |
---|
1394 | { |
---|
1395 | type = "clk"; |
---|
1396 | direction = "input"; |
---|
1397 | width = "1"; |
---|
1398 | } |
---|
1399 | PORT rst_n |
---|
1400 | { |
---|
1401 | type = "reset_n"; |
---|
1402 | direction = "input"; |
---|
1403 | width = "1"; |
---|
1404 | } |
---|
1405 | PORT av_chipselect |
---|
1406 | { |
---|
1407 | type = "chipselect"; |
---|
1408 | direction = "input"; |
---|
1409 | width = "1"; |
---|
1410 | } |
---|
1411 | PORT av_address |
---|
1412 | { |
---|
1413 | type = "address"; |
---|
1414 | direction = "input"; |
---|
1415 | width = "1"; |
---|
1416 | } |
---|
1417 | PORT av_read_n |
---|
1418 | { |
---|
1419 | type = "read_n"; |
---|
1420 | direction = "input"; |
---|
1421 | width = "1"; |
---|
1422 | } |
---|
1423 | PORT av_readdata |
---|
1424 | { |
---|
1425 | type = "readdata"; |
---|
1426 | direction = "output"; |
---|
1427 | width = "32"; |
---|
1428 | } |
---|
1429 | PORT av_write_n |
---|
1430 | { |
---|
1431 | type = "write_n"; |
---|
1432 | direction = "input"; |
---|
1433 | width = "1"; |
---|
1434 | } |
---|
1435 | PORT av_writedata |
---|
1436 | { |
---|
1437 | type = "writedata"; |
---|
1438 | direction = "input"; |
---|
1439 | width = "32"; |
---|
1440 | } |
---|
1441 | PORT av_waitrequest |
---|
1442 | { |
---|
1443 | type = "waitrequest"; |
---|
1444 | direction = "output"; |
---|
1445 | width = "1"; |
---|
1446 | } |
---|
1447 | PORT av_irq |
---|
1448 | { |
---|
1449 | type = "irq"; |
---|
1450 | direction = "output"; |
---|
1451 | width = "1"; |
---|
1452 | } |
---|
1453 | PORT dataavailable |
---|
1454 | { |
---|
1455 | direction = "output"; |
---|
1456 | type = "dataavailable"; |
---|
1457 | width = "1"; |
---|
1458 | } |
---|
1459 | PORT readyfordata |
---|
1460 | { |
---|
1461 | direction = "output"; |
---|
1462 | type = "readyfordata"; |
---|
1463 | width = "1"; |
---|
1464 | } |
---|
1465 | } |
---|
1466 | } |
---|
1467 | SYSTEM_BUILDER_INFO |
---|
1468 | { |
---|
1469 | Instantiate_In_System_Module = "1"; |
---|
1470 | Is_Enabled = "1"; |
---|
1471 | Iss_Launch_Telnet = "0"; |
---|
1472 | View |
---|
1473 | { |
---|
1474 | Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8 |
---|
1475 | <br>Read Depth: 64; Read IRQ Threshold: 8"; |
---|
1476 | MESSAGES |
---|
1477 | { |
---|
1478 | } |
---|
1479 | Is_Collapsed = "1"; |
---|
1480 | } |
---|
1481 | } |
---|
1482 | WIZARD_SCRIPT_ARGUMENTS |
---|
1483 | { |
---|
1484 | write_depth = "64"; |
---|
1485 | read_depth = "64"; |
---|
1486 | write_threshold = "8"; |
---|
1487 | read_threshold = "8"; |
---|
1488 | read_char_stream = ""; |
---|
1489 | showascii = "1"; |
---|
1490 | read_le = "0"; |
---|
1491 | write_le = "0"; |
---|
1492 | } |
---|
1493 | SIMULATION |
---|
1494 | { |
---|
1495 | Fix_Me_Up = ""; |
---|
1496 | DISPLAY |
---|
1497 | { |
---|
1498 | SIGNAL av_chipselect |
---|
1499 | { |
---|
1500 | name = "av_chipselect"; |
---|
1501 | } |
---|
1502 | SIGNAL av_address |
---|
1503 | { |
---|
1504 | name = "av_address"; |
---|
1505 | radix = "hexadecimal"; |
---|
1506 | } |
---|
1507 | SIGNAL av_read_n |
---|
1508 | { |
---|
1509 | name = "av_read_n"; |
---|
1510 | } |
---|
1511 | SIGNAL av_readdata |
---|
1512 | { |
---|
1513 | name = "av_readdata"; |
---|
1514 | radix = "hexadecimal"; |
---|
1515 | } |
---|
1516 | SIGNAL av_write_n |
---|
1517 | { |
---|
1518 | name = "av_write_n"; |
---|
1519 | } |
---|
1520 | SIGNAL av_writedata |
---|
1521 | { |
---|
1522 | name = "av_writedata"; |
---|
1523 | radix = "hexadecimal"; |
---|
1524 | } |
---|
1525 | SIGNAL av_waitrequest |
---|
1526 | { |
---|
1527 | name = "av_waitrequest"; |
---|
1528 | } |
---|
1529 | SIGNAL av_irq |
---|
1530 | { |
---|
1531 | name = "av_irq"; |
---|
1532 | } |
---|
1533 | SIGNAL dataavailable |
---|
1534 | { |
---|
1535 | name = "dataavailable"; |
---|
1536 | } |
---|
1537 | SIGNAL readyfordata |
---|
1538 | { |
---|
1539 | name = "readyfordata"; |
---|
1540 | } |
---|
1541 | } |
---|
1542 | INTERACTIVE_IN drive |
---|
1543 | { |
---|
1544 | enable = "0"; |
---|
1545 | file = "_input_data_stream.dat"; |
---|
1546 | mutex = "_input_data_mutex.dat"; |
---|
1547 | log = "_in.log"; |
---|
1548 | rate = "100"; |
---|
1549 | signals = "temp,list"; |
---|
1550 | exe = "nios2-terminal"; |
---|
1551 | } |
---|
1552 | INTERACTIVE_OUT log |
---|
1553 | { |
---|
1554 | enable = "1"; |
---|
1555 | exe = "perl -- atail-f.pl"; |
---|
1556 | file = "_output_stream.dat"; |
---|
1557 | radix = "ascii"; |
---|
1558 | signals = "temp,list"; |
---|
1559 | } |
---|
1560 | } |
---|
1561 | HDL_INFO |
---|
1562 | { |
---|
1563 | Precompiled_Simulation_Library_Files = ""; |
---|
1564 | Simulation_HDL_Files = ""; |
---|
1565 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd"; |
---|
1566 | Synthesis_Only_Files = ""; |
---|
1567 | } |
---|
1568 | PORT_WIRING |
---|
1569 | { |
---|
1570 | } |
---|
1571 | } |
---|
1572 | MODULE timer_0 |
---|
1573 | { |
---|
1574 | class = "altera_avalon_timer"; |
---|
1575 | class_version = "2.1"; |
---|
1576 | iss_model_name = "altera_avalon_timer"; |
---|
1577 | SLAVE s1 |
---|
1578 | { |
---|
1579 | SYSTEM_BUILDER_INFO |
---|
1580 | { |
---|
1581 | Bus_Type = "avalon"; |
---|
1582 | Is_Printable_Device = "0"; |
---|
1583 | Address_Alignment = "native"; |
---|
1584 | Address_Width = "3"; |
---|
1585 | Data_Width = "16"; |
---|
1586 | Has_IRQ = "1"; |
---|
1587 | Read_Wait_States = "1"; |
---|
1588 | Write_Wait_States = "0"; |
---|
1589 | MASTERED_BY cpu_0/data_master |
---|
1590 | { |
---|
1591 | priority = "1"; |
---|
1592 | } |
---|
1593 | IRQ_MASTER cpu_0/data_master |
---|
1594 | { |
---|
1595 | IRQ_Number = "1"; |
---|
1596 | } |
---|
1597 | Base_Address = "0x08001000"; |
---|
1598 | } |
---|
1599 | PORT_WIRING |
---|
1600 | { |
---|
1601 | PORT address |
---|
1602 | { |
---|
1603 | direction = "input"; |
---|
1604 | type = "address"; |
---|
1605 | width = "3"; |
---|
1606 | } |
---|
1607 | PORT chipselect |
---|
1608 | { |
---|
1609 | direction = "input"; |
---|
1610 | type = "chipselect"; |
---|
1611 | width = "1"; |
---|
1612 | } |
---|
1613 | PORT clk |
---|
1614 | { |
---|
1615 | direction = "input"; |
---|
1616 | type = "clk"; |
---|
1617 | width = "1"; |
---|
1618 | } |
---|
1619 | PORT irq |
---|
1620 | { |
---|
1621 | direction = "output"; |
---|
1622 | type = "irq"; |
---|
1623 | width = "1"; |
---|
1624 | } |
---|
1625 | PORT readdata |
---|
1626 | { |
---|
1627 | direction = "output"; |
---|
1628 | type = "readdata"; |
---|
1629 | width = "16"; |
---|
1630 | } |
---|
1631 | PORT reset_n |
---|
1632 | { |
---|
1633 | direction = "input"; |
---|
1634 | type = "reset_n"; |
---|
1635 | width = "1"; |
---|
1636 | } |
---|
1637 | PORT write_n |
---|
1638 | { |
---|
1639 | direction = "input"; |
---|
1640 | type = "write_n"; |
---|
1641 | width = "1"; |
---|
1642 | } |
---|
1643 | PORT writedata |
---|
1644 | { |
---|
1645 | direction = "input"; |
---|
1646 | type = "writedata"; |
---|
1647 | width = "16"; |
---|
1648 | } |
---|
1649 | } |
---|
1650 | } |
---|
1651 | SYSTEM_BUILDER_INFO |
---|
1652 | { |
---|
1653 | Instantiate_In_System_Module = "1"; |
---|
1654 | Is_Enabled = "1"; |
---|
1655 | View |
---|
1656 | { |
---|
1657 | Settings_Summary = "Timer with 1 ms timeout period."; |
---|
1658 | MESSAGES |
---|
1659 | { |
---|
1660 | } |
---|
1661 | Is_Collapsed = "1"; |
---|
1662 | } |
---|
1663 | } |
---|
1664 | WIZARD_SCRIPT_ARGUMENTS |
---|
1665 | { |
---|
1666 | always_run = "0"; |
---|
1667 | fixed_period = "0"; |
---|
1668 | snapshot = "1"; |
---|
1669 | period = "1"; |
---|
1670 | period_units = "ms"; |
---|
1671 | reset_output = "0"; |
---|
1672 | timeout_pulse_output = "0"; |
---|
1673 | mult = "0.001"; |
---|
1674 | } |
---|
1675 | HDL_INFO |
---|
1676 | { |
---|
1677 | Simulation_HDL_Files = ""; |
---|
1678 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.vhd"; |
---|
1679 | Precompiled_Simulation_Library_Files = ""; |
---|
1680 | Synthesis_Only_Files = ""; |
---|
1681 | } |
---|
1682 | PORT_WIRING |
---|
1683 | { |
---|
1684 | } |
---|
1685 | } |
---|
1686 | MODULE timer_1 |
---|
1687 | { |
---|
1688 | class = "altera_avalon_timer"; |
---|
1689 | class_version = "2.1"; |
---|
1690 | iss_model_name = "altera_avalon_timer"; |
---|
1691 | SLAVE s1 |
---|
1692 | { |
---|
1693 | SYSTEM_BUILDER_INFO |
---|
1694 | { |
---|
1695 | Bus_Type = "avalon"; |
---|
1696 | Is_Printable_Device = "0"; |
---|
1697 | Address_Alignment = "native"; |
---|
1698 | Address_Width = "3"; |
---|
1699 | Data_Width = "16"; |
---|
1700 | Has_IRQ = "1"; |
---|
1701 | Read_Wait_States = "1"; |
---|
1702 | Write_Wait_States = "0"; |
---|
1703 | MASTERED_BY cpu_0/data_master |
---|
1704 | { |
---|
1705 | priority = "1"; |
---|
1706 | } |
---|
1707 | IRQ_MASTER cpu_0/data_master |
---|
1708 | { |
---|
1709 | IRQ_Number = "3"; |
---|
1710 | } |
---|
1711 | Base_Address = "0x08002000"; |
---|
1712 | } |
---|
1713 | PORT_WIRING |
---|
1714 | { |
---|
1715 | PORT address |
---|
1716 | { |
---|
1717 | direction = "input"; |
---|
1718 | type = "address"; |
---|
1719 | width = "3"; |
---|
1720 | } |
---|
1721 | PORT chipselect |
---|
1722 | { |
---|
1723 | direction = "input"; |
---|
1724 | type = "chipselect"; |
---|
1725 | width = "1"; |
---|
1726 | } |
---|
1727 | PORT clk |
---|
1728 | { |
---|
1729 | direction = "input"; |
---|
1730 | type = "clk"; |
---|
1731 | width = "1"; |
---|
1732 | } |
---|
1733 | PORT irq |
---|
1734 | { |
---|
1735 | direction = "output"; |
---|
1736 | type = "irq"; |
---|
1737 | width = "1"; |
---|
1738 | } |
---|
1739 | PORT readdata |
---|
1740 | { |
---|
1741 | direction = "output"; |
---|
1742 | type = "readdata"; |
---|
1743 | width = "16"; |
---|
1744 | } |
---|
1745 | PORT reset_n |
---|
1746 | { |
---|
1747 | direction = "input"; |
---|
1748 | type = "reset_n"; |
---|
1749 | width = "1"; |
---|
1750 | } |
---|
1751 | PORT write_n |
---|
1752 | { |
---|
1753 | direction = "input"; |
---|
1754 | type = "write_n"; |
---|
1755 | width = "1"; |
---|
1756 | } |
---|
1757 | PORT writedata |
---|
1758 | { |
---|
1759 | direction = "input"; |
---|
1760 | type = "writedata"; |
---|
1761 | width = "16"; |
---|
1762 | } |
---|
1763 | } |
---|
1764 | } |
---|
1765 | SYSTEM_BUILDER_INFO |
---|
1766 | { |
---|
1767 | Instantiate_In_System_Module = "1"; |
---|
1768 | Is_Enabled = "1"; |
---|
1769 | View |
---|
1770 | { |
---|
1771 | Settings_Summary = "Timer with 1 ms timeout period."; |
---|
1772 | MESSAGES |
---|
1773 | { |
---|
1774 | } |
---|
1775 | Is_Collapsed = "1"; |
---|
1776 | } |
---|
1777 | } |
---|
1778 | WIZARD_SCRIPT_ARGUMENTS |
---|
1779 | { |
---|
1780 | always_run = "0"; |
---|
1781 | fixed_period = "0"; |
---|
1782 | snapshot = "1"; |
---|
1783 | period = "1"; |
---|
1784 | period_units = "ms"; |
---|
1785 | reset_output = "0"; |
---|
1786 | timeout_pulse_output = "0"; |
---|
1787 | mult = "0.001"; |
---|
1788 | } |
---|
1789 | HDL_INFO |
---|
1790 | { |
---|
1791 | Simulation_HDL_Files = ""; |
---|
1792 | Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_1.vhd"; |
---|
1793 | Precompiled_Simulation_Library_Files = ""; |
---|
1794 | Synthesis_Only_Files = ""; |
---|
1795 | } |
---|
1796 | PORT_WIRING |
---|
1797 | { |
---|
1798 | } |
---|
1799 | } |
---|
1800 | } |
---|