source: rtems/bsps/mips/shared/irq/isr_entries.S @ b6755af

5
Last change on this file since b6755af was b6755af, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 9, 2018 at 3:45:56 PM

bsps/mips: Move libcpu content to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 *  This file contains the raw entry points for the exceptions.
3 *
4 *  COPYRIGHT (c) 1989-2000.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11
12#include <rtems/asm.h>
13#include <rtems/mips/iregdef.h>
14#include <rtems/mips/idtcpu.h>
15
16/*
17 *  MIPS ISA Level 1 entries
18 */
19
20#if __mips == 1
21
22FRAME(exc_norm_code,sp,0,ra)
23        la      k0, _ISR_Handler /* generic external int hndlr */
24        j       k0
25        nop
26ENDFRAME(exc_norm_code)
27
28FRAME(exc_dbg_code,sp,0,ra)
29        la      k0, _DBG_Handler /* debug interrupt */
30        j       k0
31        nop
32ENDFRAME(exc_dbg_code)
33
34/* XXX this is dependent on IDT/SIM and needs to be addressed */
35FRAME(exc_utlb_code,sp,0,ra)
36        la      k0, (R_VEC+((48)*8))
37        j       k0
38        nop
39ENDFRAME(exc_utlb_code)
40
41/*
42 * MIPS ISA Level 32
43 * XXX Again, reliance on SIM. Not good.??????????
44 */
45#elif __mips == 32
46FRAME(exc_tlb_code,sp,0,ra)
47        la      k0, _ISR_Handler
48        j       k0
49        nop
50ENDFRAME(exc_tlb_code)
51
52FRAME(exc_xtlb_code,sp,0,ra)
53        la      k0, _ISR_Handler
54        j       k0
55        nop
56
57ENDFRAME(exc_xtlb_code)
58
59FRAME(exc_cache_code,sp,0,ra)
60        la      k0, _ISR_Handler
61        j       k0
62        nop
63ENDFRAME(exc_cache_code)
64
65FRAME(exc_norm_code,sp,0,ra)
66        la      k0, _ISR_Handler /* generic external int hndlr */
67        j       k0
68        nop
69ENDFRAME(exc_norm_code)
70
71/*
72 * MIPS ISA Level 3
73 * XXX Again, reliance on SIM. Not good.
74 */
75#elif __mips == 3
76
77FRAME(exc_tlb_code,sp,0,ra)
78        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
79        j       k0
80        nop
81ENDFRAME(exc_tlb_code)
82
83FRAME(exc_xtlb_code,sp,0,ra)
84        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
85        j       k0
86        nop
87
88ENDFRAME(exc_xtlb_code)
89
90FRAME(exc_cache_code,sp,0,ra)
91        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
92        j       k0
93        nop
94ENDFRAME(exc_cache_code)
95
96FRAME(exc_norm_code,sp,0,ra)
97        la      k0, _ISR_Handler /* generic external int hndlr */
98        j       k0
99        nop
100ENDFRAME(exc_norm_code)
101
102#else
103
104#error "isr_entries.S: ISA support problem"
105
106#endif
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