source: rtems/bsps/mips/rbtx4938/start/start.S

Last change on this file was 508f319e, checked in by Sebastian Huber <sebastian.huber@…>, on 11/16/18 at 06:43:51

bsps/mips: Use interrupt stack for init stack

Update #3459.

  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23
24*************************************************************************
25**
26** Copyright 1991-95 Integrated Device Technology, Inc.
27**      All Rights Reserved
28**
29** idt_csu.S -- IDT stand alone startup code
30**
31**************************************************************************/
32#include <rtems/mips/iregdef.h>
33#include <rtems/mips/idtcpu.h>
34#include <rtems/asm.h>
35
36#include <bsp.h>
37
38        .extern mon_flush_cache
39
40#if 0
41        .extern _fdata,4                /* this is defined by the linker */
42        .extern _edata,4                /* this is defined by the linker */
43        .extern _idata,4                /* this is defined by the linker */
44#endif
45        .extern _fbss,4                 /* this is defined by the linker */
46        .extern end,4                   /* this is defined by the linker */
47
48        .lcomm sim_mem_cfg_struct,12
49
50        .text
51
52#define HARD_CODED_MEM_SIZE     0x1000000       /* RBTX4938 has 16 megabytes of RAM */
53#define PMON_VECTOR 0xbfc00500
54
55#define TMP_STKSIZE  1024
56
57/*
58** P_STACKSIZE is the size of the Prom Stack.
59** the prom stack grows downward
60*/
61#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
62
63/**************************************************************************
64**
65**  start - Typical standalone start up code required for R3000/R4000
66**
67**
68**      1)  Initialize the STATUS Register
69**              a) Clear parity error bit
70**              b) Set co_processor 1 usable bit ON
71**              c) Clear all IntMask Enables
72**              d) Set kernel/disabled mode
73**      2)  Initialize Cause Register
74**              a)  clear software interrupt bits
75**      3)  Determine FPU installed or not
76**              if not, clear CoProcessor 1 usable bit
77**      4)  Initialize data areas. Clear bss area.
78**      5)  MUST allocate temporary stack until memory size determined
79**          It MUST be uncached to prevent overwriting when caches are cleared
80**      6)  Install exception handlers
81**      7)  Determine memory and cache sizes
82**      8)  Establish permanent stack (cached or uncached as defined by bss)
83**      9)  Flush Instruction and Data caches
84**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
85**      11)  Execute initialization code if the IDT/c library is to be used
86**
87**      12)  Jump to user's "main()"
88**      13)  Jump to promexit
89**
90**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
91**      This is used to mark code specific to R3xxx or R4xxx processors.
92**      IDT/C 6.x defines __mips to be the ISA level for which we're
93**      generating code. This is used to make sure the stack etc. is
94**      double word aligned, when using -mips3 (default) or -mips2,
95**      when compiling with IDT/C6.x
96**
97***************************************************************************/
98
99FRAME(start,sp,0,ra)
100
101        .set    noreorder
102#if __mips_fpr == 64
103        li      v0,SR_CU1|SR_FR         /* initally clear ERL, enable FPU with 64 bit regs */
104#else
105        li      v0,SR_CU1               /* initally clear ERL, enable FPU with 32 bit regs */
106#endif
107
108        mtc0    v0,C0_SR                /* clr IntMsks/ kernel/disabled mode */
109        nop
110        mtc0    zero,C0_CAUSE           /* clear software interrupts */
111        nop
112
113        li      v0,CFG_C_NONCOHERENT    /* initialise default cache mode */
114        mtc0    v0,C0_CONFIG
115
116/*
117**      check to see if a fpu is really plugged in
118*/
119        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
120        mtc1    t3,fp0                  /* try to write them into fp0   */
121        mtc1    zero,fp1                /* try to write zero in fp      */
122        mfc1    t0,fp0
123        mfc1    t1,fp1
124        nop
125        bne     t0,t3,1f                /* branch if no match  */
126        nop
127        bne     t1,zero,1f              /* double check for positive id   */
128        nop
129        /* We have a FPU. clear fcsr */
130        ctc1    zero, fcr31
131        j       2f                      /* status register already correct  */
132        nop
1331:
134        li      v0,0x0                  /* clear ERL and disable FPA */
135
136        mtc0    v0, C0_SR               /* reset status register */
1372:
138        la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/
139
140#if 0
141                                        /* Initialize data sections from "rom" copy */
142        la      t0,_idata               /* address of initialization data (copy of data sections placed in ROM) */
143        la      t1,_fdata               /* start of initialized data section */
144        la      t2,_edata               /* end of initialized data section */
1453:
146        lw      t3,0(t0)
147        sw      t3,0(t1)
148        addiu   t1,t1,4
149        bne     t1,t2,3b
150        addiu   t0,t0,4
151#endif
152
153                                        /* clear bss before using it */
154        la      v0,_fbss                /* start of bss */
155        la      v1,end                  /* end of bss */
1564:      sw      zero,0(v0)
157        bltu    v0,v1,4b
158        add     v0,4
159
160
161/************************************************************************
162**
163**      Temporary Stack - needed to  handle stack saves until
164**                        memory size is determined and permanent stack set
165**
166**                        MUST be uncached to avoid confusion at cache
167**                             switching during memory sizing
168**
169*************************************************************************/
170        /* For MIPS 3, we need to be sure that the stack is aligned on a
171         * double word boundary.
172         */
173        andi    t0, v0, 0x7
174        beqz    t0, 11f   /* Last three bits Zero, already aligned */
175        nop
176        add     v0, 4
17711:
178
179        or      v0, K1BASE              /* switch to uncached */
180        add     v1, v0, TMP_STKSIZE     /* end of bss + length of tmp stack */
181        sub     v1, v1, (4*4)           /* overhead */
182        move    sp, v1                  /* set sp to top of stack */
1834:      sw      zero, 0(v0)
184        bltu    v0, v1, 4b              /* clear out temp stack */
185        add     v0, 4
186
187/*      jal     init_exc_vecs */                /* install exception handlers */
188/*      nop */                          /* MUST do before memory probes */
189
190                                        /* Force processor into uncached space during memory/cache probes */
191        la      v0, 5f
192        li      v1, K1BASE
193        or      v0, v1
194        j       v0
195        nop
1965:
197
198        li      a0, HARD_CODED_MEM_SIZE /* Set memory size global */
199        jal     set_memory_size
200        nop
201
202        la      a0, sim_mem_cfg_struct
203        jal     get_mem_conf            /* Make call to get mem size */
204        nop
205        la      a0, sim_mem_cfg_struct
206        lw      a0, 0(a0)               /* Get memory size from struct */
207
208        jal     config_cache            /* determine size of D & I caches */
209        nop
210
211        move    v0, a0                  /* mem_size */
212
213        /* For MIPS 3, we need to be sure that the stack (and hence v0
214         * here) is aligned on a double word boundary.
215         */
216        andi    t0, v0, 0x7
217        beqz    t0, 12f   /* Last three bits Zero, already aligned */
218        nop
219        subu    v0, 4   /* mem_size was not aligned on doubleword bdry????*/
22012:
221
222
223
224/**************************************************************************
225**
226**  Permanent Stack - now know top of memory, put permanent stack there
227**
228***************************************************************************/
229
230        la      t2, _fbss               /* cache mode as linked */
231        and     t2, 0xF0000000          /* isolate segment */
232        la      t1, 6f
233        j       t1                      /* back to original cache mode */
234        nop
2356:
236        or      v0, t2                  /* stack back to original cache mode */
237        addiu   v0,v0,-16               /* overhead */
238        move    sp, v0                  /* now replace count w top of memory */
239        move    v1, v0
240        subu    v1, P_STACKSIZE         /* clear requested stack size */
241
2427:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
243        bltu    v1,v0,7b
244        add     v1, 4
245
246
247/* Invalidate data cache*/
248        lui     t0, 0x8000              /* Set starting address */
249        addi    t1, t0, 0x2000          /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
250                                        /* D-Cache Writeback and Invalidate */
2511:      bge     t0, t1, 2f              /* if(t0>=end_addr) then exit */
252        nop
253        cache   1, 0(t0)                /* Index_Writeback_Inv_D way 0 */
254        cache   1, 1(t0)                /* Index_Writeback_Inv_D way 1 */
255        cache   1, 2(t0)                /* Index_Writeback_Inv_D way 2 */
256        cache   1, 3(t0)                /* Index_Writeback_Inv_D way 3 */
257        b       1b
258        addi    t0, t0, 32
2592:
260
261/* Invalidate instruction cache*/
262        lui     t0, 0x8000              /* Set starting address */
263        addi    t1, t0, 0x2000          /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
264                                        /* I-Cache Disable */
265        mfc0    t2, C0_CONFIG           /* get C0_Config */
266        lui     t3, 0x2                 /* C0_CONFIG#17 ICE# */
267        or      t3, t2, t3              /* set ICE# bit */
268        mtc0    t3, C0_CONFIG           /* set C_Config */
269        b       1f                      /* stop streaming */
270        nop
271                                        /* I-Cache Invalidate */
2721:      bge     t0, t1, 2f              /* if(t0>=end_addr) then exit */
273        nop
274        cache   0, 0(t0)                /* Index_Invalidate_I way 0 */
275        cache   0, 1(t0)                /* Index_Invalidate_I way 1 */
276        cache   0, 2(t0)                /* Index_Invalidate_I way 2 */
277        cache   0, 3(t0)                /* Index_Invalidate_I way 3 */
278        b       1b
279        addi    t0, t0, 32
280                                        /* I-Cache Enable */
2812:      mtc0    t2, C0_CONFIG           /* set C0_Config */
282        nop
283
284/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
285 we don't want to run out of slow flash device. */
286
287        la      t0,0x9fc00000
288        li      t1, 0x1000
289
290        move    t3, t0
291        addu    t1, t0, t1
2921:      bge     t0, t1, 2f
293        nop
294        lui     t2, 0x1fff              /* MASK */
295        ori     t2, t2, 0xf000
296        and     t2, t3, t2              /* virtual->physical */
297        srl     t2, t2, 4               /* [31:12] --> [35:8] */
298        ori     t2, t2, 0x00c4          /* Set Valid & Lock Bits */
299        mtc0    t2, C0_TAGLO            /* Load data to TagLo reg. */
300        nop
301        cache   0x08, 3(t0)             /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/
302        nop
303        cache   0x14, 3(t0)             /* 5(I)=0x14: Fill(Memory->Cache) Way3*/
304        b       1b
305        addi    t0, t0, 32
3062:      nop
307
308        .set    reorder
309
310/*
311** Clear Translation Lookaside Buffer (TLB)
312*/
313        jal     init_tlb                /* clear the tlb */
314
315/*
316** End of CPU initialization, ready to start kernel
317*/
318        move    a0,zero         /* Set command line passed to boot_card */
319        la      sp,_ISR_Stack_area_end # Use configuration defined stack
320        subu    sp,sp,32
321        jal     boot_card
322        nop
323
324/* Kernel has been shutdown, jump to the "exit" routine */
325        jal     _sys_exit
326        move    a0,v0                           # pass through the exit code
327
3281:
329        beq     zero,zero,1b
330        nop
331
332ENDFRAME(start)
333
334/*
335 * _sys_exit -- Exit from the application. Normally we cause a user trap
336 *          to return to the ROM monitor for another run. NOTE: This is
337 *          the only other routine we provide in the crt0.o object, since
338 *          it may be tied to the "_start" routine. It also allows
339 *          executables that contain a complete world to be linked with
340 *          just the crt0.o object.
341 */
342FRAME(_sys_exit,sp,0,ra)
343
344        break   1023
345        nop
34613:
347        b       13b                             # but loop back just in-case
348        nop
349
350ENDFRAME(_sys_exit)
351
352
353
354        .globl  __sizemem
355        .ent    __sizemem
356__sizemem:
357        li      v0,HARD_CODED_MEM_SIZE
358        j       ra
359        nop
360        .end    __sizemem
361
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