1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_interrupt |
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5 | * |
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6 | * @brief interrupt definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 1989-2012. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #ifndef LIBBSP_MIPS_TX4938_IRQ_H |
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19 | #define LIBBSP_MIPS_TX4938_IRQ_H |
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20 | |
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21 | #ifndef ASM |
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22 | #include <rtems.h> |
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23 | #include <rtems/irq.h> |
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24 | #include <rtems/irq-extension.h> |
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25 | #include <rtems/score/mips.h> |
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26 | #endif |
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27 | |
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28 | /** |
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29 | * @addtogroup bsp_interrupt |
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30 | * |
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31 | * @{ |
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32 | */ |
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33 | |
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34 | /* |
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35 | * Interrupt Vector Numbers |
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36 | * |
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37 | */ |
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38 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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39 | #define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0 |
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40 | #define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1 |
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41 | #define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2 |
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42 | #define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3 |
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43 | #define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4 |
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44 | #define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5 |
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45 | #define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6 |
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46 | #define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7 |
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47 | #define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8 |
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48 | #define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9 |
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49 | #define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10 |
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50 | #define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11 |
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51 | #define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12 |
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52 | #define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13 |
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53 | #define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14 |
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54 | #define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15 |
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55 | #define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16 |
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56 | #define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17 |
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57 | #define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18 |
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58 | #define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19 |
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59 | #define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20 |
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60 | #define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21 |
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61 | #define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22 |
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62 | #define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23 |
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63 | #define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24 |
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64 | #define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25 |
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65 | #define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26 |
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66 | #define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 |
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67 | #define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28 |
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68 | #define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29 |
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69 | #define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30 |
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70 | #define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31 |
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71 | |
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72 | #define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 |
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73 | #define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 |
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74 | #define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 |
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75 | |
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76 | #define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS |
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77 | |
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78 | /** @} */ |
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79 | |
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80 | #endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ |
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