1 | /* |
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2 | |
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3 | Based upon IDT provided code with the following release: |
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4 | |
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5 | This source code has been made available to you by IDT on an AS-IS |
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6 | basis. Anyone receiving this source is licensed under IDT copyrights |
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7 | to use it in any way he or she deems fit, including copying it, |
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8 | modifying it, compiling it, and redistributing it either with or |
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9 | without modifications. No license under IDT patents or patent |
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10 | applications is to be implied by the copyright license. |
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11 | |
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12 | Any user of this software should understand that IDT cannot provide |
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13 | technical support for this software and will not be responsible for |
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14 | any consequences resulting from the use of this software. |
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15 | |
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16 | Any person who transfers this source code or any derivative work must |
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17 | include the IDT copyright notice, this paragraph, and the preceeding |
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18 | two paragraphs in the transferred software. |
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19 | |
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20 | COPYRIGHT IDT CORPORATION 1996 |
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21 | LICENSED MATERIAL - PROGRAM PROPERTY OF IDT |
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22 | |
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23 | |
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24 | ************************************************************************* |
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25 | ** |
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26 | ** Copyright 1991-95 Integrated Device Technology, Inc. |
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27 | ** All Rights Reserved |
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28 | ** |
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29 | ** idt_csu.S -- IDT stand alone startup code |
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30 | ** |
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31 | **************************************************************************/ |
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32 | #include <rtems/mips/iregdef.h> |
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33 | #include <rtems/mips/idtcpu.h> |
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34 | #include <rtems/asm.h> |
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35 | |
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36 | #include <bsp.h> |
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37 | |
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38 | .extern mon_flush_cache |
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39 | |
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40 | #if 0 |
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41 | .extern _fdata,4 /* this is defined by the linker */ |
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42 | .extern _edata,4 /* this is defined by the linker */ |
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43 | .extern _idata,4 /* this is defined by the linker */ |
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44 | #endif |
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45 | .extern _fbss,4 /* this is defined by the linker */ |
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46 | .extern end,4 /* this is defined by the linker */ |
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47 | |
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48 | .lcomm sim_mem_cfg_struct,12 |
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49 | |
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50 | .text |
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51 | |
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52 | #define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4925 has 16 megabytes of RAM */ |
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53 | #define PMON_VECTOR 0xbfc00500 |
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54 | |
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55 | #define TMP_STKSIZE 1024 |
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56 | |
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57 | /* |
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58 | ** P_STACKSIZE is the size of the Prom Stack. |
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59 | ** the prom stack grows downward |
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60 | */ |
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61 | #define P_STACKSIZE 0x2000 /* sets stack size to 8k */ |
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62 | |
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63 | |
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64 | /************************************************************************** |
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65 | ** |
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66 | ** start - Typical standalone start up code required for R3000/R4000 |
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67 | ** |
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68 | ** |
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69 | ** 1) Initialize the STATUS Register |
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70 | ** a) Clear parity error bit |
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71 | ** b) Set co_processor 1 usable bit ON |
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72 | ** c) Clear all IntMask Enables |
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73 | ** d) Set kernel/disabled mode |
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74 | ** 2) Initialize Cause Register |
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75 | ** a) clear software interrupt bits |
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76 | ** 3) Determine FPU installed or not |
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77 | ** if not, clear CoProcessor 1 usable bit |
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78 | ** 4) Initialize data areas. Clear bss area. |
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79 | ** 5) MUST allocate temporary stack until memory size determined |
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80 | ** It MUST be uncached to prevent overwriting when caches are cleared |
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81 | ** 6) Install exception handlers |
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82 | ** 7) Determine memory and cache sizes |
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83 | ** 8) Establish permanent stack (cached or uncached as defined by bss) |
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84 | ** 9) Flush Instruction and Data caches |
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85 | ** 10) If there is a Translation Lookaside Buffer, Clear the TLB |
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86 | ** 11) Execute initialization code if the IDT/c library is to be used |
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87 | ** |
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88 | ** 12) Jump to user's "main()" |
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89 | ** 13) Jump to promexit |
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90 | ** |
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91 | ** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. |
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92 | ** This is used to mark code specific to R3xxx or R4xxx processors. |
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93 | ** IDT/C 6.x defines __mips to be the ISA level for which we're |
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94 | ** generating code. This is used to make sure the stack etc. is |
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95 | ** double word aligned, when using -mips3 (default) or -mips2, |
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96 | ** when compiling with IDT/C6.x |
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97 | ** |
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98 | ***************************************************************************/ |
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99 | |
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100 | FRAME(start,sp,0,ra) |
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101 | |
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102 | .set noreorder |
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103 | #if __mips_fpr == 64 |
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104 | li v0,SR_CU1|SR_FR /* initally clear ERL, enable FPU with 64 bit regs */ |
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105 | #else |
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106 | li v0,SR_CU1 /* initally clear ERL, enable FPU with 32 bit regs */ |
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107 | #endif |
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108 | |
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109 | mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ |
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110 | nop |
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111 | mtc0 zero,C0_CAUSE /* clear software interrupts */ |
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112 | nop |
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113 | |
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114 | li v0,CFG_C_NONCOHERENT /* initialise default cache mode */ |
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115 | mtc0 v0,C0_CONFIG |
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116 | |
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117 | /* |
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118 | ** check to see if a fpu is really plugged in |
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119 | */ |
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120 | li t3,0xaaaa5555 /* put a's and 5's in t3 */ |
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121 | mtc1 t3,fp0 /* try to write them into fp0 */ |
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122 | mtc1 zero,fp1 /* try to write zero in fp */ |
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123 | mfc1 t0,fp0 |
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124 | mfc1 t1,fp1 |
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125 | nop |
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126 | bne t0,t3,1f /* branch if no match */ |
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127 | nop |
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128 | bne t1,zero,1f /* double check for positive id */ |
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129 | nop |
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130 | /* We have a FPU. clear fcsr */ |
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131 | ctc1 zero, fcr31 |
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132 | j 2f /* status register already correct */ |
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133 | nop |
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134 | 1: |
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135 | li v0,0x0 /* clear ERL and disable FPA */ |
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136 | |
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137 | mtc0 v0, C0_SR /* reset status register */ |
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138 | 2: |
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139 | la gp, _gp /* Initialize gp register (pointer to "small" data)*/ |
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140 | |
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141 | #if 0 |
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142 | /* Initialize data sections from "rom" copy */ |
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143 | la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ |
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144 | la t1,_fdata /* start of initialized data section */ |
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145 | la t2,_edata /* end of initialized data section */ |
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146 | 3: |
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147 | lw t3,0(t0) |
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148 | sw t3,0(t1) |
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149 | addiu t1,t1,4 |
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150 | bne t1,t2,3b |
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151 | addiu t0,t0,4 |
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152 | #endif |
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153 | |
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154 | /* clear bss before using it */ |
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155 | la v0,_fbss /* start of bss */ |
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156 | la v1,end /* end of bss */ |
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157 | 4: sw zero,0(v0) |
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158 | bltu v0,v1,4b |
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159 | add v0,4 |
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160 | |
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161 | |
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162 | /************************************************************************ |
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163 | ** |
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164 | ** Temporary Stack - needed to handle stack saves until |
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165 | ** memory size is determined and permanent stack set |
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166 | ** |
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167 | ** MUST be uncached to avoid confusion at cache |
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168 | ** switching during memory sizing |
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169 | ** |
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170 | *************************************************************************/ |
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171 | /* For MIPS 3, we need to be sure that the stack is aligned on a |
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172 | * double word boundary. |
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173 | */ |
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174 | andi t0, v0, 0x7 |
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175 | beqz t0, 11f /* Last three bits Zero, already aligned */ |
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176 | nop |
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177 | add v0, 4 |
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178 | 11: |
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179 | |
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180 | or v0, K1BASE /* switch to uncached */ |
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181 | add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ |
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182 | sub v1, v1, (4*4) /* overhead */ |
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183 | move sp, v1 /* set sp to top of stack */ |
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184 | 4: sw zero, 0(v0) |
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185 | bltu v0, v1, 4b /* clear out temp stack */ |
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186 | add v0, 4 |
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187 | |
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188 | /* jal init_exc_vecs */ /* install exception handlers */ |
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189 | /* nop */ /* MUST do before memory probes */ |
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190 | |
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191 | /* Force processor into uncached space during memory/cache probes */ |
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192 | la v0, 5f |
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193 | li v1, K1BASE |
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194 | or v0, v1 |
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195 | j v0 |
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196 | nop |
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197 | 5: |
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198 | |
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199 | li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ |
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200 | jal set_memory_size |
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201 | nop |
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202 | |
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203 | la a0, sim_mem_cfg_struct |
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204 | jal get_mem_conf /* Make call to get mem size */ |
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205 | nop |
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206 | la a0, sim_mem_cfg_struct |
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207 | lw a0, 0(a0) /* Get memory size from struct */ |
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208 | |
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209 | jal config_cache /* determine size of D & I caches */ |
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210 | nop |
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211 | |
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212 | move v0, a0 /* mem_size */ |
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213 | |
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214 | /* For MIPS 3, we need to be sure that the stack (and hence v0 |
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215 | * here) is aligned on a double word boundary. |
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216 | */ |
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217 | andi t0, v0, 0x7 |
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218 | beqz t0, 12f /* Last three bits Zero, already aligned */ |
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219 | nop |
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220 | subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ |
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221 | 12: |
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222 | |
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223 | |
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224 | |
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225 | /************************************************************************** |
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226 | ** |
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227 | ** Permanent Stack - now know top of memory, put permanent stack there |
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228 | ** |
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229 | ***************************************************************************/ |
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230 | |
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231 | la t2, _fbss /* cache mode as linked */ |
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232 | and t2, 0xF0000000 /* isolate segment */ |
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233 | la t1, 6f |
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234 | j t1 /* back to original cache mode */ |
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235 | nop |
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236 | 6: |
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237 | or v0, t2 /* stack back to original cache mode */ |
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238 | addiu v0,v0,-16 /* overhead */ |
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239 | move sp, v0 /* now replace count w top of memory */ |
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240 | move v1, v0 |
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241 | subu v1, P_STACKSIZE /* clear requested stack size */ |
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242 | |
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243 | 7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ |
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244 | bltu v1,v0,7b |
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245 | add v1, 4 |
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246 | |
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247 | |
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248 | /* Invalidate data cache*/ |
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249 | lui t0, 0x8000 /* Set starting address */ |
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250 | addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ |
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251 | /* D-Cache Writeback and Invalidate */ |
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252 | 1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ |
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253 | nop |
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254 | cache 1, 0(t0) /* Index_Writeback_Inv_D way 0 */ |
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255 | cache 1, 1(t0) /* Index_Writeback_Inv_D way 1 */ |
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256 | cache 1, 2(t0) /* Index_Writeback_Inv_D way 2 */ |
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257 | cache 1, 3(t0) /* Index_Writeback_Inv_D way 3 */ |
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258 | b 1b |
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259 | addi t0, t0, 32 |
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260 | 2: |
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261 | |
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262 | /* Invalidate instruction cache*/ |
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263 | lui t0, 0x8000 /* Set starting address */ |
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264 | addi t1, t0, 0x2000 /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */ |
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265 | /* I-Cache Disable */ |
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266 | mfc0 t2, C0_CONFIG /* get C0_Config */ |
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267 | lui t3, 0x2 /* C0_CONFIG#17 ICE# */ |
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268 | or t3, t2, t3 /* set ICE# bit */ |
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269 | mtc0 t3, C0_CONFIG /* set C_Config */ |
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270 | b 1f /* stop streaming */ |
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271 | nop |
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272 | /* I-Cache Invalidate */ |
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273 | 1: bge t0, t1, 2f /* if(t0>=end_addr) then exit */ |
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274 | nop |
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275 | cache 0, 0(t0) /* Index_Invalidate_I way 0 */ |
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276 | cache 0, 1(t0) /* Index_Invalidate_I way 1 */ |
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277 | cache 0, 2(t0) /* Index_Invalidate_I way 2 */ |
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278 | cache 0, 3(t0) /* Index_Invalidate_I way 3 */ |
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279 | b 1b |
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280 | addi t0, t0, 32 |
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281 | /* I-Cache Enable */ |
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282 | 2: mtc0 t2, C0_CONFIG /* set C0_Config */ |
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283 | nop |
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284 | |
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285 | /* Lock first 4k of PMON into instruction cache. This includes interrupt service code which |
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286 | we don't want to run out of slow flash device. */ |
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287 | |
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288 | la t0,0x9fc00000 |
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289 | li t1, 0x1000 |
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290 | |
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291 | move t3, t0 |
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292 | addu t1, t0, t1 |
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293 | 1: bge t0, t1, 2f |
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294 | nop |
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295 | lui t2, 0x1fff /* MASK */ |
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296 | ori t2, t2, 0xf000 |
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297 | and t2, t3, t2 /* virtual->physical */ |
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298 | srl t2, t2, 4 /* [31:12] --> [35:8] */ |
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299 | ori t2, t2, 0x00c4 /* Set Valid & Lock Bits */ |
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300 | mtc0 t2, C0_TAGLO /* Load data to TagLo reg. */ |
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301 | nop |
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302 | cache 0x08, 3(t0) /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/ |
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303 | nop |
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304 | cache 0x14, 3(t0) /* 5(I)=0x14: Fill(Memory->Cache) Way3*/ |
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305 | b 1b |
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306 | addi t0, t0, 32 |
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307 | 2: nop |
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308 | |
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309 | .set reorder |
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310 | |
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311 | /* |
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312 | ** Clear Translation Lookaside Buffer (TLB) |
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313 | */ |
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314 | jal init_tlb /* clear the tlb */ |
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315 | |
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316 | /* |
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317 | ** End of CPU initialization, ready to start kernel |
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318 | */ |
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319 | move a0,zero /* Set argc passed to main */ |
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320 | jal boot_card |
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321 | nop |
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322 | |
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323 | /* Kernel has been shutdown, jump to the "exit" routine */ |
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324 | jal _sys_exit |
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325 | move a0,v0 # pass through the exit code |
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326 | |
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327 | 1: |
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328 | beq zero,zero,1b |
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329 | nop |
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330 | |
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331 | ENDFRAME(start) |
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332 | |
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333 | /* |
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334 | * _sys_exit -- Exit from the application. Normally we cause a user trap |
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335 | * to return to the ROM monitor for another run. NOTE: This is |
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336 | * the only other routine we provide in the crt0.o object, since |
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337 | * it may be tied to the "_start" routine. It also allows |
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338 | * executables that contain a complete world to be linked with |
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339 | * just the crt0.o object. |
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340 | */ |
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341 | FRAME(_sys_exit,sp,0,ra) |
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342 | |
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343 | break 1023 |
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344 | nop |
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345 | 13: |
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346 | b 13b # but loop back just in-case |
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347 | nop |
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348 | |
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349 | ENDFRAME(_sys_exit) |
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350 | |
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351 | |
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352 | |
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353 | .globl __sizemem |
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354 | .ent __sizemem |
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355 | __sizemem: |
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356 | li v0,HARD_CODED_MEM_SIZE |
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357 | j ra |
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358 | nop |
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359 | .end __sizemem |
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360 | |
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