source: rtems/bsps/mips/rbtx4925/start/start.S

Last change on this file was 508f319e, checked in by Sebastian Huber <sebastian.huber@…>, on 11/16/18 at 06:43:51

bsps/mips: Use interrupt stack for init stack

Update #3459.

  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23
24*************************************************************************
25**
26** Copyright 1991-95 Integrated Device Technology, Inc.
27**      All Rights Reserved
28**
29** idt_csu.S -- IDT stand alone startup code
30**
31**************************************************************************/
32#include <rtems/mips/iregdef.h>
33#include <rtems/mips/idtcpu.h>
34#include <rtems/asm.h>
35
36#include <bsp.h>
37
38        .extern mon_flush_cache
39
40#if 0
41        .extern _fdata,4                /* this is defined by the linker */
42        .extern _edata,4                /* this is defined by the linker */
43        .extern _idata,4                /* this is defined by the linker */
44#endif
45        .extern _fbss,4                 /* this is defined by the linker */
46        .extern end,4                   /* this is defined by the linker */
47
48        .lcomm sim_mem_cfg_struct,12
49
50        .text
51
52#define HARD_CODED_MEM_SIZE     0x1000000       /* RBTX4925 has 16 megabytes of RAM */
53#define PMON_VECTOR 0xbfc00500
54
55#define TMP_STKSIZE  1024
56
57/*
58** P_STACKSIZE is the size of the Prom Stack.
59** the prom stack grows downward
60*/
61#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
62
63
64/**************************************************************************
65**
66**  start - Typical standalone start up code required for R3000/R4000
67**
68**
69**      1)  Initialize the STATUS Register
70**              a) Clear parity error bit
71**              b) Set co_processor 1 usable bit ON
72**              c) Clear all IntMask Enables
73**              d) Set kernel/disabled mode
74**      2)  Initialize Cause Register
75**              a)  clear software interrupt bits
76**      3)  Determine FPU installed or not
77**              if not, clear CoProcessor 1 usable bit
78**      4)  Initialize data areas. Clear bss area.
79**      5)  MUST allocate temporary stack until memory size determined
80**          It MUST be uncached to prevent overwriting when caches are cleared
81**      6)  Install exception handlers
82**      7)  Determine memory and cache sizes
83**      8)  Establish permanent stack (cached or uncached as defined by bss)
84**      9)  Flush Instruction and Data caches
85**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
86**      11)  Execute initialization code if the IDT/c library is to be used
87**
88**      12)  Jump to user's "main()"
89**      13)  Jump to promexit
90**
91**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
92**      This is used to mark code specific to R3xxx or R4xxx processors.
93**      IDT/C 6.x defines __mips to be the ISA level for which we're
94**      generating code. This is used to make sure the stack etc. is
95**      double word aligned, when using -mips3 (default) or -mips2,
96**      when compiling with IDT/C6.x
97**
98***************************************************************************/
99
100FRAME(start,sp,0,ra)
101
102        .set    noreorder
103#if __mips_fpr == 64
104        li      v0,SR_CU1|SR_FR         /* initally clear ERL, enable FPU with 64 bit regs */
105#else
106        li      v0,SR_CU1               /* initally clear ERL, enable FPU with 32 bit regs */
107#endif
108
109        mtc0    v0,C0_SR                /* clr IntMsks/ kernel/disabled mode */
110        nop
111        mtc0    zero,C0_CAUSE           /* clear software interrupts */
112        nop
113
114        li      v0,CFG_C_NONCOHERENT    /* initialise default cache mode */
115        mtc0    v0,C0_CONFIG
116
117/*
118**      check to see if a fpu is really plugged in
119*/
120        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
121        mtc1    t3,fp0                  /* try to write them into fp0   */
122        mtc1    zero,fp1                /* try to write zero in fp      */
123        mfc1    t0,fp0
124        mfc1    t1,fp1
125        nop
126        bne     t0,t3,1f                /* branch if no match  */
127        nop
128        bne     t1,zero,1f              /* double check for positive id   */
129        nop
130        /* We have a FPU. clear fcsr */
131        ctc1    zero, fcr31
132        j       2f                      /* status register already correct  */
133        nop
1341:
135        li      v0,0x0                  /* clear ERL and disable FPA */
136
137        mtc0    v0, C0_SR               /* reset status register */
1382:
139        la      gp, _gp                 /* Initialize gp register (pointer to "small" data)*/
140
141#if 0
142                                        /* Initialize data sections from "rom" copy */
143        la      t0,_idata               /* address of initialization data (copy of data sections placed in ROM) */
144        la      t1,_fdata               /* start of initialized data section */
145        la      t2,_edata               /* end of initialized data section */
1463:
147        lw      t3,0(t0)
148        sw      t3,0(t1)
149        addiu   t1,t1,4
150        bne     t1,t2,3b
151        addiu   t0,t0,4
152#endif
153
154                                        /* clear bss before using it */
155        la      v0,_fbss                /* start of bss */
156        la      v1,end                  /* end of bss */
1574:      sw      zero,0(v0)
158        bltu    v0,v1,4b
159        add     v0,4
160
161
162/************************************************************************
163**
164**      Temporary Stack - needed to  handle stack saves until
165**                        memory size is determined and permanent stack set
166**
167**                        MUST be uncached to avoid confusion at cache
168**                             switching during memory sizing
169**
170*************************************************************************/
171        /* For MIPS 3, we need to be sure that the stack is aligned on a
172         * double word boundary.
173         */
174        andi    t0, v0, 0x7
175        beqz    t0, 11f   /* Last three bits Zero, already aligned */
176        nop
177        add     v0, 4
17811:
179
180        or      v0, K1BASE              /* switch to uncached */
181        add     v1, v0, TMP_STKSIZE     /* end of bss + length of tmp stack */
182        sub     v1, v1, (4*4)           /* overhead */
183        move    sp, v1                  /* set sp to top of stack */
1844:      sw      zero, 0(v0)
185        bltu    v0, v1, 4b              /* clear out temp stack */
186        add     v0, 4
187
188/*      jal     init_exc_vecs */                /* install exception handlers */
189/*      nop */                          /* MUST do before memory probes */
190
191                                        /* Force processor into uncached space during memory/cache probes */
192        la      v0, 5f
193        li      v1, K1BASE
194        or      v0, v1
195        j       v0
196        nop
1975:
198
199        li      a0, HARD_CODED_MEM_SIZE /* Set memory size global */
200        jal     set_memory_size
201        nop
202
203        la      a0, sim_mem_cfg_struct
204        jal     get_mem_conf            /* Make call to get mem size */
205        nop
206        la      a0, sim_mem_cfg_struct
207        lw      a0, 0(a0)               /* Get memory size from struct */
208
209        jal     config_cache            /* determine size of D & I caches */
210        nop
211
212        move    v0, a0                  /* mem_size */
213
214        /* For MIPS 3, we need to be sure that the stack (and hence v0
215         * here) is aligned on a double word boundary.
216         */
217        andi    t0, v0, 0x7
218        beqz    t0, 12f   /* Last three bits Zero, already aligned */
219        nop
220        subu    v0, 4   /* mem_size was not aligned on doubleword bdry????*/
22112:
222
223
224
225/**************************************************************************
226**
227**  Permanent Stack - now know top of memory, put permanent stack there
228**
229***************************************************************************/
230
231        la      t2, _fbss               /* cache mode as linked */
232        and     t2, 0xF0000000          /* isolate segment */
233        la      t1, 6f
234        j       t1                      /* back to original cache mode */
235        nop
2366:
237        or      v0, t2                  /* stack back to original cache mode */
238        addiu   v0,v0,-16               /* overhead */
239        move    sp, v0                  /* now replace count w top of memory */
240        move    v1, v0
241        subu    v1, P_STACKSIZE         /* clear requested stack size */
242
2437:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
244        bltu    v1,v0,7b
245        add     v1, 4
246
247
248/* Invalidate data cache*/
249        lui     t0, 0x8000              /* Set starting address */
250        addi    t1, t0, 0x2000          /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
251                                        /* D-Cache Writeback and Invalidate */
2521:      bge     t0, t1, 2f              /* if(t0>=end_addr) then exit */
253        nop
254        cache   1, 0(t0)                /* Index_Writeback_Inv_D way 0 */
255        cache   1, 1(t0)                /* Index_Writeback_Inv_D way 1 */
256        cache   1, 2(t0)                /* Index_Writeback_Inv_D way 2 */
257        cache   1, 3(t0)                /* Index_Writeback_Inv_D way 3 */
258        b       1b
259        addi    t0, t0, 32
2602:
261
262/* Invalidate instruction cache*/
263        lui     t0, 0x8000              /* Set starting address */
264        addi    t1, t0, 0x2000          /* Calculate end address (assume worst case of 32 KByte / 4 Way cache) */
265                                        /* I-Cache Disable */
266        mfc0    t2, C0_CONFIG           /* get C0_Config */
267        lui     t3, 0x2                 /* C0_CONFIG#17 ICE# */
268        or      t3, t2, t3              /* set ICE# bit */
269        mtc0    t3, C0_CONFIG           /* set C_Config */
270        b       1f                      /* stop streaming */
271        nop
272                                        /* I-Cache Invalidate */
2731:      bge     t0, t1, 2f              /* if(t0>=end_addr) then exit */
274        nop
275        cache   0, 0(t0)                /* Index_Invalidate_I way 0 */
276        cache   0, 1(t0)                /* Index_Invalidate_I way 1 */
277        cache   0, 2(t0)                /* Index_Invalidate_I way 2 */
278        cache   0, 3(t0)                /* Index_Invalidate_I way 3 */
279        b       1b
280        addi    t0, t0, 32
281                                        /* I-Cache Enable */
2822:      mtc0    t2, C0_CONFIG           /* set C0_Config */
283        nop
284
285/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
286 we don't want to run out of slow flash device. */
287
288        la      t0,0x9fc00000
289        li      t1, 0x1000
290
291        move    t3, t0
292        addu    t1, t0, t1
2931:      bge     t0, t1, 2f
294        nop
295        lui     t2, 0x1fff              /* MASK */
296        ori     t2, t2, 0xf000
297        and     t2, t3, t2              /* virtual->physical */
298        srl     t2, t2, 4               /* [31:12] --> [35:8] */
299        ori     t2, t2, 0x00c4          /* Set Valid & Lock Bits */
300        mtc0    t2, C0_TAGLO            /* Load data to TagLo reg. */
301        nop
302        cache   0x08, 3(t0)             /* 2(I)=0x08: Index_Store_Tag(I$) Way3*/
303        nop
304        cache   0x14, 3(t0)             /* 5(I)=0x14: Fill(Memory->Cache) Way3*/
305        b       1b
306        addi    t0, t0, 32
3072:      nop
308
309        .set    reorder
310
311/*
312** Clear Translation Lookaside Buffer (TLB)
313*/
314        jal     init_tlb                /* clear the tlb */
315
316/*
317** End of CPU initialization, ready to start kernel
318*/
319        move    a0,zero         /* Set argc passed to main */
320        la      sp,_ISR_Stack_area_end # Use configuration defined stack
321        subu    sp,sp,32
322        jal     boot_card
323        nop
324
325/* Kernel has been shutdown, jump to the "exit" routine */
326        jal     _sys_exit
327        move    a0,v0                           # pass through the exit code
328
3291:
330        beq     zero,zero,1b
331        nop
332
333ENDFRAME(start)
334
335/*
336 * _sys_exit -- Exit from the application. Normally we cause a user trap
337 *          to return to the ROM monitor for another run. NOTE: This is
338 *          the only other routine we provide in the crt0.o object, since
339 *          it may be tied to the "_start" routine. It also allows
340 *          executables that contain a complete world to be linked with
341 *          just the crt0.o object.
342 */
343FRAME(_sys_exit,sp,0,ra)
344
345        break   1023
346        nop
34713:
348        b       13b                             # but loop back just in-case
349        nop
350
351ENDFRAME(_sys_exit)
352
353
354
355        .globl  __sizemem
356        .ent    __sizemem
357__sizemem:
358        li      v0,HARD_CODED_MEM_SIZE
359        j       ra
360        nop
361        .end    __sizemem
362
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