source: rtems/bsps/mips/malta/STATUS @ 508f319e

5
Last change on this file since 508f319e was eb36d11, checked in by Sebastian Huber <sebastian.huber@…>, on 04/25/18 at 13:06:08

bsps: Move documentation, etc. files to bsps

This patch is a part of the BSP source reorganization.

Update #3285.
  • Property mode set to 100644
File size: 1.1 KB
Line 
117 Februrary 2011
2
3XXX
4
5This is a BSP for the MIPS Malta board with a 24K CPU on it.
6It has ONLY been tested on Qemu.
7
8Anything not mentioned has not been touched at all and will
9most likely not be in the first release of the BSP.
10
11Working
12=======
13+ Board initialization and shutdown
14+ tty0 working polled
15+ tty1 working polled (see note in issues)
16+ tty2 working polled (see notes in issues)
17+ Clock Tick
18
19
20Issues
21======
22+ We have small hack to Qemu so reset will exit.  This needs to be
23  fixed to follow the PC386 Qemu model where a command line argument
24  selects reset or exit on reset.
25
26+ tty2 is generating an interrupt which causes a TLB fault. We have
27  disabled the interrupt in the CPU interrupt mask for now.
28
29+ tty1 and tty2 are not showing any data on the screen.  This is
30  most likely an issue with qemu since the status bit is changing
31  as the characters are polled out. 
32
33TBD
34===
35+ Conversion to Programmable Interrupt Controller IRQ model
36  using shared infrastructure
37+ tty0 working interrupt driver
38+ tty1 working interrupt driver
39+ tty2 working interrupt driver
40+ PCI Bus Support
41+ AMD AM79C973 NIC
42+ Consider moving mips_interrupt_mask() into BSP.
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