source: rtems/bsps/mips/include/bsp/regs.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/**
2 * @file
3 * @ingroup mips_regs
4 * @brief Standard MIPS register names.
5 */
6
7/*
8 * regs.S -- standard MIPS register names.
9 *
10 * Copyright (c) 1995 Cygnus Support
11 *
12 * The authors hereby grant permission to use, copy, modify, distribute,
13 * and license this software and its documentation for any purpose, provided
14 * that existing copyright notices are retained in all copies and that this
15 * notice is included verbatim in any distributions. No written agreement,
16 * license, or royalty fee is required for any of the authorized uses.
17 * Modifications to this software may be copyrighted by their authors
18 * and need not follow the licensing terms described here, provided that
19 * the new terms are clearly indicated on the first page of each file where
20 * they apply.
21 */
22
23/**
24 * @defgroup mips_regs MIPS Registers
25 * @ingroup mips_shared
26 * @brief MIPS Registers
27 * @{
28 */
29
30/**
31 * @name Standard MIPS register names:
32 * @{
33 */
34
35#define zero    $0
36#define z0      $0
37#define v0      $2
38#define v1      $3
39#define a0      $4
40#define a1      $5
41#define a2      $6
42#define a3      $7
43#define t0      $8
44#define t1      $9
45#define t2      $10
46#define t3      $11
47#define t4      $12
48#define t5      $13
49#define t6      $14
50#define t7      $15
51#define s0      $16
52#define s1      $17
53#define s2      $18
54#define s3      $19
55#define s4      $20
56#define s5      $21
57#define s6      $22
58#define s7      $23
59#define t8      $24
60#define t9      $25
61#define k0      $26     ///< @brief kernel private register 0 */
62#define k1      $27     ///< @brief kernel private register 1 */
63#define gp      $28     ///< @brief global data pointer */
64#define sp      $29     ///< @brief stack-pointer */
65#define fp      $30     ///< @brief frame-pointer */
66#define ra      $31     ///< @brief return address */
67#define pc      $pc     ///< @brief pc, used on mips16 */
68
69#define fp0     $f0
70#define fp1     $f1
71
72/** @} */
73
74/**
75 * @name Useful memory constants:
76 * @{
77 */
78
79#define K0BASE          0x80000000
80#ifndef __mips64
81#define K1BASE          0xA0000000
82#else
83#define K1BASE          0xFFFFFFFFA0000000LL
84#endif
85
86/** @} */
87
88#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
89
90/**
91 * @name Standard Co-Processor 0 register numbers:
92 * @{
93 */
94
95#define C0_COUNT        $9              ///< @brief Count Register */
96#define C0_SR           $12             ///< @brief Status Register */
97#define C0_CAUSE        $13             ///< @brief last exception description */
98#define C0_EPC          $14             ///< @brief Exception error address */
99#define C0_CONFIG       $16             ///< @brief CPU configuration */
100
101/** @} */
102
103/**
104 * @name Standard Status Register bitmasks:
105 * @{
106 */
107
108#define SR_CU1          0x20000000      ///< @brief Mark CP1 as usable */
109#define SR_FR           0x04000000      ///< @brief Enable MIPS III FP registers */
110#define SR_BEV          0x00400000      ///< @brief Controls location of exception vectors */
111#define SR_PE           0x00100000      ///< @brief Mark soft reset (clear parity error) */
112
113#define SR_KX           0x00000080      ///< @brief Kernel extended addressing enabled */
114#define SR_SX           0x00000040      ///< @brief Supervisor extended addressing enabled */
115#define SR_UX           0x00000020      ///< @brief User extended addressing enabled */
116
117/** @} */
118
119/**
120 * @name Standard (R4000) cache operations.
121 * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
122 * @{
123 */
124
125#define CACHE_I         (0)     ///< @brief primary instruction */
126#define CACHE_D         (1)     ///< @brief primary data */
127#define CACHE_SI        (2)     ///< @brief secondary instruction */
128#define CACHE_SD        (3)     ///< @brief secondary data (or combined instruction/data) */
129
130#define INDEX_INVALIDATE                (0)     ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */
131#define INDEX_LOAD_TAG                  (1)
132#define INDEX_STORE_TAG                 (2)
133#define CREATE_DIRTY_EXCLUSIVE          (3)     ///< @brief CACHE_D and CACHE_SD only */
134#define HIT_INVALIDATE                  (4)
135#define CACHE_FILL                      (5)     ///< @brief CACHE_I only */
136#define HIT_WRITEBACK_INVALIDATE        (5)     ///< @brief CACHE_D and CACHE_SD only */
137#define HIT_WRITEBACK                   (6)     ///< @brief CACHE_I, CACHE_D and CACHE_SD only */
138#define HIT_SET_VIRTUAL                 (7)     ///< @brief CACHE_SI and CACHE_SD only */
139
140#define BUILD_CACHE_OP(o,c)             (((o) << 2) | (c))
141
142/** @} */
143
144/**
145 * @name Individual cache operations:
146 * @{
147 */
148
149#define INDEX_INVALIDATE_I              BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
150#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
151#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
152#define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
153
154#define INDEX_LOAD_TAG_I                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
155#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
156#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
157#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
158
159#define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
160#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
161#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
162#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
163
164#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
165#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
166
167#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
168#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
169#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
170#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
171
172#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
173#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
174#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
175
176#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
177#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
178#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
179
180#define HIT_SET_VIRTUAL_SI              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
181#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
182
183/** @} */
184
185/** @} */
186
187/*> EOF regs.S <*/
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