source: rtems/bsps/mips/hurricane/start/usc.S @ b361eabd

Last change on this file since b361eabd was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on 04/20/18 at 08:35:35

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*  usc.S
2 *
3 *  COPYRIGHT (c) 1989-2010.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11#include <bspopts.h>
12#include <rtems/asm.h>
13#include <rtems/mips/iregdef.h>
14#include <rtems/mips/idtcpu.h>
15#if BSP_HAS_USC320
16  #include <usc.h>
17#endif
18
19
20/***************************************************************************
21**
22**   The following code was added to support boards using V3 USC320
23**     system controller chip.
24**
25****************************************************************************/
26
27/*************************************************************
28*  init_hbt()
29*       Initialize the heartbeat timer
30*/
31FRAME(init_hbt,sp,0,ra)
32        .set noreorder
33        la      t0,SYSTEM       # Unlock USC registers
34        li      t1,0xA5
35        sb      t1,(t0)
36
37        la      t0,WD_HBI       # Initialize heatbeat and watchdog timers
38
39                                # (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
40                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
41                                # Watchdog period = 4000 * 5 = 20000 microseconds
42        li      t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
43
44                                # (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
45                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
46                                # Watchdog period = 1000 * 20 = 20000 microseconds
47        li      t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
48
49                                # (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
50                                # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
51                                # Watchdog period = 10000 * 20 = 200000 microseconds
52        li      t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14)
53
54        sw      t1,(t0)
55
56        la      t0,SYSTEM       # Lock USC registers
57        li      t1,0x60
58        sb      t1,(t0)
59
60        .set reorder
61        j       ra
62        nop
63        .set reorder
64ENDFRAME(init_hbt)
65
66/*************************************************************
67*  reset_wdt()
68*       Reset the watchdog timer
69*/
70FRAME(reset_wdt,sp,0,ra)
71        .set noreorder
72
73        la      t0,WD_HBI+2     # Load address watchdog timer reset byte
74        li      t1,WD_INIT
75        sb      t1,(t0)
76
77        .set reorder
78        j       ra
79        nop
80        .set reorder
81ENDFRAME(reset_wdt)
82
83/*************************************************************
84*  disable_wdt()
85*       Disable watchdog timer
86*/
87FRAME(disable_wdt,sp,0,ra)
88        .set noreorder
89        la      t0,WD_HBI       # Clear watchdog enable bit in control register
90        lw      t1,(t0)
91        li      t2,~WD_EN
92        and     t1,t1,t2
93        sw      t1,(t0)
94
95        .set reorder
96        j       ra
97        nop
98        .set reorder
99ENDFRAME(disable_wdt)
100
101/*************************************************************
102*  enable_hbi(ints)
103*       Enable the heartbeat interrupt
104*/
105FRAME(enable_hbi,sp,0,ra)
106        .set noreorder
107
108        la      t0,INT_CFG3     # Enable heartbeat interrupt in USC320
109        lw      t1,(t0)
110        li      t2,(HBI_MASK | MODE_TOTEM_POLE)
111        or      t1,t1,t2
112        sw      t1,(t0)
113
114        .set reorder
115        j       ra
116        nop
117        .set reorder
118ENDFRAME(enable_hbi)
119
120/*************************************************************
121*  disable_hbi(ints)
122*       Disable the heartbeat interrupt
123*/
124FRAME(disable_hbi,sp,0,ra)
125        .set noreorder
126        la      t0,INT_CFG3     # Disable heartbeat interrupt in USC320
127        lw      t1,(t0)
128        li      t2,~HBI_MASK
129        and     t1,t1,t2
130        sw      t1,(t0)
131
132        .set reorder
133        j       ra
134        nop
135        .set reorder
136ENDFRAME(disable_hbi)
137
138
139/*************************************************************
140*  enable_wdi()
141*       Enable the watchdog interrupt
142*/
143FRAME(enable_wdi,sp,0,ra)
144        .set noreorder
145
146        la      t0,INT_CFG1     # Enable watchdog interrupt in USC320
147        lw      t1,(t0)
148        li      t2,(WDI_MASK | MODE_TOTEM_POLE)
149        or      t1,t1,t2
150        sw      t1,(t0)
151
152        .set reorder
153        j       ra
154        nop
155        .set reorder
156ENDFRAME(enable_wdi)
157
158/*************************************************************
159*  disable_wdi(ints)
160*       Disable the watchdog interrupt
161*/
162FRAME(disable_wdi,sp,0,ra)
163        .set noreorder
164
165        la      t0,INT_CFG1     # Disable watchdog interrupt in USC320
166        lw      t1,(t0)
167        li      t2,~(WDI_MASK | MODE_TOTEM_POLE)
168        and     t1,t1,t2
169        sw      t1,(t0)
170
171        la      t0,INT_STAT     # Clear watchdog interrupt status bit
172        li      t1,WDI_MASK
173        sw      t1,(t0)
174
175        .set reorder
176        j       ra
177        nop
178        .set reorder
179ENDFRAME(disable_wdi)
180
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