| 1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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| 2 | |
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| 3 | /* usc.S |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1989-2010. |
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| 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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| 8 | * Redistribution and use in source and binary forms, with or without |
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| 9 | * modification, are permitted provided that the following conditions |
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| 10 | * are met: |
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| 11 | * 1. Redistributions of source code must retain the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer. |
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer in the |
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| 15 | * documentation and/or other materials provided with the distribution. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 18 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 21 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 27 | * POSSIBILITY OF SUCH DAMAGE. |
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| 28 | */ |
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| 29 | |
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| 30 | #include <bspopts.h> |
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| 31 | #include <rtems/asm.h> |
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| 32 | #include <rtems/mips/iregdef.h> |
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| 33 | #include <rtems/mips/idtcpu.h> |
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| 34 | #if BSP_HAS_USC320 |
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| 35 | #include <usc.h> |
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| 36 | #endif |
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| 37 | |
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| 38 | |
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| 39 | /*************************************************************************** |
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| 40 | ** |
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| 41 | ** The following code was added to support boards using V3 USC320 |
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| 42 | ** system controller chip. |
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| 43 | ** |
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| 44 | ****************************************************************************/ |
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| 45 | |
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| 46 | /************************************************************* |
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| 47 | * init_hbt() |
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| 48 | * Initialize the heartbeat timer |
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| 49 | */ |
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| 50 | FRAME(init_hbt,sp,0,ra) |
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| 51 | .set noreorder |
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| 52 | la t0,SYSTEM # Unlock USC registers |
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| 53 | li t1,0xA5 |
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| 54 | sb t1,(t0) |
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| 55 | |
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| 56 | la t0,WD_HBI # Initialize heatbeat and watchdog timers |
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| 57 | |
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| 58 | # (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds |
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| 59 | # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0) |
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| 60 | # Watchdog period = 4000 * 5 = 20000 microseconds |
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| 61 | li t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5) |
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| 62 | |
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| 63 | # (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds |
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| 64 | # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0) |
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| 65 | # Watchdog period = 1000 * 20 = 20000 microseconds |
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| 66 | li t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14) |
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| 67 | |
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| 68 | # (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds |
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| 69 | # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0) |
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| 70 | # Watchdog period = 10000 * 20 = 200000 microseconds |
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| 71 | li t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14) |
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| 72 | |
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| 73 | sw t1,(t0) |
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| 74 | |
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| 75 | la t0,SYSTEM # Lock USC registers |
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| 76 | li t1,0x60 |
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| 77 | sb t1,(t0) |
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| 78 | |
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| 79 | .set reorder |
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| 80 | j ra |
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| 81 | nop |
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| 82 | .set reorder |
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| 83 | ENDFRAME(init_hbt) |
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| 84 | |
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| 85 | /************************************************************* |
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| 86 | * reset_wdt() |
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| 87 | * Reset the watchdog timer |
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| 88 | */ |
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| 89 | FRAME(reset_wdt,sp,0,ra) |
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| 90 | .set noreorder |
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| 91 | |
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| 92 | la t0,WD_HBI+2 # Load address watchdog timer reset byte |
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| 93 | li t1,WD_INIT |
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| 94 | sb t1,(t0) |
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| 95 | |
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| 96 | .set reorder |
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| 97 | j ra |
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| 98 | nop |
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| 99 | .set reorder |
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| 100 | ENDFRAME(reset_wdt) |
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| 101 | |
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| 102 | /************************************************************* |
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| 103 | * disable_wdt() |
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| 104 | * Disable watchdog timer |
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| 105 | */ |
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| 106 | FRAME(disable_wdt,sp,0,ra) |
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| 107 | .set noreorder |
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| 108 | la t0,WD_HBI # Clear watchdog enable bit in control register |
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| 109 | lw t1,(t0) |
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| 110 | li t2,~WD_EN |
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| 111 | and t1,t1,t2 |
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| 112 | sw t1,(t0) |
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| 113 | |
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| 114 | .set reorder |
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| 115 | j ra |
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| 116 | nop |
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| 117 | .set reorder |
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| 118 | ENDFRAME(disable_wdt) |
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| 119 | |
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| 120 | /************************************************************* |
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| 121 | * enable_hbi(ints) |
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| 122 | * Enable the heartbeat interrupt |
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| 123 | */ |
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| 124 | FRAME(enable_hbi,sp,0,ra) |
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| 125 | .set noreorder |
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| 126 | |
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| 127 | la t0,INT_CFG3 # Enable heartbeat interrupt in USC320 |
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| 128 | lw t1,(t0) |
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| 129 | li t2,(HBI_MASK | MODE_TOTEM_POLE) |
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| 130 | or t1,t1,t2 |
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| 131 | sw t1,(t0) |
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| 132 | |
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| 133 | .set reorder |
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| 134 | j ra |
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| 135 | nop |
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| 136 | .set reorder |
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| 137 | ENDFRAME(enable_hbi) |
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| 138 | |
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| 139 | /************************************************************* |
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| 140 | * disable_hbi(ints) |
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| 141 | * Disable the heartbeat interrupt |
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| 142 | */ |
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| 143 | FRAME(disable_hbi,sp,0,ra) |
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| 144 | .set noreorder |
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| 145 | la t0,INT_CFG3 # Disable heartbeat interrupt in USC320 |
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| 146 | lw t1,(t0) |
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| 147 | li t2,~HBI_MASK |
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| 148 | and t1,t1,t2 |
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| 149 | sw t1,(t0) |
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| 150 | |
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| 151 | .set reorder |
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| 152 | j ra |
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| 153 | nop |
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| 154 | .set reorder |
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| 155 | ENDFRAME(disable_hbi) |
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| 156 | |
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| 157 | |
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| 158 | /************************************************************* |
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| 159 | * enable_wdi() |
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| 160 | * Enable the watchdog interrupt |
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| 161 | */ |
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| 162 | FRAME(enable_wdi,sp,0,ra) |
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| 163 | .set noreorder |
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| 164 | |
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| 165 | la t0,INT_CFG1 # Enable watchdog interrupt in USC320 |
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| 166 | lw t1,(t0) |
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| 167 | li t2,(WDI_MASK | MODE_TOTEM_POLE) |
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| 168 | or t1,t1,t2 |
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| 169 | sw t1,(t0) |
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| 170 | |
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| 171 | .set reorder |
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| 172 | j ra |
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| 173 | nop |
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| 174 | .set reorder |
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| 175 | ENDFRAME(enable_wdi) |
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| 176 | |
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| 177 | /************************************************************* |
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| 178 | * disable_wdi(ints) |
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| 179 | * Disable the watchdog interrupt |
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| 180 | */ |
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| 181 | FRAME(disable_wdi,sp,0,ra) |
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| 182 | .set noreorder |
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| 183 | |
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| 184 | la t0,INT_CFG1 # Disable watchdog interrupt in USC320 |
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| 185 | lw t1,(t0) |
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| 186 | li t2,~(WDI_MASK | MODE_TOTEM_POLE) |
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| 187 | and t1,t1,t2 |
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| 188 | sw t1,(t0) |
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| 189 | |
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| 190 | la t0,INT_STAT # Clear watchdog interrupt status bit |
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| 191 | li t1,WDI_MASK |
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| 192 | sw t1,(t0) |
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| 193 | |
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| 194 | .set reorder |
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| 195 | j ra |
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| 196 | nop |
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| 197 | .set reorder |
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| 198 | ENDFRAME(disable_wdi) |
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| 199 | |
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