source: rtems/bsps/mips/hurricane/start/start.S @ 508f319e

5
Last change on this file since 508f319e was 508f319e, checked in by Sebastian Huber <sebastian.huber@…>, on 11/16/18 at 06:43:51

bsps/mips: Use interrupt stack for init stack

Update #3459.

  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22*/
23
24/*************************************************************************
25**
26** Copyright 1991-95 Integrated Device Technology, Inc.
27**      All Rights Reserved
28**
29**************************************************************************/
30
31
32#include <rtems/mips/iregdef.h>
33#include <rtems/mips/idtcpu.h>
34#include <rtems/asm.h>
35
36#include <bsp.h>
37
38#if 0
39        .extern _fdata,4                /* this is defined by the linker */
40        .extern _edata,4                /* this is defined by the linker */
41        .extern _idata,4                /* this is defined by the linker */
42#endif
43        .extern _fbss,4           /* this is defined by the linker */
44        .extern end,4             /* this is defined by the linker */
45
46        .lcomm sim_mem_cfg_struct,12
47
48        .text
49
50/* For the V3 Eval board, we can safely assume that we have
51  at least 16 megabytes of RAM */
52#define HARD_CODED_MEM_SIZE 0x1000000
53
54#define TMP_STKSIZE  1024
55
56/*
57** P_STACKSIZE is the size of the Prom Stack.
58** the prom stack grows downward
59*/
60#define P_STACKSIZE     0x2000   /* sets stack size to 8k */
61
62/**************************************************************************
63**
64**  start - Typical standalone start up code required for R3000/R4000
65**
66**
67**      1)  Initialize the STATUS Register
68**              a) Clear parity error bit
69**              b) Set co_processor 1 usable bit ON
70**              c) Clear all IntMask Enables
71**              d) Set kernel/disabled mode
72**      2)  Initialize Cause Register
73**              a)  clear software interrupt bits
74**      3)  Determine FPU installed or not
75**              if not, clear CoProcessor 1 usable bit
76**      4)  Clear bss area
77**      5)  MUST allocate temporary stack until memory size determined
78**          It MUST be uncached to prevent overwriting when caches are cleared
79**      6)  Install exception handlers
80**      7)  Determine memory and cache sizes
81**      8)  Establish permanent stack (cached or uncached as defined by bss)
82**      9)  Flush Instruction and Data caches
83**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
84**      11)  Execute initialization code if the IDT/c library is to be used
85**
86**      12)  Jump to user's "main()" (boot_card() for RTEMS)
87**      13)  Jump to promexit
88**
89**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
90**      This is used to mark code specific to R3xxx or R4xxx processors.
91**      IDT/C 6.x defines __mips to be the ISA level for which we're
92**      generating code. This is used to make sure the stack etc. is
93**      double word aligned, when using -mips3 (default) or -mips2,
94**      when compiling with IDT/C6.x
95**
96***************************************************************************/
97
98FRAME(start,sp,0,ra)
99
100        .set    noreorder
101#if __mips_fpr == 64
102        li      v0,SR_CU1|SR_FR|SR_DE   /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */
103#else
104        li      v0,SR_CU1|SR_DE         /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */
105#endif
106
107        mtc0    v0,C0_SR                /* clr IntMsks/ kernel/disabled mode */
108        nop
109        mtc0    zero,C0_CAUSE           /* clear software interrupts */
110        nop
111
112        la      t0,0xBE200000           /* on Hurricane board, enable interrupt output signal from UART ch. B */
113        li      t1,0x8                  /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
114        sw      t1,0x10(t0)
115
116        li      v0,CFG_C_NONCOHERENT    # initialise default cache mode
117        mtc0    v0,C0_CONFIG
118
119/*
120**      check to see if an fpu is really plugged in
121*/
122        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
123        mtc1    t3,fp0                  /* try to write them into fp0   */
124        mtc1    zero,fp1                /* try to write zero in fp      */
125        mfc1    t0,fp0
126        mfc1    t1,fp1
127        nop
128        bne     t0,t3,1f                /* branch if no match  */
129        nop
130        bne     t1,zero,1f              /* double check for positive id   */
131        nop
132        /* We have a FPU. clear fcsr */
133        ctc1    zero, fcr31
134        j       2f                      /* status register already correct  */
135        nop
1361:
137        li      v0,SR_DE                        /* clear ERL and disable FPA */
138
139        mtc0    v0, C0_SR               /* reset status register */
1402:
141        la      gp, _gp
142
143#if 0
144                                        /* Initialize data sections from "rom" copy */
145        la      t0,_idata               /* address of initialization data (copy of data sections placed in ROM) */
146        la      t1,_fdata               /* start of initialized data section */
147        la      t2,_edata               /* end of initialized data section */
1483:
149        lw      t3,0(t0)
150        sw      t3,0(t1)
151        addiu   t1,t1,4
152        bne     t1,t2,3b
153        addiu   t0,t0,4
154#endif
155
156                                        /* clear bss before using it */
157        la      v0,_fbss                /* start of bss */
158        la      v1,end                  /* end of bss */
1594:      sw      zero,0(v0)
160        bltu    v0,v1,4b
161        add     v0,4
162
163
164/************************************************************************
165**
166**      Temporary Stack - needed to  handle stack saves until
167**                        memory size is determined and permanent stack set
168**
169**                        MUST be uncached to avoid confusion at cache
170**                             switching during memory sizing
171**
172*************************************************************************/
173        /* For MIPS 3, we need to be sure that the stack is aligned on a
174         * double word boundary.
175         */
176        andi    t0, v0, 0x7
177        beqz    t0, 11f   /* Last three bits Zero, already aligned */
178        nop
179        add     v0, 4
18011:
181
182        or      v0, K1BASE              /* switch to uncached */
183        add     v1, v0, TMP_STKSIZE     /* end of bss + length of tmp stack */
184        sub     v1, v1, (4*4)           /* overhead */
185        move    sp, v1                  /* set sp to top of stack */
1864:      sw      zero, 0(v0)
187        bltu    v0, v1, 4b              /* clear out temp stack */
188        add     v0, 4
189
190/*      jal     init_exc_vecs */                /* install exception handlers */
191/*      nop */                          /* MUST do before memory probes */
192
193                                        /* Force processor into uncached space during memory/cache probes */
194        la      v0, 5f
195        li      v1, K1BASE
196        or      v0, v1
197        j       v0
198        nop
1995:
200
201        li      a0, HARD_CODED_MEM_SIZE /* Set memory size global */
202        jal     set_memory_size
203        nop
204
205        la      a0, sim_mem_cfg_struct
206        jal     get_mem_conf            /* Make call to get mem size */
207        nop
208        la      a0, sim_mem_cfg_struct
209        lw      a0, 0(a0)               /* Get memory size from struct */
210
211        jal     config_cache            /* determine size of D & I caches */
212        nop
213
214        move    v0, a0                  /* mem_size */
215
216        /* For MIPS 3, we need to be sure that the stack (and hence v0
217         * here) is aligned on a double word boundary.
218         */
219        andi    t0, v0, 0x7
220        beqz    t0, 12f   /* Last three bits Zero, already aligned */
221        nop
222        subu    v0, 4   /* mem_size was not aligned on doubleword bdry????*/
22312:
224
225
226
227/**************************************************************************
228**
229**  Permanent Stack - now know top of memory, put permanent stack there
230**
231***************************************************************************/
232
233        la      t2, _fbss               /* cache mode as linked */
234        and     t2, 0xF0000000          /* isolate segment */
235        la      t1, 6f
236        j       t1                      /* back to original cache mode */
237        nop
2386:
239        or      v0, t2                  /* stack back to original cache mode */
240        addiu   v0,v0,-16               /* overhead */
241        move    sp, v0                  /* now replace count w top of memory */
242        move    v1, v0
243        subu    v1, P_STACKSIZE         /* clear requested stack size */
244
2457:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
246        bltu    v1,v0,7b
247        add     v1, 4
248        .set    reorder
249
250/* FIX THIS - This corrupts memory spaces */
251/*      jal     flush_cache_nowrite     */      /* flush Data & Instruction caches */
252
253/*      jal     mon_flush_cache         */
254
255/**************************************************************************
256**
257**      If this chip supports a Translation Lookaside Buffer, clear it
258**
259***************************************************************************/
260
261        .set    noreorder
262        mfc0    t1,  C0_SR              /* look at Status Register */
263        nop
264        .set    reorder
265
266        jal     init_tlb                /* clear the tlb */
267
268/* Force processor into cached instruction space for rest of initialization */
269#if 0
270        la      t0, 1f
271        li      t1, K0BASE              /* force into cached space */
272        or      t0, t1
273        j       t0
274        nop
2751:
276#endif
277
278/************************************************************************
279**
280**  Initialization required if using IDT/c or libc.a, standard C Lib
281**
282**  can SKIP if not necessary for application
283**
284************************************************************************/
2858:
286
287/* FIX THIS - Need the pmon equivalent
288        jal     idtsim_init_sbrk
289        jal     idtsim_init_file
290*/
291
292/***********************  END I/O initialization **********************/
293
294
295        move    a0,zero         /* Set command line passed to main */
296        la      sp,_ISR_Stack_area_end # Use configuration defined stack
297        subu    sp,sp,32
298        jal     boot_card
299        nop
300
301        # jump to the "exit" routine
302        jal     idtsim__exit
303        move    a0,v0                           # pass through the exit code
304
305
306        # FIX THIS - Need the pmon equivalent
307        # jal   idtsim_promexit
308
3091:
310        beq     zero,zero,1b
311        nop
312
313ENDFRAME(start)
314
315/*
316 * _sys_exit -- Exit from the application. Normally we cause a user trap
317 *          to return to the ROM monitor for another run. NOTE: This is
318 *          the only other routine we provide in the crt0.o object, since
319 *          it may be tied to the "_start" routine. It also allows
320 *          executables that contain a complete world to be linked with
321 *          just the crt0.o object.
322 */
323FRAME(_sys_exit,sp,0,ra)
324
325        break   1023
326        nop
32713:
328        b       13b                             # but loop back just in-case
329        nop
330
331ENDFRAME(_sys_exit)
332
333
334
335        .globl  __sizemem
336        .ent    __sizemem
337__sizemem:
338        li      v0,HARD_CODED_MEM_SIZE
339        j       ra
340        nop
341        .end    __sizemem
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