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network.c @ 031df391

Last change on this file since 031df391 was 031df391, checked in by Sebastian Huber <sebastian.huber@…>, on 04/23/18 at 07:53:31

bsps: Move legacy network drivers to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

Property mode set to 100644

File size: 31.1 KB

Line
1	/*
2	* RTEMS driver for MCF5282 Fast Ethernet Controller
3	*
4	* Author: W. Eric Norum <norume@aps.anl.gov>
5	*
6	* COPYRIGHT (c) 2005.
7	* On-Line Applications Research Corporation (OAR).
8	*
9	* The license and distribution terms for this file may be
10	* found in the file LICENSE in this distribution or at
11	* http://www.rtems.org/license/LICENSE.
12	*/
13
14	#define __INSIDE_RTEMS_BSD_TCPIP_STACK__
15
16	#include <bsp.h>
17	#include <stdio.h>
18	#include <errno.h>
19	#include <stdarg.h>
20	#include <string.h>
21	#include <rtems.h>
22	#include <rtems/error.h>
23	#include <rtems/rtems_bsdnet.h>
24
25	#include <sys/param.h>
26	#include <sys/mbuf.h>
27	#include <sys/socket.h>
28	#include <sys/sockio.h>
29
30	#include <net/ethernet.h>
31	#include <net/if.h>
32
33	#include <netinet/in.h>
34	#include <netinet/if_ether.h>
35
36
37	/*
38	* Number of interfaces supported by this driver
39	*/
40	#define NIFACES 1
41
42	#define FEC_INTC0_TX_VECTOR (64+23)
43	#define FEC_INTC0_RX_VECTOR (64+27)
44	#define MII_VECTOR (64+7) /* IRQ7* pin connected to external transceiver */
45	#define MII_EPPAR MCF5282_EPORT_EPPAR_EPPA7_LEVEL
46	#define MII_EPDDR MCF5282_EPORT_EPDDR_EPDD7
47	#define MII_EPIER MCF5282_EPORT_EPIER_EPIE7
48	#define MII_EPPDR MCF5282_EPORT_EPPDR_EPPD7
49
50	/*
51	* Default number of buffer descriptors set aside for this driver.
52	* The number of transmit buffer descriptors has to be quite large
53	* since a single frame often uses three or more buffer descriptors.
54	*/
55	#define RX_BUF_COUNT 32
56	#define TX_BUF_COUNT 20
57	#define TX_BD_PER_BUF 3
58
59	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
60
61	/*
62	* RTEMS event used by interrupt handler to signal daemons.
63	* This must not be the same event used by the TCP/IP task synchronization.
64	*/
65	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
66	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
67
68	/*
69	* RTEMS event used to start transmit daemon.
70	* This must not be the same as INTERRUPT_EVENT.
71	*/
72	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
73
74	/*
75	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
76	* Round off to nearest multiple of RBUF_ALIGN.
77	*/
78	#define MAX_MTU_SIZE 1518
79	#define RBUF_ALIGN 4
80	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
81
82	#if (MCLBYTES < RBUF_SIZE)
83	#error "Driver must have MCLBYTES > RBUF_SIZE"
84	#endif
85
86	/*
87	* Per-device data
88	*/
89	struct mcf5282_enet_struct {
90	struct arpcom arpcom;
91	struct mbuf **rxMbuf;
92	struct mbuf **txMbuf;
93	int acceptBroadcast;
94	int rxBdCount;
95	int txBdCount;
96	int txBdHead;
97	int txBdTail;
98	int txBdActiveCount;
99	mcf5282BufferDescriptor_t *rxBdBase;
100	mcf5282BufferDescriptor_t *txBdBase;
101	rtems_id rxDaemonTid;
102	rtems_id txDaemonTid;
103
104	/*
105	* Statistics
106	*/
107	unsigned long rxInterrupts;
108	unsigned long txInterrupts;
109	unsigned long miiInterrupts;
110	unsigned long txRawWait;
111	unsigned long txRealign;
112	unsigned long txRealignDrop;
113
114	/*
115	* Link parameters
116	*/
117	enum { link_auto, link_100Full, link_10Half } link;
118	uint16_t mii_cr;
119	uint16_t mii_sr2;
120	};
121	static struct mcf5282_enet_struct enet_driver[NIFACES];
122
123	/*
124	* Read MII register
125	* Busy-waits, but transfer time should be short!
126	*/
127	static int
128	getMII(int phyNumber, int regNumber)
129	{
130	MCF5282_FEC_MMFR = (0x1 << 30) \|
131	(0x2 << 28) \|
132	(phyNumber << 23) \|
133	(regNumber << 18) \|
134	(0x2 << 16);
135	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
136	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
137	return MCF5282_FEC_MMFR & 0xFFFF;
138	}
139
140	/*
141	* Write MII register
142	* Busy-waits, but transfer time should be short!
143	*/
144	static void
145	setMII(int phyNumber, int regNumber, int value)
146	{
147	MCF5282_FEC_MMFR = (0x1 << 30) \|
148	(0x1 << 28) \|
149	(phyNumber << 23) \|
150	(regNumber << 18) \|
151	(0x2 << 16) \|
152	(value & 0xFFFF);
153	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
154	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
155	}
156
157	static rtems_isr
158	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
159	{
160	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
161	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
162	enet_driver[0].rxInterrupts++;
163	rtems_bsdnet_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
164	}
165
166	static rtems_isr
167	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
168	{
169	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
170	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
171	enet_driver[0].txInterrupts++;
172	rtems_bsdnet_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
173	}
174
175	static rtems_isr
176	mcf5282_mii_interrupt_handler( rtems_vector_number v )
177	{
178	uint16 sr2;
179
180	enet_driver[0].miiInterrupts++;
181	getMII(1, 19); /* Read and clear interrupt status bits */
182	enet_driver[0].mii_sr2 = sr2 = getMII(1, 17);
183	if (((sr2 & 0x200) != 0)
184	&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) == 0))
185	MCF5282_FEC_TCR \|= MCF5282_FEC_TCR_FDEN;
186	else if (((sr2 & 0x200) == 0)
187	&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) != 0))
188	MCF5282_FEC_TCR &= ~MCF5282_FEC_TCR_FDEN;
189	}
190
191	/*
192	* Allocate buffer descriptors from (non-cached) on-chip static RAM
193	* Ensure 128-bit (16-byte) alignment
194	* Allow some space at the beginning for other diagnostic counters
195	*/
196	static mcf5282BufferDescriptor_t *
197	mcf5282_bd_allocate(unsigned int count)
198	{
199	static mcf5282BufferDescriptor_t *bdp = __SRAMBASE.fec_descriptors;
200	mcf5282BufferDescriptor_t *p = bdp;
201
202	bdp += count;
203	if ((int)bdp & 0xF)
204	bdp = (mcf5282BufferDescriptor_t )((char )bdp + (16 - ((int)bdp & 0xF)));
205	return p;
206	}
207
208	static void
209	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
210	{
211	int i;
212	const unsigned char *hwaddr;
213	rtems_status_code status;
214	rtems_isr_entry old_handler;
215	uint32_t clock_speed = bsp_get_CPU_clock_speed();
216
217	/*
218	* Issue reset to FEC
219	*/
220	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
221	rtems_task_wake_after(2);
222	MCF5282_FEC_ECR = 0;
223
224	/*
225	* Configuration of I/O ports is done outside of this function
226	*/
227	#if 0
228	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
229	#endif
230
231	/*
232	* Set our physical address
233	*/
234	hwaddr = sc->arpcom.ac_enaddr;
235	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
236	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
237	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
238
239
240	/*
241	* Clear the hash table
242	*/
243	MCF5282_FEC_GAUR = 0;
244	MCF5282_FEC_GALR = 0;
245
246	/*
247	* Set up receive buffer size
248	*/
249	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
250
251	/*
252	* Allocate mbuf pointers
253	*/
254	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
255	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
256	if (!sc->rxMbuf \|\| !sc->txMbuf)
257	rtems_panic("No memory for mbuf pointers");
258
259	/*
260	* Set receiver and transmitter buffer descriptor bases
261	*/
262	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
263	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
264	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
265	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
266
267	/*
268	* Set up Receive Control Register:
269	* Not promiscuous
270	* MII mode
271	* Full duplex
272	* No loopback
273	*/
274	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
275	MCF5282_FEC_RCR_MII_MODE;
276
277	/*
278	* Set up Transmit Control Register:
279	* Full or half duplex
280	* No heartbeat
281	*/
282	if (sc->link == link_10Half)
283	MCF5282_FEC_TCR = 0;
284	else
285	MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
286
287	/*
288	* Initialize statistic counters
289	*/
290	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
291	{
292	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
293	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
294	*vuip++ = 0;
295	}
296	MCF5282_FEC_MIBC = 0;
297
298	/*
299	* Set MII speed to <= 2.5 MHz
300	*/
301	i = (clock_speed + 5000000 - 1) / 5000000;
302	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
303
304	/*
305	* Set PHYS
306	* LED1 receive status, LED2 link status, LEDs stretched
307	* Advertise 100 Mb/s, full-duplex, IEEE-802.3
308	* Turn off auto-negotiate
309	* Clear status
310	*/
311	setMII(1, 20, 0x24F2);
312	setMII(1, 4, 0x0181);
313	setMII(1, 0, 0x0);
314	rtems_task_wake_after(2);
315	sc->mii_sr2 = getMII(1, 17);
316	switch (sc->link) {
317	case link_auto:
318	/*
319	* Enable speed-change, duplex-change and link-status-change interrupts
320	* Enable auto-negotiate (start at 100/FULL)
321	*/
322	setMII(1, 18, 0x0072);
323	setMII(1, 0, 0x3100);
324	break;
325
326	case link_10Half:
327	/*
328	* Force 10/HALF
329	*/
330	setMII(1, 0, 0x0);
331	break;
332
333	case link_100Full:
334	/*
335	* Force 100/FULL
336	*/
337	setMII(1, 0, 0x2100);
338	break;
339	}
340	sc->mii_cr = getMII(1, 0);
341
342	/*
343	* Set up receive buffer descriptors
344	*/
345	for (i = 0 ; i < sc->rxBdCount ; i++)
346	(sc->rxBdBase + i)->status = 0;
347
348	/*
349	* Set up transmit buffer descriptors
350	*/
351	for (i = 0 ; i < sc->txBdCount ; i++) {
352	sc->txBdBase[i].status = 0;
353	sc->txMbuf[i] = NULL;
354	}
355	sc->txBdHead = sc->txBdTail = 0;
356	sc->txBdActiveCount = 0;
357
358	/*
359	* Set up interrupts
360	*/
361	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
362	if (status != RTEMS_SUCCESSFUL)
363	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
364	rtems_status_text(status));
365	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY);
366	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
367	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
368	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
369
370	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
371	if (status != RTEMS_SUCCESSFUL)
372	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
373	rtems_status_text(status));
374	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY);
375	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
376	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
377	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
378
379	status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
380	if (status != RTEMS_SUCCESSFUL)
381	rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
382	rtems_status_text(status));
383	MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
384	MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
385	MCF5282_EPORT_EPIER \|= MII_EPIER;
386	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 \| MCF5282_INTC_IMRL_MASKALL);
387	}
388
389	/*
390	* Soak up buffer descriptors that have been sent.
391	*/
392	static void
393	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
394	{
395	struct mbuf m, n;
396	uint16_t status;
397
398	while ((sc->txBdActiveCount != 0)
399	&& (((status = sc->txBdBase[sc->txBdTail].status) & MCF5282_FEC_TxBD_R) == 0)) {
400	if ((status & MCF5282_FEC_TxBD_TO1) == 0) {
401	m = sc->txMbuf[sc->txBdTail];
402	MFREE(m, n);
403	}
404	if (++sc->txBdTail == sc->txBdCount)
405	sc->txBdTail = 0;
406	sc->txBdActiveCount--;
407	}
408	}
409
410	static void
411	fec_rxDaemon (void *arg)
412	{
413	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
414	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
415	struct mbuf *m;
416	uint16_t status;
417	volatile mcf5282BufferDescriptor_t *rxBd;
418	int rxBdIndex;
419
420	/*
421	* Allocate space for incoming packets and start reception
422	*/
423	for (rxBdIndex = 0 ; ;) {
424	rxBd = sc->rxBdBase + rxBdIndex;
425	MGETHDR(m, M_WAIT, MT_DATA);
426	MCLGET(m, M_WAIT);
427	m->m_pkthdr.rcvif = ifp;
428	sc->rxMbuf[rxBdIndex] = m;
429	rxBd->buffer = mtod(m, void *);
430	rxBd->status = MCF5282_FEC_RxBD_E;
431	if (++rxBdIndex == sc->rxBdCount) {
432	rxBd->status \|= MCF5282_FEC_RxBD_W;
433	break;
434	}
435	}
436
437	/*
438	* Input packet handling loop
439	*/
440	MCF5282_FEC_RDAR = 0;
441
442	rxBdIndex = 0;
443	for (;;) {
444	rxBd = sc->rxBdBase + rxBdIndex;
445
446	/*
447	* Wait for packet if there's not one ready
448	*/
449	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
450	/*
451	* Clear old events.
452	*/
453	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
454
455	/*
456	* Wait for packet to arrive.
457	* Check the buffer descriptor before waiting for the event.
458	* This catches the case when a packet arrives between the
459	* `if' above, and the clearing of the RXF bit in the EIR.
460	*/
461	while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
462	rtems_event_set events;
463	int level;
464
465	rtems_interrupt_disable(level);
466	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
467	rtems_interrupt_enable(level);
468	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
469	RTEMS_WAIT\|RTEMS_EVENT_ANY,
470	RTEMS_NO_TIMEOUT,
471	&events);
472	}
473	}
474
475	/*
476	* Check that packet is valid
477	*/
478	if (status & MCF5282_FEC_RxBD_L) {
479	/*
480	* Pass the packet up the chain.
481	* FIXME: Packet filtering hook could be done here.
482	*/
483	struct ether_header *eh;
484	int len = rxBd->length - sizeof(uint32_t);
485
486	m = sc->rxMbuf[rxBdIndex];
487	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
488	/*
489	* Invalidate the cache. The cache is so small that it's
490	* reasonable to simply invalidate the whole thing.
491	*/
492	rtems_cache_invalidate_entire_data();
493	#endif
494	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
495	eh = mtod(m, struct ether_header *);
496	m->m_data += sizeof(struct ether_header);
497	ether_input(ifp, eh, m);
498
499	/*
500	* Allocate a new mbuf
501	*/
502	MGETHDR(m, M_WAIT, MT_DATA);
503	MCLGET(m, M_WAIT);
504	m->m_pkthdr.rcvif = ifp;
505	sc->rxMbuf[rxBdIndex] = m;
506	rxBd->buffer = mtod(m, void *);
507	}
508
509	/*
510	* Reenable the buffer descriptor
511	*/
512	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
513	MCF5282_FEC_RDAR = 0;
514
515	/*
516	* Move to next buffer descriptor
517	*/
518	if (++rxBdIndex == sc->rxBdCount)
519	rxBdIndex = 0;
520	}
521	}
522
523	static void
524	fec_sendpacket(struct ifnet ifp, struct mbuf m)
525	{
526	struct mcf5282_enet_struct *sc = ifp->if_softc;
527	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
528	uint16_t status;
529	int nAdded;
530
531	/*
532	* Free up buffer descriptors
533	*/
534	fec_retire_tx_bd(sc);
535
536	/*
537	* Set up the transmit buffer descriptors.
538	* No need to pad out short packets since the
539	* hardware takes care of that automatically.
540	* No need to copy the packet to a contiguous buffer
541	* since the hardware is capable of scatter/gather DMA.
542	*/
543	nAdded = 0;
544	firstTxBd = sc->txBdBase + sc->txBdHead;
545
546	while (m != NULL) {
547	/*
548	* Wait for buffer descriptor to become available
549	*/
550	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
551	/*
552	* Clear old events.
553	*/
554	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
555
556	/*
557	* Wait for buffer descriptor to become available.
558	* Check for buffer descriptors before waiting for the event.
559	* This catches the case when a buffer became available between
560	* the `if' above, and the clearing of the TXF bit in the EIR.
561	*/
562	fec_retire_tx_bd(sc);
563	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
564	rtems_event_set events;
565	int level;
566
567	rtems_interrupt_disable(level);
568	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
569	rtems_interrupt_enable(level);
570	sc->txRawWait++;
571	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
572	RTEMS_WAIT\|RTEMS_EVENT_ANY,
573	RTEMS_NO_TIMEOUT,
574	&events);
575	fec_retire_tx_bd(sc);
576	}
577	}
578
579	/*
580	* Don't set the READY flag on the first fragment
581	* until the whole packet has been readied.
582	*/
583	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
584
585	/*
586	* The IP fragmentation routine in ip_output
587	* can produce fragments with zero length.
588	*/
589	txBd = sc->txBdBase + sc->txBdHead;
590	if (m->m_len) {
591	char p = mtod(m, char );
592	int offset = (int)p & 0x3;
593	if (offset == 0) {
594	txBd->buffer = p;
595	txBd->length = m->m_len;
596	sc->txMbuf[sc->txBdHead] = m;
597	m = m->m_next;
598	}
599	else {
600	/*
601	* Stupid FEC can't handle misaligned data!
602	* Move offending bytes to a local buffer.
603	* Use buffer descriptor TO1 bit to indicate this.
604	*/
605	int nmove = 4 - offset;
606	char d = (char )&sc->txMbuf[sc->txBdHead];
607	status \|= MCF5282_FEC_TxBD_TO1;
608	sc->txRealign++;
609	if (nmove > m->m_len)
610	nmove = m->m_len;
611	m->m_data += nmove;
612	m->m_len -= nmove;
613	txBd->buffer = d;
614	txBd->length = nmove;
615	while (nmove--)
616	d++ = p++;
617	if (m->m_len == 0) {
618	struct mbuf *n;
619	sc->txRealignDrop++;
620	MFREE(m, n);
621	m = n;
622	}
623	}
624	nAdded++;
625	if (++sc->txBdHead == sc->txBdCount) {
626	status \|= MCF5282_FEC_TxBD_W;
627	sc->txBdHead = 0;
628	}
629	txBd->status = status;
630	}
631	else {
632	/*
633	* Toss empty mbufs.
634	*/
635	struct mbuf *n;
636	MFREE(m, n);
637	m = n;
638	}
639	}
640	if (nAdded) {
641	txBd->status = status \| MCF5282_FEC_TxBD_R
642	\| MCF5282_FEC_TxBD_L
643	\| MCF5282_FEC_TxBD_TC;
644	if (nAdded > 1)
645	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
646	MCF5282_FEC_TDAR = 0;
647	sc->txBdActiveCount += nAdded;
648	}
649	}
650
651	void
652	fec_txDaemon(void *arg)
653	{
654	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
655	struct ifnet *ifp = &sc->arpcom.ac_if;
656	struct mbuf *m;
657	rtems_event_set events;
658
659	for (;;) {
660	/*
661	* Wait for packet
662	*/
663	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
664	RTEMS_EVENT_ANY \| RTEMS_WAIT,
665	RTEMS_NO_TIMEOUT,
666	&events);
667
668	/*
669	* Send packets till queue is empty
670	*/
671	for (;;) {
672	/*
673	* Get the next mbuf chain to transmit.
674	*/
675	IF_DEQUEUE(&ifp->if_snd, m);
676	if (!m)
677	break;
678	fec_sendpacket(ifp, m);
679	}
680	ifp->if_flags &= ~IFF_OACTIVE;
681	}
682	}
683
684
685	/*
686	* Send packet (caller provides header).
687	*/
688	static void
689	mcf5282_enet_start(struct ifnet *ifp)
690	{
691	struct mcf5282_enet_struct *sc = ifp->if_softc;
692
693	rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
694	ifp->if_flags \|= IFF_OACTIVE;
695	}
696
697	static void
698	fec_init(void *arg)
699	{
700	struct mcf5282_enet_struct *sc = arg;
701	struct ifnet *ifp = &sc->arpcom.ac_if;
702
703	if (sc->txDaemonTid == 0) {
704	/*
705	* Set up hardware
706	*/
707	mcf5282_fec_initialize_hardware(sc);
708
709	/*
710	* Start driver tasks
711	*/
712	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
713	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
714	}
715
716	/*
717	* Set flags appropriately
718	*/
719	if (ifp->if_flags & IFF_PROMISC)
720	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
721	else
722	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
723
724	/*
725	* Tell the world that we're running.
726	*/
727	ifp->if_flags \|= IFF_RUNNING;
728
729	/*
730	* Enable receiver and transmitter
731	*/
732	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
733	}
734
735
736	static void
737	fec_stop(struct mcf5282_enet_struct *sc)
738	{
739	struct ifnet *ifp = &sc->arpcom.ac_if;
740
741	ifp->if_flags &= ~IFF_RUNNING;
742
743	/*
744	* Shut down receiver and transmitter
745	*/
746	MCF5282_FEC_ECR = 0x0;
747	}
748
749	/*
750	* Show interface statistics
751	*/
752	static void
753	enet_stats(struct mcf5282_enet_struct *sc)
754	{
755	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
756	printf("Rx Packet Count:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_PACKETS);
757	printf(" Rx Broadcast:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_BC_PKT);
758	printf(" Rx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_MC_PKT);
759	printf("CRC/Align error:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_CRC_ALIGN);
760	printf(" Rx Undersize:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_UNDERSIZE);
761	printf(" Rx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OVERSIZE);
762	printf(" Rx Fragment:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_FRAG);
763	printf(" Rx Jabber:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_JAB);
764	printf(" Rx 64:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P64);
765	printf(" Rx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P65T0127);
766	printf(" Rx 128-255:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P128TO255);
767	printf(" Rx 256-511:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P256TO511);
768	printf(" Rx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P512TO1023);
769	printf(" Rx 1024-2047:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P1024TO2047);
770	printf(" Rx >=2048:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_GTE2048);
771	printf(" Rx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OCTETS);
772	printf(" Rx Dropped:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_DROP);
773	printf(" Rx frame OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FRAME_OK);
774	printf(" Rx CRC error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_CRC);
775	printf(" Rx Align error:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_ALIGN);
776	printf(" FIFO Overflow:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_MACERR);
777	printf("Rx Pause Frames:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FDXFC);
778	printf(" Rx Octets OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_OCTETS_OK);
779	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
780	printf("Tx Output Waits:%-10lu", sc->txRawWait);
781	printf("Tx mbuf realign:%-10lu\n", sc->txRealign);
782	printf("Tx realign drop:%-10lu", sc->txRealignDrop);
783	printf(" Tx Unaccounted:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_DROP);
784	printf("Tx Packet Count:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_PACKETS);
785	printf(" Tx Broadcast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_BC_PKT);
786	printf(" Tx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_MC_PKT);
787	printf("CRC/Align error:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_CRC_ALIGN);
788	printf(" Tx Undersize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_UNDERSIZE);
789	printf(" Tx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OVERSIZE);
790	printf(" Tx Fragment:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_FRAG);
791	printf(" Tx Jabber:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_JAB);
792	printf(" Tx Collisions:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_COL);
793	printf(" Tx 64:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P64);
794	printf(" Tx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P65TO127);
795	printf(" Tx 128-255:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P128TO255);
796	printf(" Tx 256-511:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P256TO511);
797	printf(" Tx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P512TO1023);
798	printf(" Tx 1024-2047:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P1024TO2047);
799	printf(" Tx >=2048:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P_GTE2048);
800	printf(" Tx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OCTETS);
801	printf(" Tx Dropped:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_DROP);
802	printf(" Tx Frame OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FRAME_OK);
803	printf(" Tx 1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_1COL);
804	printf("Tx >1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_MCOL);
805	printf(" Tx Deferred:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_DEF);
806	printf(" Late Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_LCOL);
807	printf(" Excessive Coll:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_EXCOL);
808	printf(" FIFO Underrun:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_MACERR);
809	printf(" Carrier Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_CSERR);
810	printf(" Tx SQE Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_SQE);
811	printf("Tx Pause Frames:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FDXFC);
812	printf(" Tx Octets OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_OCTETS_OK);
813	printf(" MII interrupts:%-10lu\n", sc->miiInterrupts);
814	if ((sc->mii_sr2 & 0x400) == 0) {
815	printf("LINK DOWN!\n");
816	}
817	else {
818	int speed;
819	int full;
820	int fixed;
821	if (sc->mii_cr & 0x1000) {
822	fixed = 0;
823	speed = sc->mii_sr2 & 0x4000 ? 100 : 10;
824	full = sc->mii_sr2 & 0x200 ? 1 : 0;
825	}
826	else {
827	fixed = 1;
828	speed = sc->mii_cr & 0x2000 ? 100 : 10;
829	full = sc->mii_cr & 0x100 ? 1 : 0;
830	}
831	printf("Link %s %d Mb/s, %s-duplex.\n",
832	fixed ? "fixed" : "auto-negotiate",
833	speed,
834	full ? "full" : "half");
835	}
836	printf(" EIR:%8.8lx ", (uint32_t) MCF5282_FEC_EIR);
837	printf("EIMR:%8.8lx ", (uint32_t) MCF5282_FEC_EIMR);
838	printf("RDAR:%8.8lx ", (uint32_t) MCF5282_FEC_RDAR);
839	printf("TDAR:%8.8lx\n", (uint32_t) MCF5282_FEC_TDAR);
840	printf(" ECR:%8.8lx ", (uint32_t) MCF5282_FEC_ECR);
841	printf(" RCR:%8.8lx ", (uint32_t) MCF5282_FEC_RCR);
842	printf(" TCR:%8.8lx\n", (uint32_t) MCF5282_FEC_TCR);
843	printf("FRBR:%8.8lx ", (uint32_t) MCF5282_FEC_FRBR);
844	printf("FRSR:%8.8lx\n", (uint32_t) MCF5282_FEC_FRSR);
845	if (sc->txBdActiveCount != 0) {
846	int i, n;
847	/*
848	* Yes, there are races here with adding and retiring descriptors,
849	* but this diagnostic is more for when things have backed up.
850	*/
851	printf("Transmit Buffer Descriptors (Tail %d, Head %d, Unretired %d):\n",
852	sc->txBdTail,
853	sc->txBdHead,
854	sc->txBdActiveCount);
855	i = sc->txBdTail;
856	for (n = 0 ; n < sc->txBdCount ; n++) {
857	if ((sc->txBdBase[i].status & MCF5282_FEC_TxBD_R) != 0)
858	printf(" %3d: status:%4.4x length:%-4d buffer:%p\n",
859	i,
860	sc->txBdBase[i].status,
861	sc->txBdBase[i].length,
862	sc->txBdBase[i].buffer);
863	if (++i == sc->txBdCount)
864	i = 0;
865	}
866	}
867	}
868
869	static int
870	fec_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
871	{
872	struct mcf5282_enet_struct *sc = ifp->if_softc;
873	int error = 0;
874
875	switch (command) {
876	case SIOCGIFADDR:
877	case SIOCSIFADDR:
878	ether_ioctl(ifp, command, data);
879	break;
880
881	case SIOCSIFFLAGS:
882	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
883	case IFF_RUNNING:
884	fec_stop(sc);
885	break;
886
887	case IFF_UP:
888	fec_init(sc);
889	break;
890
891	case IFF_UP \| IFF_RUNNING:
892	fec_stop(sc);
893	fec_init(sc);
894	break;
895
896	default:
897	break;
898	}
899	break;
900
901	case SIO_RTEMS_SHOW_STATS:
902	enet_stats(sc);
903	break;
904
905	/*
906	* FIXME: All sorts of multicast commands need to be added here!
907	*/
908	default:
909	error = EINVAL;
910	break;
911	}
912	return error;
913	}
914
915	int
916	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
917	{
918	struct mcf5282_enet_struct *sc;
919	struct ifnet *ifp;
920	int mtu;
921	int unitNumber;
922	char *unitName;
923	const unsigned char *hwaddr;
924	const char *env;
925
926	/*
927	* Parse driver name
928	*/
929	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
930	return 0;
931
932	/*
933	* Is driver free?
934	*/
935	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
936	printf("Bad FEC unit number.\n");
937	return 0;
938	}
939	sc = &enet_driver[unitNumber - 1];
940	ifp = &sc->arpcom.ac_if;
941	if (ifp->if_softc != NULL) {
942	printf("Driver already in use.\n");
943	return 0;
944	}
945
946	/*
947	* Process options
948	*/
949	if (config->hardware_address) {
950	hwaddr = config->hardware_address;
951	} else if ((hwaddr = bsp_gethwaddr(unitNumber - 1)) == NULL) {
952	/* Locally-administered address */
953	static const unsigned char defaultAddress[ETHER_ADDR_LEN] = {
954	0x06, 'R', 'T', 'E', 'M', 'S'};
955	printf ("WARNING -- No %s%d Ethernet address specified "
956	"-- Using default address.\n", unitName, unitNumber);
957	hwaddr = defaultAddress;
958	}
959	printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n",
960	unitName, unitNumber,
961	hwaddr[0], hwaddr[1], hwaddr[2],
962	hwaddr[3], hwaddr[4], hwaddr[5]);
963	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
964
965	if (config->mtu)
966	mtu = config->mtu;
967	else
968	mtu = ETHERMTU;
969	if (config->rbuf_count)
970	sc->rxBdCount = config->rbuf_count;
971	else
972	sc->rxBdCount = RX_BUF_COUNT;
973	if (config->xbuf_count)
974	sc->txBdCount = config->xbuf_count;
975	else
976	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
977
978	sc->acceptBroadcast = !config->ignore_broadcast;
979
980	/*
981	* Set up network interface values
982	*/
983	ifp->if_softc = sc;
984	ifp->if_unit = unitNumber;
985	ifp->if_name = unitName;
986	ifp->if_mtu = mtu;
987	ifp->if_init = fec_init;
988	ifp->if_ioctl = fec_ioctl;
989	ifp->if_start = mcf5282_enet_start;
990	ifp->if_output = ether_output;
991	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
992	if (ifp->if_snd.ifq_maxlen == 0)
993	ifp->if_snd.ifq_maxlen = ifqmaxlen;
994
995	/*
996	* Check for environment overrides
997	*/
998	if (((env = bsp_getbenv("IPADDR0_100FULL")) != NULL)
999	&& ((env == 'y') \|\| (env == 'Y')))
1000	sc->link = link_100Full;
1001	else if (((env = bsp_getbenv("IPADDR0_10HALF")) != NULL)
1002	&& ((env == 'y') \|\| (env == 'Y')))
1003	sc->link = link_10Half;
1004	else
1005	sc->link = link_auto;
1006
1007	/*
1008	* Attach the interface
1009	*/
1010	if_attach(ifp);
1011	ether_ifattach(ifp);
1012	return 1;
1013	};

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source: rtems/bsps/m68k/uC5282/net/network.c @ 031df391

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