| 1 | #include "fpsp-namespace.h" |
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| 2 | // |
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| 3 | // |
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| 4 | // bugfix.sa 3.2 1/31/91 |
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| 5 | // |
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| 6 | // This file contains workarounds for bugs in the 040 |
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| 7 | // relating to the Floating-Point Software Package (FPSP) |
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| 8 | // |
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| 9 | // Fixes for bugs: 1238 |
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| 10 | // |
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| 11 | // Bug: 1238 |
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| 12 | // |
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| 13 | // |
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| 14 | // /* The following dirty_bit clear should be left in |
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| 15 | // * the handler permanently to improve throughput. |
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| 16 | // * The dirty_bits are located at bits [23:16] in |
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| 17 | // * longword $08 in the busy frame $4x60. Bit 16 |
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| 18 | // * corresponds to FP0, bit 17 corresponds to FP1, |
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| 19 | // * and so on. |
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| 20 | // */ |
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| 21 | // if (E3_exception_just_serviced) { |
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| 22 | // dirty_bit[cmdreg3b[9:7]] = 0; |
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| 23 | // } |
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| 24 | // |
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| 25 | // if (fsave_format_version != $40) {goto NOFIX} |
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| 26 | // |
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| 27 | // if !(E3_exception_just_serviced) {goto NOFIX} |
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| 28 | // if (cupc == 0000000) {goto NOFIX} |
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| 29 | // if ((cmdreg1b[15:13] != 000) && |
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| 30 | // (cmdreg1b[15:10] != 010001)) {goto NOFIX} |
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| 31 | // if (((cmdreg1b[15:13] != 000) || ((cmdreg1b[12:10] != cmdreg2b[9:7]) && |
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| 32 | // (cmdreg1b[12:10] != cmdreg3b[9:7])) ) && |
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| 33 | // ((cmdreg1b[ 9: 7] != cmdreg2b[9:7]) && |
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| 34 | // (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) ) {goto NOFIX} |
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| 35 | // |
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| 36 | // /* Note: for 6d43b or 8d43b, you may want to add the following code |
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| 37 | // * to get better coverage. (If you do not insert this code, the part |
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| 38 | // * won't lock up; it will simply get the wrong answer.) |
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| 39 | // * Do NOT insert this code for 10d43b or later parts. |
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| 40 | // * |
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| 41 | // * if (fpiarcu == integer stack return address) { |
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| 42 | // * cupc = 0000000; |
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| 43 | // * goto NOFIX; |
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| 44 | // * } |
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| 45 | // */ |
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| 46 | // |
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| 47 | // if (cmdreg1b[15:13] != 000) {goto FIX_OPCLASS2} |
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| 48 | // FIX_OPCLASS0: |
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| 49 | // if (((cmdreg1b[12:10] == cmdreg2b[9:7]) || |
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| 50 | // (cmdreg1b[ 9: 7] == cmdreg2b[9:7])) && |
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| 51 | // (cmdreg1b[12:10] != cmdreg3b[9:7]) && |
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| 52 | // (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) { /* xu conflict only */ |
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| 53 | // /* We execute the following code if there is an |
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| 54 | // xu conflict and NOT an nu conflict */ |
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| 55 | // |
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| 56 | // /* first save some values on the fsave frame */ |
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| 57 | // stag_temp = STAG[fsave_frame]; |
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| 58 | // cmdreg1b_temp = CMDREG1B[fsave_frame]; |
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| 59 | // dtag_temp = DTAG[fsave_frame]; |
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| 60 | // ete15_temp = ETE15[fsave_frame]; |
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| 61 | // |
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| 62 | // CUPC[fsave_frame] = 0000000; |
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| 63 | // FRESTORE |
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| 64 | // FSAVE |
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| 65 | // |
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| 66 | // /* If the xu instruction is exceptional, we punt. |
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| 67 | // * Otherwise, we would have to include OVFL/UNFL handler |
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| 68 | // * code here to get the correct answer. |
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| 69 | // */ |
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| 70 | // if (fsave_frame_format == $4060) {goto KILL_PROCESS} |
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| 71 | // |
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| 72 | // fsave_frame = /* build a long frame of all zeros */ |
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| 73 | // fsave_frame_format = $4060; /* label it as long frame */ |
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| 74 | // |
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| 75 | // /* load it with the temps we saved */ |
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| 76 | // STAG[fsave_frame] = stag_temp; |
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| 77 | // CMDREG1B[fsave_frame] = cmdreg1b_temp; |
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| 78 | // DTAG[fsave_frame] = dtag_temp; |
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| 79 | // ETE15[fsave_frame] = ete15_temp; |
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| 80 | // |
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| 81 | // /* Make sure that the cmdreg3b dest reg is not going to |
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| 82 | // * be destroyed by a FMOVEM at the end of all this code. |
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| 83 | // * If it is, you should move the current value of the reg |
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| 84 | // * onto the stack so that the reg will loaded with that value. |
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| 85 | // */ |
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| 86 | // |
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| 87 | // /* All done. Proceed with the code below */ |
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| 88 | // } |
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| 89 | // |
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| 90 | // etemp = FP_reg_[cmdreg1b[12:10]]; |
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| 91 | // ete15 = ~ete14; |
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| 92 | // cmdreg1b[15:10] = 010010; |
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| 93 | // clear(bug_flag_procIDxxxx); |
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| 94 | // FRESTORE and return; |
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| 95 | // |
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| 96 | // |
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| 97 | // FIX_OPCLASS2: |
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| 98 | // if ((cmdreg1b[9:7] == cmdreg2b[9:7]) && |
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| 99 | // (cmdreg1b[9:7] != cmdreg3b[9:7])) { /* xu conflict only */ |
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| 100 | // /* We execute the following code if there is an |
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| 101 | // xu conflict and NOT an nu conflict */ |
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| 102 | // |
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| 103 | // /* first save some values on the fsave frame */ |
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| 104 | // stag_temp = STAG[fsave_frame]; |
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| 105 | // cmdreg1b_temp = CMDREG1B[fsave_frame]; |
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| 106 | // dtag_temp = DTAG[fsave_frame]; |
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| 107 | // ete15_temp = ETE15[fsave_frame]; |
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| 108 | // etemp_temp = ETEMP[fsave_frame]; |
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| 109 | // |
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| 110 | // CUPC[fsave_frame] = 0000000; |
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| 111 | // FRESTORE |
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| 112 | // FSAVE |
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| 113 | // |
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| 114 | // |
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| 115 | // /* If the xu instruction is exceptional, we punt. |
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| 116 | // * Otherwise, we would have to include OVFL/UNFL handler |
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| 117 | // * code here to get the correct answer. |
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| 118 | // */ |
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| 119 | // if (fsave_frame_format == $4060) {goto KILL_PROCESS} |
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| 120 | // |
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| 121 | // fsave_frame = /* build a long frame of all zeros */ |
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| 122 | // fsave_frame_format = $4060; /* label it as long frame */ |
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| 123 | // |
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| 124 | // /* load it with the temps we saved */ |
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| 125 | // STAG[fsave_frame] = stag_temp; |
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| 126 | // CMDREG1B[fsave_frame] = cmdreg1b_temp; |
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| 127 | // DTAG[fsave_frame] = dtag_temp; |
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| 128 | // ETE15[fsave_frame] = ete15_temp; |
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| 129 | // ETEMP[fsave_frame] = etemp_temp; |
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| 130 | // |
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| 131 | // /* Make sure that the cmdreg3b dest reg is not going to |
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| 132 | // * be destroyed by a FMOVEM at the end of all this code. |
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| 133 | // * If it is, you should move the current value of the reg |
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| 134 | // * onto the stack so that the reg will loaded with that value. |
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| 135 | // */ |
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| 136 | // |
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| 137 | // /* All done. Proceed with the code below */ |
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| 138 | // } |
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| 139 | // |
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| 140 | // if (etemp_exponent == min_sgl) etemp_exponent = min_dbl; |
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| 141 | // if (etemp_exponent == max_sgl) etemp_exponent = max_dbl; |
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| 142 | // cmdreg1b[15:10] = 010101; |
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| 143 | // clear(bug_flag_procIDxxxx); |
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| 144 | // FRESTORE and return; |
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| 145 | // |
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| 146 | // |
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| 147 | // NOFIX: |
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| 148 | // clear(bug_flag_procIDxxxx); |
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| 149 | // FRESTORE and return; |
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| 150 | // |
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| 151 | |
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| 152 | |
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| 153 | // Copyright (C) Motorola, Inc. 1990 |
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| 154 | // All Rights Reserved |
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| 155 | // |
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| 156 | // THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA |
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| 157 | // The copyright notice above does not evidence any |
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| 158 | // actual or intended publication of such source code. |
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| 159 | |
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| 160 | //BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package |
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| 161 | |
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| 162 | |section 8 |
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| 163 | |
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| 164 | #include "fpsp.defs" |
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| 165 | |
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| 166 | |xref fpsp_fmt_error |
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| 167 | |
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| 168 | .global b1238_fix |
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| 169 | b1238_fix: |
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| 170 | // |
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| 171 | // This code is entered only on completion of the handling of an |
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| 172 | // nu-generated ovfl, unfl, or inex exception. If the version |
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| 173 | // number of the fsave is not $40, this handler is not necessary. |
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| 174 | // Simply branch to fix_done and exit normally. |
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| 175 | // |
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| 176 | cmpib #VER_40,4(%a7) |
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| 177 | bne fix_done |
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| 178 | // |
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| 179 | // Test for cu_savepc equal to zero. If not, this is not a bug |
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| 180 | // #1238 case. |
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| 181 | // |
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| 182 | moveb CU_SAVEPC(%a6),%d0 |
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| 183 | andib #0xFE,%d0 |
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| 184 | beq fix_done //if zero, this is not bug #1238 |
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| 185 | |
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| 186 | // |
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| 187 | // Test the register conflict aspect. If opclass0, check for |
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| 188 | // cu src equal to xu dest or equal to nu dest. If so, go to |
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| 189 | // op0. Else, or if opclass2, check for cu dest equal to |
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| 190 | // xu dest or equal to nu dest. If so, go to tst_opcl. Else, |
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| 191 | // exit, it is not the bug case. |
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| 192 | // |
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| 193 | // Check for opclass 0. If not, go and check for opclass 2 and sgl. |
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| 194 | // |
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| 195 | movew CMDREG1B(%a6),%d0 |
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| 196 | andiw #0xE000,%d0 //strip all but opclass |
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| 197 | bne op2sgl //not opclass 0, check op2 |
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| 198 | // |
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| 199 | // Check for cu and nu register conflict. If one exists, this takes |
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| 200 | // priority over a cu and xu conflict. |
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| 201 | // |
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| 202 | bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src |
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| 203 | bfextu CMDREG3B(%a6){#6:#3},%d1 //get 3rd dest |
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| 204 | cmpb %d0,%d1 |
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| 205 | beqs op0 //if equal, continue bugfix |
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| 206 | // |
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| 207 | // Check for cu dest equal to nu dest. If so, go and fix the |
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| 208 | // bug condition. Otherwise, exit. |
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| 209 | // |
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| 210 | bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest |
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| 211 | cmpb %d0,%d1 //cmp 1st dest with 3rd dest |
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| 212 | beqs op0 //if equal, continue bugfix |
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| 213 | // |
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| 214 | // Check for cu and xu register conflict. |
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| 215 | // |
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| 216 | bfextu CMDREG2B(%a6){#6:#3},%d1 //get 2nd dest |
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| 217 | cmpb %d0,%d1 //cmp 1st dest with 2nd dest |
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| 218 | beqs op0_xu //if equal, continue bugfix |
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| 219 | bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src |
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| 220 | cmpb %d0,%d1 //cmp 1st src with 2nd dest |
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| 221 | beq op0_xu |
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| 222 | bne fix_done //if the reg checks fail, exit |
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| 223 | // |
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| 224 | // We have the opclass 0 situation. |
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| 225 | // |
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| 226 | op0: |
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| 227 | bfextu CMDREG1B(%a6){#3:#3},%d0 //get source register no |
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| 228 | movel #7,%d1 |
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| 229 | subl %d0,%d1 |
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| 230 | clrl %d0 |
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| 231 | bsetl %d1,%d0 |
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| 232 | fmovemx %d0,ETEMP(%a6) //load source to ETEMP |
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| 233 | |
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| 234 | moveb #0x12,%d0 |
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| 235 | bfins %d0,CMDREG1B(%a6){#0:#6} //opclass 2, extended |
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| 236 | // |
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| 237 | // Set ETEMP exponent bit 15 as the opposite of ete14 |
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| 238 | // |
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| 239 | btst #6,ETEMP_EX(%a6) //check etemp exponent bit 14 |
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| 240 | beq setete15 |
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| 241 | bclr #etemp15_bit,STAG(%a6) |
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| 242 | bra finish |
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| 243 | setete15: |
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| 244 | bset #etemp15_bit,STAG(%a6) |
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| 245 | bra finish |
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| 246 | |
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| 247 | // |
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| 248 | // We have the case in which a conflict exists between the cu src or |
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| 249 | // dest and the dest of the xu. We must clear the instruction in |
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| 250 | // the cu and restore the state, allowing the instruction in the |
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| 251 | // xu to complete. Remember, the instruction in the nu |
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| 252 | // was exceptional, and was completed by the appropriate handler. |
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| 253 | // If the result of the xu instruction is not exceptional, we can |
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| 254 | // restore the instruction from the cu to the frame and continue |
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| 255 | // processing the original exception. If the result is also |
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| 256 | // exceptional, we choose to kill the process. |
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| 257 | // |
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| 258 | // Items saved from the stack: |
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| 259 | // |
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| 260 | // $3c stag - L_SCR1 |
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| 261 | // $40 cmdreg1b - L_SCR2 |
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| 262 | // $44 dtag - L_SCR3 |
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| 263 | // |
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| 264 | // The cu savepc is set to zero, and the frame is restored to the |
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| 265 | // fpu. |
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| 266 | // |
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| 267 | op0_xu: |
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| 268 | movel STAG(%a6),L_SCR1(%a6) |
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| 269 | movel CMDREG1B(%a6),L_SCR2(%a6) |
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| 270 | movel DTAG(%a6),L_SCR3(%a6) |
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| 271 | andil #0xe0000000,L_SCR3(%a6) |
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| 272 | moveb #0,CU_SAVEPC(%a6) |
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| 273 | movel (%a7)+,%d1 //save return address from bsr |
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| 274 | frestore (%a7)+ |
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| 275 | fsave -(%a7) |
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| 276 | // |
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| 277 | // Check if the instruction which just completed was exceptional. |
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| 278 | // |
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| 279 | cmpw #0x4060,(%a7) |
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| 280 | beq op0_xb |
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| 281 | // |
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| 282 | // It is necessary to isolate the result of the instruction in the |
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| 283 | // xu if it is to fp0 - fp3 and write that value to the USER_FPn |
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| 284 | // locations on the stack. The correct destination register is in |
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| 285 | // cmdreg2b. |
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| 286 | // |
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| 287 | bfextu CMDREG2B(%a6){#6:#3},%d0 //get dest register no |
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| 288 | cmpil #3,%d0 |
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| 289 | bgts op0_xi |
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| 290 | beqs op0_fp3 |
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| 291 | cmpil #1,%d0 |
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| 292 | blts op0_fp0 |
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| 293 | beqs op0_fp1 |
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| 294 | op0_fp2: |
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| 295 | fmovemx %fp2-%fp2,USER_FP2(%a6) |
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| 296 | bras op0_xi |
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| 297 | op0_fp1: |
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| 298 | fmovemx %fp1-%fp1,USER_FP1(%a6) |
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| 299 | bras op0_xi |
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| 300 | op0_fp0: |
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| 301 | fmovemx %fp0-%fp0,USER_FP0(%a6) |
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| 302 | bras op0_xi |
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| 303 | op0_fp3: |
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| 304 | fmovemx %fp3-%fp3,USER_FP3(%a6) |
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| 305 | // |
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| 306 | // The frame returned is idle. We must build a busy frame to hold |
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| 307 | // the cu state information and setup etemp. |
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| 308 | // |
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| 309 | op0_xi: |
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| 310 | movel #22,%d0 //clear 23 lwords |
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| 311 | clrl (%a7) |
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| 312 | op0_loop: |
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| 313 | clrl -(%a7) |
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| 314 | dbf %d0,op0_loop |
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| 315 | movel #0x40600000,-(%a7) |
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| 316 | movel L_SCR1(%a6),STAG(%a6) |
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| 317 | movel L_SCR2(%a6),CMDREG1B(%a6) |
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| 318 | movel L_SCR3(%a6),DTAG(%a6) |
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| 319 | moveb #0x6,CU_SAVEPC(%a6) |
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| 320 | movel %d1,-(%a7) //return bsr return address |
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| 321 | bfextu CMDREG1B(%a6){#3:#3},%d0 //get source register no |
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| 322 | movel #7,%d1 |
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| 323 | subl %d0,%d1 |
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| 324 | clrl %d0 |
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| 325 | bsetl %d1,%d0 |
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| 326 | fmovemx %d0,ETEMP(%a6) //load source to ETEMP |
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| 327 | |
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| 328 | moveb #0x12,%d0 |
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| 329 | bfins %d0,CMDREG1B(%a6){#0:#6} //opclass 2, extended |
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| 330 | // |
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| 331 | // Set ETEMP exponent bit 15 as the opposite of ete14 |
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| 332 | // |
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| 333 | btst #6,ETEMP_EX(%a6) //check etemp exponent bit 14 |
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| 334 | beq op0_sete15 |
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| 335 | bclr #etemp15_bit,STAG(%a6) |
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| 336 | bra finish |
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| 337 | op0_sete15: |
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| 338 | bset #etemp15_bit,STAG(%a6) |
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| 339 | bra finish |
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| 340 | |
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| 341 | // |
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| 342 | // The frame returned is busy. It is not possible to reconstruct |
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| 343 | // the code sequence to allow completion. We will jump to |
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| 344 | // fpsp_fmt_error and allow the kernel to kill the process. |
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| 345 | // |
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| 346 | op0_xb: |
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| 347 | jmp fpsp_fmt_error |
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| 348 | |
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| 349 | // |
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| 350 | // Check for opclass 2 and single size. If not both, exit. |
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| 351 | // |
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| 352 | op2sgl: |
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| 353 | movew CMDREG1B(%a6),%d0 |
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| 354 | andiw #0xFC00,%d0 //strip all but opclass and size |
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| 355 | cmpiw #0x4400,%d0 //test for opclass 2 and size=sgl |
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| 356 | bne fix_done //if not, it is not bug 1238 |
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| 357 | // |
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| 358 | // Check for cu dest equal to nu dest or equal to xu dest, with |
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| 359 | // a cu and nu conflict taking priority an nu conflict. If either, |
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| 360 | // go and fix the bug condition. Otherwise, exit. |
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| 361 | // |
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| 362 | bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest |
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| 363 | bfextu CMDREG3B(%a6){#6:#3},%d1 //get 3rd dest |
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| 364 | cmpb %d0,%d1 //cmp 1st dest with 3rd dest |
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| 365 | beq op2_com //if equal, continue bugfix |
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| 366 | bfextu CMDREG2B(%a6){#6:#3},%d1 //get 2nd dest |
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| 367 | cmpb %d0,%d1 //cmp 1st dest with 2nd dest |
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| 368 | bne fix_done //if the reg checks fail, exit |
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| 369 | // |
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| 370 | // We have the case in which a conflict exists between the cu src or |
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| 371 | // dest and the dest of the xu. We must clear the instruction in |
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| 372 | // the cu and restore the state, allowing the instruction in the |
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| 373 | // xu to complete. Remember, the instruction in the nu |
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| 374 | // was exceptional, and was completed by the appropriate handler. |
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| 375 | // If the result of the xu instruction is not exceptional, we can |
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| 376 | // restore the instruction from the cu to the frame and continue |
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| 377 | // processing the original exception. If the result is also |
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| 378 | // exceptional, we choose to kill the process. |
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| 379 | // |
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| 380 | // Items saved from the stack: |
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| 381 | // |
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| 382 | // $3c stag - L_SCR1 |
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| 383 | // $40 cmdreg1b - L_SCR2 |
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| 384 | // $44 dtag - L_SCR3 |
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| 385 | // etemp - FP_SCR2 |
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| 386 | // |
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| 387 | // The cu savepc is set to zero, and the frame is restored to the |
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| 388 | // fpu. |
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| 389 | // |
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| 390 | op2_xu: |
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| 391 | movel STAG(%a6),L_SCR1(%a6) |
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| 392 | movel CMDREG1B(%a6),L_SCR2(%a6) |
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| 393 | movel DTAG(%a6),L_SCR3(%a6) |
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| 394 | andil #0xe0000000,L_SCR3(%a6) |
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| 395 | moveb #0,CU_SAVEPC(%a6) |
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| 396 | movel ETEMP(%a6),FP_SCR2(%a6) |
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| 397 | movel ETEMP_HI(%a6),FP_SCR2+4(%a6) |
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| 398 | movel ETEMP_LO(%a6),FP_SCR2+8(%a6) |
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| 399 | movel (%a7)+,%d1 //save return address from bsr |
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| 400 | frestore (%a7)+ |
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| 401 | fsave -(%a7) |
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| 402 | // |
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| 403 | // Check if the instruction which just completed was exceptional. |
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| 404 | // |
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| 405 | cmpw #0x4060,(%a7) |
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| 406 | beq op2_xb |
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| 407 | // |
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| 408 | // It is necessary to isolate the result of the instruction in the |
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| 409 | // xu if it is to fp0 - fp3 and write that value to the USER_FPn |
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| 410 | // locations on the stack. The correct destination register is in |
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| 411 | // cmdreg2b. |
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| 412 | // |
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| 413 | bfextu CMDREG2B(%a6){#6:#3},%d0 //get dest register no |
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| 414 | cmpil #3,%d0 |
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| 415 | bgts op2_xi |
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| 416 | beqs op2_fp3 |
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| 417 | cmpil #1,%d0 |
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| 418 | blts op2_fp0 |
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| 419 | beqs op2_fp1 |
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| 420 | op2_fp2: |
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| 421 | fmovemx %fp2-%fp2,USER_FP2(%a6) |
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| 422 | bras op2_xi |
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| 423 | op2_fp1: |
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| 424 | fmovemx %fp1-%fp1,USER_FP1(%a6) |
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| 425 | bras op2_xi |
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| 426 | op2_fp0: |
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| 427 | fmovemx %fp0-%fp0,USER_FP0(%a6) |
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| 428 | bras op2_xi |
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| 429 | op2_fp3: |
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| 430 | fmovemx %fp3-%fp3,USER_FP3(%a6) |
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| 431 | // |
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| 432 | // The frame returned is idle. We must build a busy frame to hold |
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| 433 | // the cu state information and fix up etemp. |
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| 434 | // |
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| 435 | op2_xi: |
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| 436 | movel #22,%d0 //clear 23 lwords |
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| 437 | clrl (%a7) |
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| 438 | op2_loop: |
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| 439 | clrl -(%a7) |
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| 440 | dbf %d0,op2_loop |
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| 441 | movel #0x40600000,-(%a7) |
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| 442 | movel L_SCR1(%a6),STAG(%a6) |
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| 443 | movel L_SCR2(%a6),CMDREG1B(%a6) |
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| 444 | movel L_SCR3(%a6),DTAG(%a6) |
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| 445 | moveb #0x6,CU_SAVEPC(%a6) |
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| 446 | movel FP_SCR2(%a6),ETEMP(%a6) |
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| 447 | movel FP_SCR2+4(%a6),ETEMP_HI(%a6) |
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| 448 | movel FP_SCR2+8(%a6),ETEMP_LO(%a6) |
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| 449 | movel %d1,-(%a7) |
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| 450 | bra op2_com |
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| 451 | |
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| 452 | // |
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| 453 | // We have the opclass 2 single source situation. |
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| 454 | // |
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| 455 | op2_com: |
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| 456 | moveb #0x15,%d0 |
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| 457 | bfins %d0,CMDREG1B(%a6){#0:#6} //opclass 2, double |
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| 458 | |
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| 459 | cmpw #0x407F,ETEMP_EX(%a6) //single +max |
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| 460 | bnes case2 |
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| 461 | movew #0x43FF,ETEMP_EX(%a6) //to double +max |
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| 462 | bra finish |
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| 463 | case2: |
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| 464 | cmpw #0xC07F,ETEMP_EX(%a6) //single -max |
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| 465 | bnes case3 |
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| 466 | movew #0xC3FF,ETEMP_EX(%a6) //to double -max |
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| 467 | bra finish |
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| 468 | case3: |
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| 469 | cmpw #0x3F80,ETEMP_EX(%a6) //single +min |
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| 470 | bnes case4 |
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| 471 | movew #0x3C00,ETEMP_EX(%a6) //to double +min |
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| 472 | bra finish |
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| 473 | case4: |
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| 474 | cmpw #0xBF80,ETEMP_EX(%a6) //single -min |
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| 475 | bne fix_done |
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| 476 | movew #0xBC00,ETEMP_EX(%a6) //to double -min |
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| 477 | bra finish |
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| 478 | // |
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| 479 | // The frame returned is busy. It is not possible to reconstruct |
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| 480 | // the code sequence to allow completion. fpsp_fmt_error causes |
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| 481 | // an fline illegal instruction to be executed. |
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| 482 | // |
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| 483 | // You should replace the jump to fpsp_fmt_error with a jump |
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| 484 | // to the entry point used to kill a process. |
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| 485 | // |
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| 486 | op2_xb: |
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| 487 | jmp fpsp_fmt_error |
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| 488 | |
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| 489 | // |
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| 490 | // Enter here if the case is not of the situations affected by |
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| 491 | // bug #1238, or if the fix is completed, and exit. |
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| 492 | // |
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| 493 | finish: |
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| 494 | fix_done: |
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| 495 | rts |
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| 496 | |
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| 497 | |end |
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