source: rtems/bsps/m68k/shared/cache/cache.h @ b82a4b4

Last change on this file since b82a4b4 was cba349c, checked in by Joel Sherrill <joel@…>, on Aug 17, 2018 at 6:30:19 PM

bsps/m68k/shared/cache/cache.h: Fix warnings and clean up

  • Property mode set to 100644
File size: 6.0 KB
Line 
1/*
2 *  M68K Cache Manager Support
3 */
4
5#if (defined(__mc68020__) && !defined(__mcpu32__))
6# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
7#elif defined(__mc68030__)
8# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
9# define M68K_DATA_CACHE_ALIGNMENT 16
10#elif ( defined(__mc68040__) || defined (__mc68060__) )
11# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
12# define M68K_DATA_CACHE_ALIGNMENT 16
13#elif ( defined(__mcf5200__) )
14# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
15# if ( defined(__mcf528x__) )
16#  define M68K_DATA_CACHE_ALIGNMENT 16
17# endif
18#elif ( defined(__mcf5300__) )
19# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
20# define M68K_DATA_CACHE_ALIGNMENT 16
21#elif defined(__mcfv4e__)
22# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
23# define M68K_DATA_CACHE_ALIGNMENT 16
24#endif
25
26#if defined(M68K_DATA_CACHE_ALIGNMENT)
27#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
28#endif
29
30#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
31#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
32#endif
33
34/*
35 *  Since the cacr is common to all mc680x0, provide macros
36 *  for masking values in that register.
37 */
38
39/*
40 *  Used to clear bits in the cacr.
41 */
42#define _CPU_CACR_AND(mask)                                        \
43  {                                                                \
44  register unsigned long _value = mask;                            \
45  register unsigned long _ctl = 0;                                 \
46  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
47                  andl %2, %0;                /* and with _val */  \
48                  movec %1, %%cacr"           /* write the cacr */ \
49   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
50  }
51
52
53/*
54 *  Used to set bits in the cacr.
55 */
56#define _CPU_CACR_OR(mask)                                         \
57  {                                                                \
58  register unsigned long _value = mask;                            \
59  register unsigned long _ctl = 0;                                 \
60  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
61                  orl %2, %0;                 /* or with _val */   \
62                  movec %1, %%cacr"           /* write the cacr */ \
63   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
64  }
65
66
67/*
68 * CACHE MANAGER: The following functions are CPU-specific.
69 * They provide the basic implementation for the rtems_* cache
70 * management routines. If a given function has no meaning for the CPU,
71 * it does nothing by default.
72 */
73#if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) )
74
75#if defined(__mc68030__)
76
77/* Only the mc68030 has a data cache; it is writethrough only. */
78
79RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(const void * d_addr) {}
80RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void) {}
81
82RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
83  const void * d_addr
84)
85{
86  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
87  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
88  _CPU_CACR_OR(0x00000400);
89}
90
91RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
92{
93  _CPU_CACR_OR( 0x00000800 );
94}
95
96RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void)
97{
98  _CPU_CACR_OR( 0x00000200 );
99}
100
101RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void)
102{
103  _CPU_CACR_AND( 0xFFFFFDFF );
104}
105
106RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
107{
108  _CPU_CACR_OR( 0x00000100 );
109}
110
111RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
112{
113  _CPU_CACR_AND( 0xFFFFFEFF );
114}
115#endif
116
117
118/* Both the 68020 and 68030 have instruction caches */
119
120RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
121  const void * d_addr
122)
123{
124  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
125  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
126  _CPU_CACR_OR( 0x00000004 );
127}
128
129RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
130{
131  _CPU_CACR_OR( 0x00000008 );
132}
133
134RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void)
135{
136  _CPU_CACR_OR( 0x00000002);
137}
138
139RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void)
140{
141  _CPU_CACR_AND( 0xFFFFFFFD );
142}
143
144RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
145{
146  _CPU_CACR_OR( 0x00000001 );
147}
148
149RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
150{
151  _CPU_CACR_AND( 0xFFFFFFFE );
152}
153
154
155#elif ( defined(__mc68040__) || defined (__mc68060__) )
156
157/* Cannot be frozen */
158RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void) {}
159RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void) {}
160RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void) {}
161RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void) {}
162
163RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
164  const void * d_addr
165)
166{
167  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
168  __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
169}
170
171RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
172  const void * d_addr
173)
174{
175  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
176  __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
177}
178
179RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void)
180{
181  __asm__ volatile ( "cpusha %%dc" :: );
182}
183
184RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
185{
186  __asm__ volatile ( "cinva %%dc" :: );
187}
188
189RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
190{
191  _CPU_CACR_OR( 0x80000000 );
192}
193
194RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
195{
196  _CPU_CACR_AND( 0x7FFFFFFF );
197}
198
199RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
200  const void * i_addr )
201{
202  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
203  __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
204}
205
206RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
207{
208  __asm__ volatile ( "cinva %%ic" :: );
209}
210
211RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
212{
213  _CPU_CACR_OR( 0x00008000 );
214}
215
216RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
217{
218  _CPU_CACR_AND( 0xFFFF7FFF );
219}
220#endif
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