1 | /* |
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2 | * M68K Cache Manager Support |
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3 | */ |
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4 | |
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5 | #if (defined(__mc68020__) && !defined(__mcpu32__)) |
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6 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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7 | #elif defined(__mc68030__) |
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8 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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9 | # define M68K_DATA_CACHE_ALIGNMENT 16 |
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10 | #elif ( defined(__mc68040__) || defined (__mc68060__) ) |
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11 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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12 | # define M68K_DATA_CACHE_ALIGNMENT 16 |
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13 | #elif ( defined(__mcf5200__) ) |
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14 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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15 | # if ( defined(__mcf528x__) ) |
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16 | # define M68K_DATA_CACHE_ALIGNMENT 16 |
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17 | # endif |
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18 | #elif ( defined(__mcf5300__) ) |
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19 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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20 | # define M68K_DATA_CACHE_ALIGNMENT 16 |
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21 | #elif defined(__mcfv4e__) |
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22 | # define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 |
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23 | # define M68K_DATA_CACHE_ALIGNMENT 16 |
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24 | #endif |
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25 | |
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26 | #if defined(M68K_DATA_CACHE_ALIGNMENT) |
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27 | #define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT |
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28 | #endif |
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29 | |
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30 | #if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT) |
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31 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT |
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32 | #endif |
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33 | |
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34 | /* |
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35 | * Since the cacr is common to all mc680x0, provide macros |
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36 | * for masking values in that register. |
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37 | */ |
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38 | |
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39 | /* |
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40 | * Used to clear bits in the cacr. |
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41 | */ |
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42 | #define _CPU_CACR_AND(mask) \ |
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43 | { \ |
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44 | register unsigned long _value = mask; \ |
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45 | register unsigned long _ctl = 0; \ |
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46 | __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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47 | andl %2, %0; /* and with _val */ \ |
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48 | movec %1, %%cacr" /* write the cacr */ \ |
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49 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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50 | } |
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51 | |
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52 | |
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53 | /* |
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54 | * Used to set bits in the cacr. |
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55 | */ |
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56 | #define _CPU_CACR_OR(mask) \ |
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57 | { \ |
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58 | register unsigned long _value = mask; \ |
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59 | register unsigned long _ctl = 0; \ |
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60 | __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \ |
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61 | orl %2, %0; /* or with _val */ \ |
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62 | movec %1, %%cacr" /* write the cacr */ \ |
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63 | : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ |
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64 | } |
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65 | |
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66 | |
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67 | /* |
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68 | * CACHE MANAGER: The following functions are CPU-specific. |
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69 | * They provide the basic implementation for the rtems_* cache |
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70 | * management routines. If a given function has no meaning for the CPU, |
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71 | * it does nothing by default. |
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72 | */ |
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73 | #if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) ) |
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74 | |
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75 | #if defined(__mc68030__) |
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76 | |
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77 | /* Only the mc68030 has a data cache; it is writethrough only. */ |
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78 | |
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79 | void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} |
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80 | void _CPU_cache_flush_entire_data ( void ) {} |
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81 | |
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82 | void _CPU_cache_invalidate_1_data_line ( |
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83 | const void * d_addr ) |
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84 | { |
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85 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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86 | __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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87 | _CPU_CACR_OR(0x00000400); |
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88 | } |
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89 | |
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90 | void _CPU_cache_invalidate_entire_data ( void ) |
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91 | { |
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92 | _CPU_CACR_OR( 0x00000800 ); |
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93 | } |
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94 | |
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95 | void _CPU_cache_freeze_data ( void ) |
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96 | { |
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97 | _CPU_CACR_OR( 0x00000200 ); |
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98 | } |
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99 | |
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100 | void _CPU_cache_unfreeze_data ( void ) |
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101 | { |
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102 | _CPU_CACR_AND( 0xFFFFFDFF ); |
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103 | } |
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104 | |
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105 | void _CPU_cache_enable_data ( void ) |
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106 | { |
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107 | _CPU_CACR_OR( 0x00000100 ); |
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108 | } |
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109 | void _CPU_cache_disable_data ( void ) |
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110 | { |
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111 | _CPU_CACR_AND( 0xFFFFFEFF ); |
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112 | } |
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113 | #endif |
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114 | |
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115 | |
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116 | /* Both the 68020 and 68030 have instruction caches */ |
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117 | |
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118 | void _CPU_cache_invalidate_1_instruction_line ( |
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119 | const void * d_addr ) |
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120 | { |
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121 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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122 | __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ |
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123 | _CPU_CACR_OR( 0x00000004 ); |
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124 | } |
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125 | |
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126 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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127 | { |
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128 | _CPU_CACR_OR( 0x00000008 ); |
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129 | } |
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130 | |
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131 | void _CPU_cache_freeze_instruction ( void ) |
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132 | { |
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133 | _CPU_CACR_OR( 0x00000002); |
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134 | } |
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135 | |
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136 | void _CPU_cache_unfreeze_instruction ( void ) |
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137 | { |
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138 | _CPU_CACR_AND( 0xFFFFFFFD ); |
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139 | } |
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140 | |
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141 | void _CPU_cache_enable_instruction ( void ) |
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142 | { |
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143 | _CPU_CACR_OR( 0x00000001 ); |
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144 | } |
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145 | |
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146 | void _CPU_cache_disable_instruction ( void ) |
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147 | { |
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148 | _CPU_CACR_AND( 0xFFFFFFFE ); |
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149 | } |
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150 | |
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151 | |
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152 | #elif ( defined(__mc68040__) || defined (__mc68060__) ) |
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153 | |
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154 | /* Cannot be frozen */ |
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155 | void _CPU_cache_freeze_data ( void ) {} |
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156 | void _CPU_cache_unfreeze_data ( void ) {} |
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157 | void _CPU_cache_freeze_instruction ( void ) {} |
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158 | void _CPU_cache_unfreeze_instruction ( void ) {} |
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159 | |
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160 | void _CPU_cache_flush_1_data_line ( |
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161 | const void * d_addr ) |
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162 | { |
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163 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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164 | __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); |
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165 | } |
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166 | |
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167 | void _CPU_cache_invalidate_1_data_line ( |
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168 | const void * d_addr ) |
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169 | { |
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170 | void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); |
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171 | __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); |
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172 | } |
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173 | |
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174 | void _CPU_cache_flush_entire_data ( void ) |
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175 | { |
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176 | asm volatile ( "cpusha %%dc" :: ); |
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177 | } |
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178 | |
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179 | void _CPU_cache_invalidate_entire_data ( void ) |
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180 | { |
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181 | asm volatile ( "cinva %%dc" :: ); |
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182 | } |
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183 | |
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184 | void _CPU_cache_enable_data ( void ) |
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185 | { |
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186 | _CPU_CACR_OR( 0x80000000 ); |
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187 | } |
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188 | |
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189 | void _CPU_cache_disable_data ( void ) |
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190 | { |
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191 | _CPU_CACR_AND( 0x7FFFFFFF ); |
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192 | } |
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193 | |
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194 | void _CPU_cache_invalidate_1_instruction_line ( |
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195 | const void * i_addr ) |
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196 | { |
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197 | void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); |
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198 | __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); |
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199 | } |
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200 | |
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201 | void _CPU_cache_invalidate_entire_instruction ( void ) |
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202 | { |
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203 | asm volatile ( "cinva %%ic" :: ); |
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204 | } |
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205 | |
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206 | void _CPU_cache_enable_instruction ( void ) |
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207 | { |
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208 | _CPU_CACR_OR( 0x00008000 ); |
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209 | } |
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210 | |
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211 | void _CPU_cache_disable_instruction ( void ) |
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212 | { |
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213 | _CPU_CACR_AND( 0xFFFF7FFF ); |
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214 | } |
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215 | #endif |
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