source: rtems/bsps/m68k/shared/cache/cache.h @ 4cf93658

5
Last change on this file since 4cf93658 was 4cf93658, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 27, 2018 at 1:37:51 PM

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

  • Property mode set to 100644
File size: 5.5 KB
Line 
1/*
2 *  M68K Cache Manager Support
3 */
4
5#if (defined(__mc68020__) && !defined(__mcpu32__))
6# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
7#elif defined(__mc68030__)
8# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
9# define M68K_DATA_CACHE_ALIGNMENT 16
10#elif ( defined(__mc68040__) || defined (__mc68060__) )
11# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
12# define M68K_DATA_CACHE_ALIGNMENT 16
13#elif ( defined(__mcf5200__) )
14# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
15# if ( defined(__mcf528x__) )
16#  define M68K_DATA_CACHE_ALIGNMENT 16
17# endif
18#elif ( defined(__mcf5300__) )
19# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
20# define M68K_DATA_CACHE_ALIGNMENT 16
21#elif defined(__mcfv4e__)
22# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
23# define M68K_DATA_CACHE_ALIGNMENT 16
24#endif
25
26#if defined(M68K_DATA_CACHE_ALIGNMENT)
27#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
28#endif
29
30#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
31#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
32#endif
33
34/*
35 *  Since the cacr is common to all mc680x0, provide macros
36 *  for masking values in that register.
37 */
38
39/*
40 *  Used to clear bits in the cacr.
41 */
42#define _CPU_CACR_AND(mask)                                        \
43  {                                                                \
44  register unsigned long _value = mask;                            \
45  register unsigned long _ctl = 0;                                 \
46  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
47                  andl %2, %0;                /* and with _val */  \
48                  movec %1, %%cacr"           /* write the cacr */ \
49   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
50  }
51
52
53/*
54 *  Used to set bits in the cacr.
55 */
56#define _CPU_CACR_OR(mask)                                         \
57        {                                                                \
58  register unsigned long _value = mask;                            \
59  register unsigned long _ctl = 0;                                 \
60  __asm__ volatile ( "movec %%cacr, %0;           /* read the cacr */  \
61                  orl %2, %0;                 /* or with _val */   \
62                  movec %1, %%cacr"           /* write the cacr */ \
63   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
64  }
65
66
67/*
68 * CACHE MANAGER: The following functions are CPU-specific.
69 * They provide the basic implementation for the rtems_* cache
70 * management routines. If a given function has no meaning for the CPU,
71 * it does nothing by default.
72 */
73#if ( (defined(__mc68020__) && !defined(__mcpu32__)) || defined(__mc68030__) )
74
75#if defined(__mc68030__)
76
77/* Only the mc68030 has a data cache; it is writethrough only. */
78
79void _CPU_cache_flush_1_data_line ( const void * d_addr ) {}
80void _CPU_cache_flush_entire_data ( void ) {}
81
82void _CPU_cache_invalidate_1_data_line (
83  const void * d_addr )
84{
85  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
86  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
87  _CPU_CACR_OR(0x00000400);
88}
89
90void _CPU_cache_invalidate_entire_data ( void )
91{
92  _CPU_CACR_OR( 0x00000800 );
93}
94
95void _CPU_cache_freeze_data ( void )
96{
97  _CPU_CACR_OR( 0x00000200 );
98}
99
100void _CPU_cache_unfreeze_data ( void )
101{
102  _CPU_CACR_AND( 0xFFFFFDFF );
103}
104
105void _CPU_cache_enable_data ( void )
106{
107  _CPU_CACR_OR( 0x00000100 );
108}
109void _CPU_cache_disable_data (  void )
110{
111  _CPU_CACR_AND( 0xFFFFFEFF );
112}
113#endif
114
115
116/* Both the 68020 and 68030 have instruction caches */
117
118void _CPU_cache_invalidate_1_instruction_line (
119  const void * d_addr )
120{
121  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
122  __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
123  _CPU_CACR_OR( 0x00000004 );
124}
125
126void _CPU_cache_invalidate_entire_instruction ( void )
127{
128  _CPU_CACR_OR( 0x00000008 );
129}
130
131void _CPU_cache_freeze_instruction ( void )
132{
133  _CPU_CACR_OR( 0x00000002);
134}
135
136void _CPU_cache_unfreeze_instruction ( void )
137{
138  _CPU_CACR_AND( 0xFFFFFFFD );
139}
140
141void _CPU_cache_enable_instruction ( void )
142{
143  _CPU_CACR_OR( 0x00000001 );
144}
145
146void _CPU_cache_disable_instruction (   void )
147{
148  _CPU_CACR_AND( 0xFFFFFFFE );
149}
150
151
152#elif ( defined(__mc68040__) || defined (__mc68060__) )
153
154/* Cannot be frozen */
155void _CPU_cache_freeze_data ( void ) {}
156void _CPU_cache_unfreeze_data ( void ) {}
157void _CPU_cache_freeze_instruction ( void ) {}
158void _CPU_cache_unfreeze_instruction ( void ) {}
159
160void _CPU_cache_flush_1_data_line (
161  const void * d_addr )
162{
163  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
164  __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
165}
166
167void _CPU_cache_invalidate_1_data_line (
168  const void * d_addr )
169{
170  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
171  __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
172}
173
174void _CPU_cache_flush_entire_data ( void )
175{
176        asm volatile ( "cpusha %%dc" :: );
177}
178
179void _CPU_cache_invalidate_entire_data ( void )
180{
181        asm volatile ( "cinva %%dc" :: );
182}
183
184void _CPU_cache_enable_data ( void )
185{
186  _CPU_CACR_OR( 0x80000000 );
187}
188
189void _CPU_cache_disable_data ( void )
190{
191  _CPU_CACR_AND( 0x7FFFFFFF );
192}
193
194void _CPU_cache_invalidate_1_instruction_line (
195  const void * i_addr )
196{
197  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
198  __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
199}
200
201void _CPU_cache_invalidate_entire_instruction ( void )
202{
203                asm volatile ( "cinva %%ic" :: );
204}
205
206void _CPU_cache_enable_instruction ( void )
207{
208  _CPU_CACR_OR( 0x00008000 );
209}
210
211void _CPU_cache_disable_instruction ( void )
212{
213        _CPU_CACR_AND( 0xFFFF7FFF );
214}
215#endif
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