[b8b2f19] | 1 | /** |
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| 2 | * @file |
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[c2bb3add] | 3 | * |
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[b8b2f19] | 4 | * Cache Management Support Routines for the MCF532x |
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[c2bb3add] | 5 | */ |
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| 6 | |
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| 7 | #include <rtems.h> |
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| 8 | #include <mcf532x/mcf532x.h> |
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[4cf93658] | 9 | #include "cache.h" |
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[c2bb3add] | 10 | |
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[92a8cee] | 11 | #define m68k_set_cacr(_cacr) \ |
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| 12 | __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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[c2bb3add] | 13 | |
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| 14 | /* |
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| 15 | * Read/write copy of common cache |
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| 16 | * Default cache mode is *disabled* (cache only ACRx areas) |
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| 17 | * Allow CPUSHL to invalidate a cache line |
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| 18 | * Enable store buffer |
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| 19 | */ |
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| 20 | static uint32_t cacr_mode = MCF_CACR_ESB | |
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| 21 | MCF_CACR_DCM(3); |
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| 22 | |
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| 23 | /* |
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| 24 | * Cannot be frozen |
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| 25 | */ |
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[4cf93658] | 26 | static void _CPU_cache_freeze_data(void) |
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[c2bb3add] | 27 | { |
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| 28 | } |
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| 29 | |
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[4cf93658] | 30 | static void _CPU_cache_unfreeze_data(void) |
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[c2bb3add] | 31 | { |
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| 32 | } |
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| 33 | |
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[4cf93658] | 34 | static void _CPU_cache_freeze_instruction(void) |
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[c2bb3add] | 35 | { |
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| 36 | } |
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| 37 | |
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[4cf93658] | 38 | static void _CPU_cache_unfreeze_instruction(void) |
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[c2bb3add] | 39 | { |
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| 40 | } |
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| 41 | |
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[4cf93658] | 42 | static void _CPU_cache_flush_1_data_line(const void *d_addr) |
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[c2bb3add] | 43 | { |
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| 44 | register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4; |
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| 45 | |
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[8525cff] | 46 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 47 | adr += 1; |
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[8525cff] | 48 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 49 | adr += 1; |
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[8525cff] | 50 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 51 | adr += 1; |
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[8525cff] | 52 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 53 | } |
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| 54 | |
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[4cf93658] | 55 | static void _CPU_cache_flush_entire_data(void) |
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[c2bb3add] | 56 | { |
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| 57 | register unsigned long set, adr; |
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[023f1dd9] | 58 | |
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[c2bb3add] | 59 | for(set = 0; set < 256; ++set) { |
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| 60 | adr = (set << 4); |
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[8525cff] | 61 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 62 | adr += 1; |
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[8525cff] | 63 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 64 | adr += 1; |
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[8525cff] | 65 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 66 | adr += 1; |
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[8525cff] | 67 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 68 | } |
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| 69 | } |
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| 70 | |
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[4cf93658] | 71 | static void _CPU_cache_enable_instruction(void) |
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[c2bb3add] | 72 | { |
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| 73 | rtems_interrupt_level level; |
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| 74 | |
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| 75 | rtems_interrupt_disable(level); |
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| 76 | if(!(cacr_mode & MCF_CACR_CENB)) |
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| 77 | { |
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| 78 | cacr_mode |= MCF_CACR_CENB; |
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| 79 | m68k_set_cacr(cacr_mode); |
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| 80 | } |
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| 81 | rtems_interrupt_enable(level); |
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| 82 | } |
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| 83 | |
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[4cf93658] | 84 | static void _CPU_cache_disable_instruction(void) |
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[c2bb3add] | 85 | { |
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| 86 | rtems_interrupt_level level; |
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| 87 | |
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| 88 | rtems_interrupt_disable(level); |
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| 89 | if((cacr_mode & MCF_CACR_CENB)) |
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| 90 | { |
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| 91 | cacr_mode &= ~MCF_CACR_CENB; |
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| 92 | m68k_set_cacr(cacr_mode); |
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| 93 | } |
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| 94 | rtems_interrupt_enable(level); |
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| 95 | } |
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| 96 | |
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[4cf93658] | 97 | static void _CPU_cache_invalidate_entire_instruction(void) |
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[c2bb3add] | 98 | { |
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| 99 | m68k_set_cacr(cacr_mode | MCF_CACR_CINVA); |
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| 100 | } |
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| 101 | |
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[4cf93658] | 102 | static void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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[c2bb3add] | 103 | { |
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| 104 | register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4; |
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| 105 | |
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[8525cff] | 106 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 107 | adr += 1; |
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[8525cff] | 108 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 109 | adr += 1; |
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[8525cff] | 110 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 111 | adr += 1; |
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[8525cff] | 112 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr)); |
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[c2bb3add] | 113 | } |
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| 114 | |
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[4cf93658] | 115 | static void _CPU_cache_enable_data(void) |
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[c2bb3add] | 116 | { |
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| 117 | /* |
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| 118 | * The 532x has a unified data and instruction cache, so we call through |
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| 119 | * to enable instruction. |
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| 120 | */ |
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| 121 | _CPU_cache_enable_instruction(); |
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| 122 | } |
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| 123 | |
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[4cf93658] | 124 | static void _CPU_cache_disable_data(void) |
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[c2bb3add] | 125 | { |
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| 126 | /* |
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| 127 | * The 532x has a unified data and instruction cache, so we call through |
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| 128 | * to disable instruction. |
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| 129 | */ |
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| 130 | _CPU_cache_disable_instruction(); |
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| 131 | } |
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| 132 | |
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[4cf93658] | 133 | static void _CPU_cache_invalidate_entire_data(void) |
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[c2bb3add] | 134 | { |
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| 135 | _CPU_cache_invalidate_entire_instruction(); |
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| 136 | } |
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| 137 | |
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[4cf93658] | 138 | static void _CPU_cache_invalidate_1_data_line(const void *addr) |
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[c2bb3add] | 139 | { |
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| 140 | _CPU_cache_invalidate_1_instruction_line(addr); |
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[023f1dd9] | 141 | } |
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[4cf93658] | 142 | |
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| 143 | #include "../../../shared/cache/cacheimpl.h" |
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