1 | /** |
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2 | * @file |
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3 | * |
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4 | * Cache Management Support Routines for the MCF5282 |
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5 | */ |
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6 | |
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7 | #include <rtems.h> |
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8 | #include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ |
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9 | #include "cache.h" |
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10 | |
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11 | /* |
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12 | * CPU-space access |
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13 | */ |
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14 | #define m68k_set_acr0(_acr0) \ |
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15 | __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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16 | #define m68k_set_acr1(_acr1) \ |
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17 | __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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18 | |
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19 | #define NOP __asm__ volatile ("nop"); |
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20 | |
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21 | /* |
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22 | * DEFAULT WHEN mcf5xxx_initialize_cacr not called |
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23 | * Read/write copy of common cache |
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24 | * Split I/D cache |
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25 | * Allow CPUSHL to invalidate a cache line |
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26 | * Enable buffered writes |
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27 | * No burst transfers on non-cacheable accesses |
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28 | * Default cache mode is *disabled* (cache only ACRx areas) |
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29 | */ |
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30 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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31 | MCF5XXX_CACR_DBWE | |
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32 | MCF5XXX_CACR_DCM; |
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33 | |
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34 | void mcf5xxx_initialize_cacr(uint32_t cacr) |
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35 | { |
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36 | cacr_mode = cacr; |
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37 | m68k_set_cacr( cacr_mode ); |
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38 | } |
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39 | |
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40 | /* |
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41 | * Cannot be frozen |
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42 | */ |
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43 | static void _CPU_cache_freeze_data(void) {} |
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44 | static void _CPU_cache_unfreeze_data(void) {} |
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45 | static void _CPU_cache_freeze_instruction(void) {} |
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46 | static void _CPU_cache_unfreeze_instruction(void) {} |
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47 | |
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48 | /* |
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49 | * Write-through data cache -- flushes are unnecessary |
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50 | */ |
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51 | static void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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52 | static void _CPU_cache_flush_entire_data(void) {} |
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53 | |
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54 | static void _CPU_cache_enable_instruction(void) |
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55 | { |
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56 | rtems_interrupt_level level; |
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57 | |
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58 | rtems_interrupt_disable(level); |
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59 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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60 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI ); |
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61 | NOP; |
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62 | rtems_interrupt_enable(level); |
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63 | } |
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64 | |
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65 | static void _CPU_cache_disable_instruction(void) |
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66 | { |
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67 | rtems_interrupt_level level; |
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68 | |
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69 | rtems_interrupt_disable(level); |
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70 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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71 | m68k_set_cacr(cacr_mode); |
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72 | rtems_interrupt_enable(level); |
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73 | } |
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74 | |
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75 | static void _CPU_cache_invalidate_entire_instruction(void) |
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76 | { |
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77 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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78 | NOP; |
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79 | } |
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80 | |
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81 | static void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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82 | { |
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83 | /* |
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84 | * Top half of cache is I-space |
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85 | */ |
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86 | addr = (void *)((int)addr | 0x400); |
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87 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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88 | } |
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89 | |
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90 | static void _CPU_cache_enable_data(void) |
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91 | { |
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92 | rtems_interrupt_level level; |
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93 | |
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94 | rtems_interrupt_disable(level); |
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95 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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96 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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97 | rtems_interrupt_enable(level); |
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98 | } |
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99 | |
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100 | static void _CPU_cache_disable_data(void) |
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101 | { |
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102 | rtems_interrupt_level level; |
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103 | |
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104 | rtems_interrupt_disable(level); |
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105 | cacr_mode |= MCF5XXX_CACR_DISD; |
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106 | m68k_set_cacr(cacr_mode); |
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107 | rtems_interrupt_enable(level); |
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108 | } |
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109 | |
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110 | static void _CPU_cache_invalidate_entire_data(void) |
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111 | { |
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112 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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113 | } |
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114 | |
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115 | static void _CPU_cache_invalidate_1_data_line(const void *addr) |
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116 | { |
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117 | /* |
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118 | * Bottom half of cache is D-space |
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119 | */ |
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120 | addr = (void *)((int)addr & ~0x400); |
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121 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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122 | } |
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123 | |
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124 | #include "../../../shared/cache/cacheimpl.h" |
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