source: rtems/bsps/m68k/shared/cache/cache-mcf5282.c @ d584269

5
Last change on this file since d584269 was 4cf93658, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 27, 2018 at 1:37:51 PM

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/**
2 *  @file
3 *
4 *  Cache Management Support Routines for the MCF5282
5 */
6
7#include <rtems.h>
8#include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
9#include "cache.h"
10
11/*
12 * CPU-space access
13 */
14#define m68k_set_acr0(_acr0) \
15  __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
16#define m68k_set_acr1(_acr1) \
17  __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
18
19#define NOP __asm__ volatile ("nop");
20
21/*
22 * DEFAULT WHEN mcf5xxx_initialize_cacr not called
23 *   Read/write copy of common cache
24 *   Split I/D cache
25 *   Allow CPUSHL to invalidate a cache line
26 *   Enable buffered writes
27 *   No burst transfers on non-cacheable accesses
28 *   Default cache mode is *disabled* (cache only ACRx areas)
29 */
30static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
31                            MCF5XXX_CACR_DBWE |
32                            MCF5XXX_CACR_DCM;
33
34void mcf5xxx_initialize_cacr(uint32_t cacr)
35{
36  cacr_mode = cacr;
37  m68k_set_cacr( cacr_mode );
38}
39
40/*
41 * Cannot be frozen
42 */
43static void _CPU_cache_freeze_data(void) {}
44static void _CPU_cache_unfreeze_data(void) {}
45static void _CPU_cache_freeze_instruction(void) {}
46static void _CPU_cache_unfreeze_instruction(void) {}
47
48/*
49 * Write-through data cache -- flushes are unnecessary
50 */
51static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
52static void _CPU_cache_flush_entire_data(void) {}
53
54static void _CPU_cache_enable_instruction(void)
55{
56  rtems_interrupt_level level;
57
58  rtems_interrupt_disable(level);
59    cacr_mode &= ~MCF5XXX_CACR_DIDI;
60    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI );
61    NOP;
62  rtems_interrupt_enable(level);
63}
64
65static void _CPU_cache_disable_instruction(void)
66{
67  rtems_interrupt_level level;
68
69  rtems_interrupt_disable(level);
70    cacr_mode |= MCF5XXX_CACR_DIDI;
71    m68k_set_cacr(cacr_mode);
72  rtems_interrupt_enable(level);
73}
74
75static void _CPU_cache_invalidate_entire_instruction(void)
76{
77  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
78  NOP;
79}
80
81static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
82{
83  /*
84   * Top half of cache is I-space
85   */
86  addr = (void *)((int)addr | 0x400);
87  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
88}
89
90static void _CPU_cache_enable_data(void)
91{
92  rtems_interrupt_level level;
93
94  rtems_interrupt_disable(level);
95    cacr_mode &= ~MCF5XXX_CACR_DISD;
96    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
97  rtems_interrupt_enable(level);
98}
99
100static void _CPU_cache_disable_data(void)
101{
102  rtems_interrupt_level level;
103
104  rtems_interrupt_disable(level);
105    cacr_mode |= MCF5XXX_CACR_DISD;
106    m68k_set_cacr(cacr_mode);
107  rtems_interrupt_enable(level);
108}
109
110static void _CPU_cache_invalidate_entire_data(void)
111{
112  m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
113}
114
115static void _CPU_cache_invalidate_1_data_line(const void *addr)
116{
117  /*
118   * Bottom half of cache is D-space
119   */
120  addr = (void *)((int)addr & ~0x400);
121  __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
122}
123
124#include "../../../shared/cache/cacheimpl.h"
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