source: rtems/bsps/m68k/shared/cache/cache-mcf5235.c @ 4cf93658

5
Last change on this file since 4cf93658 was 4cf93658, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 27, 2018 at 1:37:51 PM

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 *  COPYRIGHT (c) 1989-2008.
3 *  On-Line Applications Research Corporation (OAR).
4 *
5 *  The license and distribution terms for this file may be
6 *  found in the file LICENSE in this distribution or at
7 *  http://www.rtems.org/license/LICENSE.
8 */
9
10#include <rtems.h>
11#include <mcf5235/mcf5235.h>
12#include "cache.h"
13
14/*
15 *  Default value for the cacr is set by the BSP
16 */
17extern uint32_t cacr_mode;
18
19/*
20 * Cannot be frozen
21 */
22static void _CPU_cache_freeze_data(void) {}
23static void _CPU_cache_unfreeze_data(void) {}
24static void _CPU_cache_freeze_instruction(void) {}
25static void _CPU_cache_unfreeze_instruction(void) {}
26
27/*
28 * Write-through data cache -- flushes are unnecessary
29 */
30static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
31static void _CPU_cache_flush_entire_data(void) {}
32
33static void _CPU_cache_enable_instruction(void)
34{
35    rtems_interrupt_level level;
36
37    rtems_interrupt_disable(level);
38    cacr_mode &= ~MCF5XXX_CACR_DIDI;
39    m68k_set_cacr(cacr_mode);
40    rtems_interrupt_enable(level);
41}
42
43static void _CPU_cache_disable_instruction(void)
44{
45    rtems_interrupt_level level;
46
47    rtems_interrupt_disable(level);
48    cacr_mode |= MCF5XXX_CACR_DIDI;
49    m68k_set_cacr(cacr_mode);
50    rtems_interrupt_enable(level);
51}
52
53static void _CPU_cache_invalidate_entire_instruction(void)
54{
55    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
56}
57
58static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
59{
60    /*
61     * Top half of cache is I-space
62     */
63    addr = (void *)((int)addr | 0x400);
64    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
65}
66
67static void _CPU_cache_enable_data(void)
68{
69    rtems_interrupt_level level;
70
71    rtems_interrupt_disable(level);
72    cacr_mode &= ~MCF5XXX_CACR_DISD;
73    m68k_set_cacr(cacr_mode);
74    rtems_interrupt_enable(level);
75}
76
77static void _CPU_cache_disable_data(void)
78{
79    rtems_interrupt_level level;
80
81    rtems_interrupt_disable(level);
82    cacr_mode |= MCF5XXX_CACR_DISD;
83    m68k_set_cacr(cacr_mode);
84    rtems_interrupt_enable(level);
85}
86
87static void _CPU_cache_invalidate_entire_data(void)
88{
89    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
90}
91
92static void _CPU_cache_invalidate_1_data_line(const void *addr)
93{
94    /*
95     * Bottom half of cache is D-space
96     */
97    addr = (void *)((int)addr & ~0x400);
98    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
99}
100
101#include "../../../shared/cache/cacheimpl.h"
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