1 | /** |
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2 | * @file |
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3 | * |
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4 | * Following defines must reflect the setup of the particular MVME167. |
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5 | * All page references are to the MVME166/MVME167/MVME187 Single Board |
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6 | * Computer Programmer's Reference Guide (MVME187PG/D2) with the April |
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7 | * 1993 supplements/addenda (MVME187PG/D2A1). |
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8 | */ |
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9 | |
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10 | /* |
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11 | * COPYRIGHT (c) 1989-2012. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | * |
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18 | * Modifications of respective RTEMS file: |
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19 | * Copyright (c) 1998, National Research Council of Canada |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_M68K_MVME167_BSP_H |
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23 | #define LIBBSP_M68K_MVME167_BSP_H |
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24 | |
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25 | #include <bspopts.h> |
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26 | #include <bsp/default-initial-extension.h> |
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27 | |
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28 | #include <rtems.h> |
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29 | #include <rtems/bspIo.h> |
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30 | |
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31 | #include <mvme16x_hw.h> |
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32 | |
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33 | #ifdef __cplusplus |
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34 | extern "C" { |
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35 | #endif |
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36 | |
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37 | /* GCSR is in mvme16x_hw.h */ |
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38 | /* LCSR is in mvme16x_hw.h */ |
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39 | /* i82596 is in mvme16x_hw.h */ |
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40 | /* NVRAM is in mvme16x_hw.h */ |
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41 | |
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42 | #if 0 |
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43 | /* |
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44 | * Representation of the PCCchip2 |
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45 | */ |
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46 | typedef volatile struct pccchip2_regs_ { |
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47 | unsigned char chip_id; /* 0xFFF42000 */ |
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48 | unsigned char chip_revision; /* 0xFFF42001 */ |
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49 | unsigned char gen_control; /* 0xFFF42002 */ |
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50 | unsigned char vector_base; /* 0xFFF42003 */ |
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51 | unsigned long timer_cmp_1; /* 0xFFF42004 */ |
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52 | unsigned long timer_cnt_1; /* 0xFFF42008 */ |
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53 | unsigned long timer_cmp_2; /* 0xFFF4200C */ |
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54 | unsigned long timer_cnt_2; /* 0xFFF42010 */ |
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55 | unsigned char LSB_prescaler_count;/* 0xFFF42014 */ |
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56 | unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ |
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57 | unsigned char timer_ctl_2; /* 0xFFF42016 */ |
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58 | unsigned char timer_ctl_1; /* 0xFFF42017 */ |
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59 | unsigned char gpi_int_ctl; /* 0xFFF42018 */ |
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60 | unsigned char gpio_ctl; /* 0xFFF42019 */ |
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61 | unsigned char timer_int_ctl_2; /* 0xFFF4201A */ |
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62 | unsigned char timer_int_ctl_1; /* 0xFFF4201B */ |
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63 | unsigned char SCC_error; /* 0xFFF4201C */ |
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64 | unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ |
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65 | unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ |
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66 | unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ |
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67 | unsigned char reserved1[3]; |
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68 | unsigned char modem_piack; /* 0xFFF42023 */ |
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69 | unsigned char reserved2; |
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70 | unsigned char tx_piack; /* 0xFFF42025 */ |
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71 | unsigned char reserved3; |
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72 | unsigned char rx_piack; /* 0xFFF42027 */ |
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73 | unsigned char LANC_error; /* 0xFFF42028 */ |
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74 | unsigned char reserved4; |
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75 | unsigned char LANC_int_ctl; /* 0xFFF4202A */ |
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76 | unsigned char LANC_berr_ctl; /* 0xFFF4202B */ |
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77 | unsigned char SCSI_error; /* 0xFFF4202C */ |
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78 | unsigned char reserved5[2]; |
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79 | unsigned char SCSI_int_ctl; /* 0xFFF4202F */ |
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80 | unsigned char print_ack_int_ctl; /* 0xFFF42030 */ |
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81 | unsigned char print_fault_int_ctl;/* 0xFFF42031 */ |
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82 | unsigned char print_sel_int_ctl; /* 0xFFF42032 */ |
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83 | unsigned char print_pe_int_ctl; /* 0xFFF42033 */ |
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84 | unsigned char print_busy_int_ctl; /* 0xFFF42034 */ |
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85 | unsigned char reserved6; |
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86 | unsigned char print_input_status; /* 0xFFF42036 */ |
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87 | unsigned char print_ctl; /* 0xFFF42037 */ |
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88 | unsigned char chip_speed; /* 0xFFF42038 */ |
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89 | unsigned char reserved7; |
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90 | unsigned char print_data; /* 0xFFF4203A */ |
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91 | unsigned char reserved8[3]; |
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92 | unsigned char int_level; /* 0xFFF4203E */ |
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93 | unsigned char int_mask; /* 0xFFF4203F */ |
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94 | } pccchip2_regs; |
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95 | |
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96 | /* |
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97 | * Base address of the PCCchip2. |
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98 | * This is not configurable in the MVME167. |
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99 | */ |
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100 | #define pccchip2 ((pccchip2_regs * const) 0xFFF42000) |
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101 | |
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102 | #endif |
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103 | /* |
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104 | * The MVME167 is equiped with one or two MEMC040 memory controllers at |
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105 | * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers |
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106 | * were initialized by 167Bug. |
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107 | */ |
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108 | typedef volatile struct memc040_regs_ { |
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109 | unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */ |
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110 | unsigned char reserved1[3]; |
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111 | unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */ |
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112 | unsigned char reserved2[3]; |
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113 | unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */ |
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114 | unsigned char reserved3[3]; |
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115 | unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */ |
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116 | unsigned char reserved4[3]; |
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117 | unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */ |
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118 | unsigned char reserved5[3]; |
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119 | unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */ |
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120 | unsigned char reserved6[3]; |
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121 | unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */ |
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122 | unsigned char reserved7[3]; |
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123 | unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */ |
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124 | } memc040_regs; |
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125 | |
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126 | /* |
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127 | * Base address of the MEMC040s. |
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128 | * This is not configurable in the MVME167. |
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129 | */ |
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130 | #define memc040_1 ((memc040_regs * const) 0xFFF43000) |
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131 | #define memc040_2 ((memc040_regs * const) 0xFFF43100) |
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132 | |
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133 | /* |
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134 | * The MVME167 may be equiped with error-correcting RAM cards. In this case, |
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135 | * each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port |
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136 | * assumes that these controllers, if present, are initialized by 167Bug. |
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137 | * They do not appear to hold information of interest at this time, so they |
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138 | * are not described. However, each MCECC pair lives at the same address as |
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139 | * the MEMC040 is replaces. The first eight registers of the MCECC are |
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140 | * nearly identical to the ones of the MEMC040, and the memc040_X structures |
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141 | * can be used to read those first eight registers. |
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142 | */ |
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143 | |
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144 | /* |
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145 | * Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller |
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146 | */ |
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147 | typedef volatile struct cd2401_regs_ { |
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148 | unsigned char reserved1[7]; |
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149 | unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */ |
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150 | unsigned char reserved2; |
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151 | unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */ |
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152 | unsigned char reserved3[6]; |
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153 | unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */ |
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154 | unsigned char ier; /* 0xFFF45011 - Interrupt Enable */ |
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155 | unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */ |
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156 | unsigned char ccr; /* 0xFFF45013 - Channel Command */ |
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157 | unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */ |
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158 | unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */ |
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159 | unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */ |
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160 | unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */ |
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161 | unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */ |
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162 | unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */ |
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163 | unsigned char csr; /* 0xFFF4501A - Channel Status */ |
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164 | unsigned char cmr; /* 0xFFF4501B - Channel Mode */ |
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165 | union { |
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166 | struct { |
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167 | unsigned char schr4; /* 0xFFF4501C - Special Character 4 */ |
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168 | unsigned char schr3; /* 0xFFF4501D - Special Character 3 */ |
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169 | unsigned char schr2; /* 0xFFF4501E - Special Character 2 */ |
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170 | unsigned char schr1; /* 0xFFF4501F - Special Character 1 */ |
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171 | } async; |
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172 | struct { |
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173 | unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */ |
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174 | unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */ |
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175 | unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */ |
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176 | unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */ |
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177 | } sync; |
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178 | } u1; |
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179 | unsigned char reserved4[2]; |
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180 | unsigned char scrh; /* 0xFFF45022 - Special Character Range High */ |
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181 | unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */ |
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182 | union { |
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183 | struct { |
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184 | unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */ |
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185 | } w; |
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186 | struct { |
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187 | unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */ |
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188 | unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */ |
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189 | } b; |
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190 | } u2; |
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191 | unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */ |
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192 | unsigned char reserved5[2]; |
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193 | union { |
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194 | struct { |
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195 | unsigned char ttr; /* 0xFFF45029 - Transmit Timer */ |
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196 | } async; |
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197 | struct { |
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198 | unsigned char gt2; /* 0xFFF45029 - General Timer 2 */ |
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199 | } sync; |
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200 | } u3; |
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201 | union { |
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202 | struct { |
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203 | unsigned short gt1; /* 0xFFF4502A - General Timer 1 */ |
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204 | } w; |
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205 | struct { |
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206 | unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */ |
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207 | unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */ |
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208 | } b; |
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209 | } u4; |
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210 | unsigned char reserved6[2]; |
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211 | unsigned char lnxt; /* 0xFF4502E - LNext Character */ |
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212 | unsigned char reserved7; |
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213 | unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */ |
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214 | unsigned char reserved8[7]; |
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215 | unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */ |
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216 | unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */ |
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217 | unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */ |
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218 | unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */ |
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219 | unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */ |
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220 | unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */ |
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221 | unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */ |
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222 | unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */ |
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223 | unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */ |
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224 | unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */ |
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225 | unsigned short reserved9; |
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226 | unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */ |
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227 | unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */ |
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228 | unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */ |
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229 | unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */ |
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230 | unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */ |
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231 | unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */ |
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232 | unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */ |
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233 | unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */ |
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234 | unsigned short reserved10; |
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235 | unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */ |
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236 | unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */ |
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237 | unsigned char reserved11[32]; |
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238 | unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */ |
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239 | unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */ |
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240 | unsigned char reserved12[2]; |
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241 | unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */ |
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242 | unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */ |
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243 | unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */ |
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244 | union { |
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245 | struct { |
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246 | unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */ |
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247 | } w; |
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248 | struct { |
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249 | unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */ |
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250 | unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */ |
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251 | } b; |
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252 | } u5; |
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253 | unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */ |
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254 | unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */ |
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255 | unsigned char reserved13[2]; |
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256 | unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */ |
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257 | unsigned char reserved14[49]; |
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258 | unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */ |
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259 | unsigned char reserved15[2]; |
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260 | unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */ |
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261 | unsigned char reserved16[4]; |
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262 | unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */ |
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263 | unsigned char reserved17[2]; |
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264 | unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */ |
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265 | unsigned char reserved18[10]; |
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266 | unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */ |
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267 | unsigned char reserved19[3]; |
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268 | unsigned char tpr; /* 0xFFF450DA - Timer Period */ |
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269 | unsigned char reserved20[3]; |
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270 | unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */ |
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271 | unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */ |
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272 | unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */ |
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273 | unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */ |
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274 | unsigned char stk; /* 0xFFF450E2 - Stack */ |
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275 | unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */ |
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276 | unsigned char reserved21[8]; |
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277 | unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */ |
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278 | unsigned char rir; /* 0xFFF450ED - Receive Interrupt */ |
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279 | unsigned char car; /* 0xFFF450EE - Channel Access */ |
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280 | unsigned char mir; /* 0xFFF450EF - Model Interrupt */ |
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281 | unsigned char reserved22[6]; |
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282 | unsigned char dmr; /* 0xFFF450F6 - DMA Mode */ |
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283 | unsigned char reserved23; |
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284 | unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */ |
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285 | } cd2401_regs; |
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286 | |
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287 | /* |
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288 | * Base address of the CD2401. |
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289 | * This is not configurable in the MVME167. |
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290 | */ |
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291 | #define cd2401 ((cd2401_regs * const) 0xFFF45000) |
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292 | |
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293 | /* CD2401 is clocked at 20 MHz */ |
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294 | #define CD2401_CLK_RATE 20000000 |
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295 | |
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296 | /* BSP-wide functions */ |
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297 | |
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298 | rtems_isr_entry set_vector( |
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299 | rtems_isr_entry handler, |
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300 | rtems_vector_number vector, |
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301 | int type |
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302 | ); |
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303 | |
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304 | #ifdef M167_INIT |
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305 | #undef EXTERN |
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306 | #define EXTERN |
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307 | #else |
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308 | #undef EXTERN |
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309 | #define EXTERN extern |
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310 | #endif |
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311 | |
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312 | extern void *M68Kvec[]; /* vector table address */ |
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313 | |
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314 | #ifdef __cplusplus |
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315 | } |
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316 | #endif |
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317 | |
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318 | #endif |
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