[88867e89] | 1 | /* |
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[ac7d5ef0] | 2 | * This routine initializes the Tick Timer 2 on the MVME162 board. |
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| 3 | * The tick frequency is 1 millisecond. |
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[88867e89] | 4 | */ |
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| 5 | |
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| 6 | /* |
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[08311cc3] | 7 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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[98e4ebf5] | 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[ac7d5ef0] | 13 | * |
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| 14 | * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. |
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| 15 | * EISCAT Scientific Association. M.Savitski |
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| 16 | * |
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| 17 | * This material is a part of the MVME162 Board Support Package |
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| 18 | * for the RTEMS executive. Its licensing policies are those of the |
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| 19 | * RTEMS above. |
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| 20 | */ |
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| 21 | |
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| 22 | #include <stdlib.h> |
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| 23 | |
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| 24 | #include <bsp.h> |
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[f6c92120] | 25 | #include <rtems/clockdrv.h> |
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[ac7d5ef0] | 26 | |
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| 27 | #define MS_COUNT 1000 /* T2's countdown constant (1 ms) */ |
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[c6fb8e90] | 28 | #define CLOCK_INT_LEVEL 6 /* T2's interrupt level */ |
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[ac7d5ef0] | 29 | |
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[629e12a] | 30 | uint32_t Clock_isrs; /* ISRs until next tick */ |
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| 31 | volatile uint32_t Clock_driver_ticks; /* ticks since initialization */ |
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[ac7d5ef0] | 32 | rtems_isr_entry Old_ticker; |
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| 33 | |
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[3a4ae6c] | 34 | void Clock_exit( void ); |
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[6128a4a] | 35 | |
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[3a4ae6c] | 36 | #define CLOCK_VECTOR (VBR0 * 0x10 + 0x9) |
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[6128a4a] | 37 | |
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[3a4ae6c] | 38 | /* |
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| 39 | * ISR Handler |
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| 40 | */ |
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[88867e89] | 41 | static rtems_isr Clock_isr(rtems_vector_number vector) |
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[ac7d5ef0] | 42 | { |
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[3a4ae6c] | 43 | Clock_driver_ticks += 1; |
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| 44 | lcsr->timer_cnt_2 = 0; /* clear counter */ |
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| 45 | lcsr->intr_clear |= 0x02000000; |
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[ac7d5ef0] | 46 | |
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[3a4ae6c] | 47 | if ( Clock_isrs == 1 ) { |
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| 48 | rtems_clock_tick(); |
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[12bd47e] | 49 | Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000; |
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[3a4ae6c] | 50 | } |
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[6128a4a] | 51 | else |
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[3a4ae6c] | 52 | Clock_isrs -= 1; |
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[ac7d5ef0] | 53 | } |
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| 54 | |
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[88867e89] | 55 | static void Install_clock(rtems_isr_entry clock_isr ) |
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[ac7d5ef0] | 56 | { |
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| 57 | |
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| 58 | Clock_driver_ticks = 0; |
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[12bd47e] | 59 | Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000; |
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[ac7d5ef0] | 60 | |
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[0dd1d44] | 61 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); |
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| 62 | lcsr->vector_base |= MASK_INT; /* unmask VMEchip2 interrupts */ |
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| 63 | lcsr->to_ctl = 0xE7; /* prescaler to 1 MHz (see Appendix A1) */ |
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| 64 | lcsr->timer_cmp_2 = MS_COUNT; |
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| 65 | lcsr->timer_cnt_2 = 0; /* clear counter */ |
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| 66 | lcsr->board_ctl |= 0x700; /* increment, reset-on-compare, and */ |
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| 67 | /* clear-overflow-cnt */ |
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[ac7d5ef0] | 68 | |
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[0dd1d44] | 69 | lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10; /* set int level */ |
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| 70 | lcsr->intr_ena |= 0x02000000; /* enable tick timer 2 interrupt */ |
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[ac7d5ef0] | 71 | |
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[0dd1d44] | 72 | atexit( Clock_exit ); |
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[3a4ae6c] | 73 | } |
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[ac7d5ef0] | 74 | |
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| 75 | void Clock_exit( void ) |
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| 76 | { |
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| 77 | /* Dummy for now. See other m68k BSP's for code examples */ |
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| 78 | } |
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[3a4ae6c] | 79 | |
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| 80 | rtems_device_driver Clock_initialize( |
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| 81 | rtems_device_major_number major, |
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| 82 | rtems_device_minor_number minor, |
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| 83 | void *pargp |
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| 84 | ) |
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| 85 | { |
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| 86 | Install_clock( Clock_isr ); |
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[6128a4a] | 87 | |
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[3a4ae6c] | 88 | return RTEMS_SUCCESSFUL; |
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| 89 | } |
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