source: rtems/bsps/m68k/mcf5329/start/cfinit.c @ ff081aee

Last change on this file since ff081aee was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 23.3 KB
Line 
1/*********************************************************************
2* Initialisation Code for ColdFire MCF5329 Processor                 *
3**********************************************************************
4 Generated by ColdFire Initialisation Utility 2.10.8
5 Wed Jul 02 14:26:25 2008
6
7 MicroAPL Ltd makes no warranties in respect of the suitability
8 of this code for any particular purpose, and accepts
9 no liability for any loss arising out of its use. The person or
10 persons making use of this file must make the final evaluation
11 as to its suitability and correctness for a particular application.
12
13*/
14
15/* External reference frequency is 16.0000 MHz
16 Internal bus clock frequency = 80.00 MHz
17 Processor core frequency = 240.00 MHz
18*/
19
20#include <bsp.h>
21
22/* eDMA Transfer Control Descriptor definitions */
23#define  MCF_EDMA_TCD_W0(channel)            (*(vuint32 *)(0xFC045000+((channel)*0x20)))        /* Transfer Control Descriptor Word 0 */
24#define  MCF_EDMA_TCD_W1(channel)            (*(vuint32 *)(0xFC045004+((channel)*0x20)))        /* Transfer Control Descriptor Word 1 */
25#define  MCF_EDMA_TCD_W2(channel)            (*(vuint32 *)(0xFC045008+((channel)*0x20)))        /* Transfer Control Descriptor Word 2 */
26#define  MCF_EDMA_TCD_W3(channel)            (*(vuint32 *)(0xFC04500C+((channel)*0x20)))        /* Transfer Control Descriptor Word 3 */
27#define  MCF_EDMA_TCD_W4(channel)            (*(vuint32 *)(0xFC045010+((channel)*0x20)))        /* Transfer Control Descriptor Word 4 */
28#define  MCF_EDMA_TCD_W5(channel)            (*(vuint32 *)(0xFC045014+((channel)*0x20)))        /* Transfer Control Descriptor Word 5 */
29#define  MCF_EDMA_TCD_W6(channel)            (*(vuint32 *)(0xFC045018+((channel)*0x20)))        /* Transfer Control Descriptor Word 6 */
30#define  MCF_EDMA_TCD_W7(channel)            (*(vuint32 *)(0xFC04501C+((channel)*0x20)))        /* Transfer Control Descriptor Word 7 */
31
32/* Function prototypes */
33void init_main(void);
34static void disable_interrupts(void);
35static void disable_watchdog_timer(void);
36static void disable_cache(void);
37extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
38static void init_cache(void);
39static void init_crossbar(void);
40extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
41static void init_eport(void);
42static void init_flexcan(void);
43static void init_dma_timers(void);
44static void init_interrupt_timers(void);
45static void init_real_time_clock(void);
46static void init_watchdog_timers(void);
47static void init_edma(void);
48static void init_pin_assignments(void);
49extern void init_sdram_controller(void)
50  __attribute__ ((section(".ram_code")));
51static void init_interrupt_controller(void);
52
53/*********************************************************************
54* init_main - Main entry point for initialisation code               *
55**********************************************************************/
56void init_main(void)
57{
58  init_clock_config();
59
60  /* Disable interrupts, watchdog timer, cache */
61  disable_interrupts();
62  disable_watchdog_timer();
63  disable_cache();
64
65  /* Initialise individual modules */
66  init_cache();
67  init_crossbar();
68  init_chip_selects();
69  init_eport();
70  init_flexcan();
71  init_dma_timers();
72  init_interrupt_timers();
73  init_real_time_clock();
74  init_watchdog_timers();
75  init_edma();
76  init_pin_assignments();
77
78  /* Initialise SDRAM controller (must be done after pin assignments) */
79  init_sdram_controller();
80
81  /* Initialise interrupt controller */
82  init_interrupt_controller();
83}
84
85/*********************************************************************
86* disable_interrupts - Disable all interrupt sources                 *
87**********************************************************************/
88static void disable_interrupts(void)
89{
90  vuint8 *p;
91  int i;
92
93  /* Set ICR001-ICR063 to 0x0 */
94  p = (vuint8 *) & MCF_INTC0_ICR1;
95  for (i = 1; i <= 63; i++)
96    *p++ = 0x0;
97
98  /* Set ICR100-ICR163 to 0x0 */
99  p = (vuint8 *) & MCF_INTC1_ICR0;
100  for (i = 100; i <= 163; i++)
101    *p++ = 0x0;
102}
103
104/*********************************************************************
105* disable_watchdog_timer - Disable system watchdog timer             *
106**********************************************************************/
107static void disable_watchdog_timer(void)
108{
109  /* Disable Core Watchdog Timer */
110  MCF_SCM_CWCR = 0;
111}
112
113/*********************************************************************
114* disable_cache - Disable and invalidate cache                       *
115**********************************************************************/
116static void disable_cache(void)
117{
118  __asm__ ("move.l   #0x01000000,%d0");
119  __asm__ ("movec    %d0,%CACR");
120}
121
122/*********************************************************************
123* init_clock_config - Clock Module                                   *
124**********************************************************************/
125void init_clock_config(void)
126{
127  /* Clock module uses normal PLL mode with 16.0000 MHz external reference
128     Bus clock frequency = 80.00 MHz
129     Processor clock frequency = 3 x bus clock = 240.00 MHz
130     Dithering disabled
131   */
132
133  /* Check to see if the SDRAM has already been initialized
134     by a run control tool. If it has, put SDRAM into self-refresh mode before
135     initializing the PLL
136   */
137  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
138    MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
139
140  /* Temporarily switch to LIMP mode
141     NOTE: Ensure that this code is not executing from SDRAM, since the
142     SDRAM Controller is disabled in LIMP mode
143   */
144  MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
145  MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
146
147  /* Configure the PLL settings */
148  MCF_PLL_PODR = MCF_PLL_PODR_CPUDIV(0x2) | MCF_PLL_PODR_BUSDIV(0x6);
149  MCF_PLL_PFDR = MCF_PLL_PFDR_MFD(0x78);
150  MCF_PLL_PLLCR = 0;
151  MCF_PLL_PMDR = 0;
152
153  /* Enable PLL and wait for lock */
154  MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
155  while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
156
157  /* From the Device Errata:
158
159     "After exiting LIMP mode, the value of 0x40000000 should be written
160     to address 0xFC0B8080 before attempting to initialize the SDRAMC
161     or exit the SDRAM from self-refresh mode."
162   */
163  *(vuint32 *) 0xfc0b8080 = 0x40000000;
164
165  /* If we put the SDRAM into self-refresh mode earlier, restore mode now */
166  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
167    MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
168}
169
170/*********************************************************************
171* init_cache - Unified (Instruction and Data) Cache                  *
172**********************************************************************/
173static void init_cache(void)
174{
175  /* ACR0: Cache accesses to 32 MB memory region at address $40000000
176     CACR: Don't cache accesses to the rest of memory
177   */
178  /*
179   * Cache is enabled in bspstart.c
180   */
181#if 0
182  __asm__ ("move.l   #0xa0000600,%d0");
183  __asm__ ("movec    %d0,%CACR");
184#endif
185  __asm__ ("move.l   #0x4001c020,%d0");
186  __asm__ ("movec    %d0,%ACR0");
187  __asm__ ("move.l   #0x00000000,%d0");
188  __asm__ ("movec    %d0,%ACR1");
189}
190
191/*********************************************************************
192* init_crossbar - Cross-Bar Switch (XBS) Module                      *
193**********************************************************************/
194static void init_crossbar(void)
195{
196  /* XBS settings for FlexBus/SDRAM Controller slave:
197     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
198   */
199  MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
200    MCF_XBS_PRS_M5(0x4) |
201    MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
202  MCF_XBS_CRS1 = 0;
203
204  /* XBS settings for SRAM Backdoor slave:
205     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
206   */
207  MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
208    MCF_XBS_PRS_M5(0x4) |
209    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
210  MCF_XBS_CRS4 = 0;
211
212  /* XBS settings for Cryptography Modules slave:
213     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
214   */
215  MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
216    MCF_XBS_PRS_M5(0x4) |
217    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
218  MCF_XBS_CRS6 = 0;
219
220  /* XBS settings for On-chip Peripherals slave:
221     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
222   */
223  MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
224    MCF_XBS_PRS_M5(0x4) |
225    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
226  MCF_XBS_CRS7 = 0;
227}
228
229/*********************************************************************
230* init_chip_selects - Chip Select Module (FlexBus)                   *
231**********************************************************************/
232void init_chip_selects(void)
233{
234  /* Chip Select 1 disabled (CSMR1[V] = 0) */
235  MCF_FBCS1_CSMR = 0;
236
237  /* Chip Select 2 disabled (CSMR2[V] = 0) */
238  MCF_FBCS2_CSMR = 0;
239
240  /* Chip Select 3 disabled (CSMR3[V] = 0) */
241  MCF_FBCS3_CSMR = 0;
242
243  /* Chip Select 4 disabled (CSMR4[V] = 0) */
244  MCF_FBCS4_CSMR = 0;
245
246  /* Chip Select 5 disabled (CSMR5[V] = 0) */
247  MCF_FBCS5_CSMR = 0;
248
249  /* Chip Select 0: 2 MB of Flash at base address $00000000
250     Port size = 16 bits
251     Assert chip select on first rising clock edge after address is asserted
252     Generate internal transfer acknowledge after 7 wait states
253     Address is held for 1 clock at end of read and write cycles
254   */
255  MCF_FBCS0_CSAR = 0;
256  MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
257    (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
258  MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
259}
260
261/*********************************************************************
262* init_eport - Edge Port Module (EPORT)                              *
263**********************************************************************/
264static void init_eport(void)
265{
266  /* Pins 1-7 configured as GPIO inputs */
267  MCF_EPORT_EPPAR = 0;
268  MCF_EPORT_EPDDR = 0;
269  MCF_EPORT_EPIER = 0;
270}
271
272/*********************************************************************
273* init_flexcan - FlexCAN Module                                      *
274**********************************************************************/
275static void init_flexcan(void)
276{
277  /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
278  MCF_CAN_IMASK = 0;
279  MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
280  MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
281  MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
282  MCF_CAN_CANCTRL = 0;
283  MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
284    MCF_CAN_CANMCR_FRZ |
285    MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
286}
287
288/*********************************************************************
289* init_sdram_controller - SDRAM Controller                           *
290**********************************************************************/
291void init_sdram_controller(void)
292{
293  /* Check to see if the SDRAM has already been initialized
294     by a run control tool and skip if so
295   */
296  if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
297    return;
298
299  /* Ensure that there is a delay from processor reset of the time recommended in
300     the SDRAM data sheet (typically 100-200 microseconds) until the following
301     code so that the SDRAM is ready for commands...
302   */
303
304  /* SDRAM controller configured for Double-data rate (DDR) SDRAM
305     Bus width = 16 bits
306     SDRAM specification:
307     SDRAM clock frequency = 80.00 MHz
308     CASL = 2.5
309     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
310     Write recovery time, tWR = 15.0 nanoseconds
311     Precharge comand to ACTV command, tRP = 20.0 nanoseconds
312     Auto refresh command period, tRFC = 75.0 nanoseconds
313     Average periodic refresh interval, tREFI = 7.8 microseconds
314   */
315
316  /* Memory block 0 enabled - 32 MBytes at address $40000000
317     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
318   */
319  MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
320
321  /* Memory block 1 disabled */
322  MCF_SDRAMC_SDCS1 = 0;
323
324  /* Initialise SDCFG1 register with delay and timing values
325     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
326     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
327   */
328  MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
329    MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
330    MCF_SDRAMC_SDCFG1_RDLAT(0x7) |
331    MCF_SDRAMC_SDCFG1_ACT2RW(0x2) |
332    MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
333    MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
334
335  /* Initialise SDCFG2 register with delay and timing values
336     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
337   */
338  MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
339    MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
340    MCF_SDRAMC_SDCFG2_BRD2WT(0x6) | MCF_SDRAMC_SDCFG2_BL(0x7);
341
342  /* Issue a Precharge All command */
343  MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN |
344    MCF_SDRAMC_SDCR_CKE |
345    MCF_SDRAMC_SDCR_DDR |
346    MCF_SDRAMC_SDCR_MUX(0x1) |
347    MCF_SDRAMC_SDCR_RCNT(0x8) | MCF_SDRAMC_SDCR_PS_16 | MCF_SDRAMC_SDCR_IPALL;
348
349  /* Write Extended Mode Register */
350  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_CMD;
351
352  /* Write Mode Register and Reset DLL */
353  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
354    MCF_SDRAMC_SDMR_AD(0x163) | MCF_SDRAMC_SDMR_CMD;
355
356  /* Insert code here to pause for DLL lock time specified by memory... */
357
358  /* Issue a second Precharge All command */
359  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
360
361  /* Refresh sequence...
362     (check the number of refreshes required by the SDRAM manufacturer)
363   */
364  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
365  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
366
367  /* Write Mode Register and clear the Reset DLL bit */
368  MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
369    MCF_SDRAMC_SDMR_AD(0x63) | MCF_SDRAMC_SDMR_CMD;
370
371  /* Enable automatic refresh and lock SDMR */
372  MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
373  MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_REF |
374    MCF_SDRAMC_SDCR_DQS_OE(0x8) | MCF_SDRAMC_SDCR_DQS_OE(0x4);
375
376}
377
378/*********************************************************************
379* init_dma_timers - DMA Timers                                       *
380**********************************************************************/
381static void init_dma_timers(void)
382{
383  /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
384  MCF_DTIM0_DTMR = 0;
385  MCF_DTIM0_DTXMR = 0;
386  MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
387
388  /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
389  MCF_DTIM1_DTMR = 0;
390  MCF_DTIM1_DTXMR = 0;
391  MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
392
393  /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
394  MCF_DTIM2_DTMR = 0;
395  MCF_DTIM2_DTXMR = 0;
396  MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
397
398  /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
399  MCF_DTIM3_DTMR = 0;
400  MCF_DTIM3_DTXMR = 0;
401  MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
402}
403
404/*********************************************************************
405* init_interrupt_timers - Programmable Interrupt Timers (PIT)        *
406**********************************************************************/
407static void init_interrupt_timers(void)
408{
409  /* PIT0 disabled (PCSR0[EN]=0) */
410  MCF_PIT0_PCSR = 0;
411
412  /* PIT1 disabled (PCSR1[EN]=0) */
413  MCF_PIT1_PCSR = 0;
414
415  /* PIT2 disabled (PCSR2[EN]=0) */
416  MCF_PIT2_PCSR = 0;
417
418  /* PIT3 disabled (PCSR3[EN]=0) */
419  MCF_PIT3_PCSR = 0;
420}
421
422/*********************************************************************
423* init_real_time_clock - Real-Time Clock (RTC)                       *
424**********************************************************************/
425static void init_real_time_clock(void)
426{
427  /* Disable the RTC */
428  MCF_RTC_CR = 0;
429}
430
431/*********************************************************************
432* init_watchdog_timers - Watchdog Timers                             *
433**********************************************************************/
434static void init_watchdog_timers(void)
435{
436  /* Watchdog Timer disabled (WCR[EN]=0)
437     NOTE: WCR and WMR cannot be written again until after the
438     processor is reset.
439   */
440  MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
441  MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
442
443  /* Core watchdog timer disabled */
444  MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
445}
446
447/*********************************************************************
448* init_edma - eDMA Controller                                        *
449**********************************************************************/
450static void init_edma(void)
451{
452  /* Associate eDMA channels 9-12 with SSI signals */
453  MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
454
455  /* Configured for round-robin arbitration mode */
456  MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
457
458  /* All error interrupts are disabled */
459  MCF_EDMA_EEI = 0;
460
461  /* All DMA requests from peripherals are masked */
462  MCF_EDMA_ERQ = 0;
463}
464
465/*********************************************************************
466* init_interrupt_controller - Interrupt Controller                   *
467**********************************************************************/
468static void init_interrupt_controller(void)
469{
470  /* No interrupt sources configured */
471  MCF_INTC1_ICR0 = 0;
472  MCF_INTC1_ICR1 = 0;
473  MCF_INTC1_ICR3 = 0;
474  MCF_INTC1_ICR4 = 0;
475  MCF_INTC1_ICR5 = 0;
476  MCF_INTC1_ICR6 = 0;
477  MCF_INTC1_ICR7 = 0;
478  MCF_INTC1_ICR8 = 0;
479  MCF_INTC1_ICR9 = 0;
480  MCF_INTC1_ICR10 = 0;
481  MCF_INTC1_ICR11 = 0;
482  MCF_INTC1_ICR12 = 0;
483  MCF_INTC1_ICR13 = 0;
484  MCF_INTC1_ICR14 = 0;
485  MCF_INTC1_ICR15 = 0;
486  MCF_INTC1_ICR16 = 0;
487  MCF_INTC1_ICR17 = 0;
488  MCF_INTC1_ICR18 = 0;
489  MCF_INTC1_ICR19 = 0;
490  MCF_INTC1_ICR40 = 0;
491  MCF_INTC1_ICR41 = 0;
492  MCF_INTC1_ICR42 = 0;
493  MCF_INTC1_ICR43 = 0;
494  MCF_INTC1_ICR44 = 0;
495  MCF_INTC1_ICR45 = 0;
496  MCF_INTC1_ICR46 = 0;
497  MCF_INTC1_ICR47 = 0;
498  MCF_INTC1_ICR48 = 0;
499  MCF_INTC1_ICR49 = 0;
500  MCF_INTC1_ICR50 = 0;
501  MCF_INTC1_ICR51 = 0;
502  MCF_INTC1_ICR52 = 0;
503  MCF_INTC1_ICR53 = 0;
504  MCF_INTC0_ICR1 = 0;
505  MCF_INTC0_ICR2 = 0;
506  MCF_INTC0_ICR3 = 0;
507  MCF_INTC0_ICR4 = 0;
508  MCF_INTC0_ICR5 = 0;
509  MCF_INTC0_ICR6 = 0;
510  MCF_INTC0_ICR7 = 0;
511  MCF_INTC0_ICR8 = 0;
512  MCF_INTC0_ICR9 = 0;
513  MCF_INTC0_ICR10 = 0;
514  MCF_INTC0_ICR11 = 0;
515  MCF_INTC0_ICR12 = 0;
516  MCF_INTC0_ICR13 = 0;
517  MCF_INTC0_ICR14 = 0;
518  MCF_INTC0_ICR15 = 0;
519  MCF_INTC0_ICR16 = 0;
520  MCF_INTC0_ICR17 = 0;
521  MCF_INTC0_ICR18 = 0;
522  MCF_INTC0_ICR19 = 0;
523  MCF_INTC0_ICR20 = 0;
524  MCF_INTC0_ICR21 = 0;
525  MCF_INTC0_ICR22 = 0;
526  MCF_INTC0_ICR23 = 0;
527  MCF_INTC0_ICR24 = 0;
528  MCF_INTC0_ICR25 = 0;
529  MCF_INTC0_ICR26 = 0;
530  MCF_INTC0_ICR27 = 0;
531  MCF_INTC0_ICR28 = 0;
532  MCF_INTC0_ICR30 = 0;
533  MCF_INTC0_ICR31 = 0;
534  MCF_INTC0_ICR32 = 0;
535  MCF_INTC0_ICR33 = 0;
536  MCF_INTC0_ICR34 = 0;
537  MCF_INTC0_ICR35 = 0;
538  MCF_INTC0_ICR36 = 0;
539  MCF_INTC0_ICR37 = 0;
540  MCF_INTC0_ICR38 = 0;
541  MCF_INTC0_ICR39 = 0;
542  MCF_INTC0_ICR40 = 0;
543  MCF_INTC0_ICR41 = 0;
544  MCF_INTC0_ICR42 = 0;
545  MCF_INTC0_ICR43 = 0;
546  MCF_INTC0_ICR44 = 0;
547  MCF_INTC0_ICR45 = 0;
548  MCF_INTC0_ICR46 = 0;
549  MCF_INTC0_ICR47 = 0;
550  MCF_INTC0_ICR48 = 0;
551  MCF_INTC0_ICR62 = 0;
552  MCF_INTC0_IMRH = 0xffffffff;
553  MCF_INTC0_IMRL = 0xffffffff;
554  MCF_INTC1_IMRH = 0xffffffff;
555  MCF_INTC1_IMRL = 0xffffffff;
556}
557
558/*********************************************************************
559* init_pin_assignments - Pin Assignment and General Purpose I/O      *
560**********************************************************************/
561static void init_pin_assignments(void)
562{
563  /* Pin assignments for port BUSCTL
564     Pin BUSCTL3 : External bus output enable, /OE
565     Pin BUSCTL2 : External bus transfer acknowledge, /TA
566     Pin BUSCTL1 : External bus read/write, R/W
567     Pin BUSCTL0 : External bus transfer start, /TS
568   */
569  MCF_GPIO_PDDR_BUSCTL = 0;
570  MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
571    MCF_GPIO_PAR_BUSCTL_PAR_TA |
572    MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
573
574  /* Pin assignments for port BE
575     Pin BE3 : External bus byte enable BW/BWE3
576     Pin BE2 : External bus byte enable BW/BWE2
577     Pin BE1 : External bus byte enable BW/BWE1
578     Pin BE0 : External bus byte enable BW/BWE0
579   */
580  MCF_GPIO_PDDR_BE = 0;
581  MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 |
582    MCF_GPIO_PAR_BE_PAR_BE2 |
583    MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
584
585  /* Pin assignments for port CS
586     Pin CS5 : Flex bus chip select /FB_CS5
587     Pin CS4 : Flex bus chip select /FB_CS4
588     Pin CS3 : Flex bus chip select /FB_CS3
589     Pin CS2 : Flex bus chip select /FB_CS2
590     Pin CS1 : Flex bus chip select /FB_CS1
591   */
592  MCF_GPIO_PDDR_CS = 0;
593  MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 |
594    MCF_GPIO_PAR_CS_PAR_CS4 |
595    MCF_GPIO_PAR_CS_PAR_CS3 |
596    MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
597
598  /* Pin assignments for port FECI2C
599     Pin FECI2C3 : FEC management data clock, FEC_MDC
600     Pin FECI2C2 : FEC management data, FEC_MDIO
601     Pin FECI2C1 : GPIO input
602     Pin FECI2C0 : GPIO input
603   */
604  MCF_GPIO_PDDR_FECI2C = 0;
605  MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) |
606    MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
607
608  /* Pin assignments for ports FECH and FECL
609     Pin FECH7 : FEC transmit clock, FEC_TXCLK
610     Pin FECH6 : FEC transmit enable, FEC_TXEN
611     Pin FECH5 : FEC transmit data 0, FEC_TXD0
612     Pin FECH4 : FEC collision, FEC_COL
613     Pin FECH3 : FEC receive clock, FEC_RXCLK
614     Pin FECH2 : FEC receive data valid, FEC_RXDV
615     Pin FECH1 : FEC receive data 0, FEC_RXD0
616     Pin FECH0 : FEC carrier receive sense, FEC_CRS
617     Pin FECL7 : FEC transmit data 3, FEC_TXD3
618     Pin FECL6 : FEC transmit data 2, FEC_TXD2
619     Pin FECL5 : FEC transmit data 1, FEC_TXD1
620     Pin FECL4 : FEC transmit error, FEC_TXER
621     Pin FECL3 : FEC receive data 3, FEX_RXD3
622     Pin FECL2 : FEC receive data 2, FEX_RXD2
623     Pin FECL1 : FEC receive data 1, FEX_RXD1
624     Pin FECL0 : FEC receive error, FEC_RXER
625   */
626  MCF_GPIO_PDDR_FECH = 0;
627  MCF_GPIO_PDDR_FECL = 0;
628  MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) |
629    MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
630
631  /* Pin assignments for port IRQ
632     Pins are all used for EdgePort GPIO/IRQ
633   */
634  MCF_GPIO_PAR_IRQ = 0;
635
636  /* Pin assignments for port LCDDATAH
637     Pins are all GPIO inputs
638   */
639  MCF_GPIO_PDDR_LCDDATAH = 0;
640  MCF_GPIO_PAR_LCDDATA = 0;
641
642  /* Pin assignments for port LCDDATAM
643     Port LCDDATAM pins are all GPIO inputs
644   */
645  MCF_GPIO_PDDR_LCDDATAM = 0;
646
647  /* Pin assignments for port LCDDATAL
648     Port LCDDATAL pins are all GPIO inputs
649   */
650  MCF_GPIO_PDDR_LCDDATAL = 0;
651
652  /* Pin assignments for port LCDCTLH
653     Pins are all GPIO inputs
654   */
655  MCF_GPIO_PDDR_LCDCTLH = 0;
656  MCF_GPIO_PAR_LCDCTL = 0;
657
658  /* Pin assignments for port LCDCTLL
659     Pins are all GPIO inputs
660   */
661  MCF_GPIO_PDDR_LCDCTLL = 0;
662
663  /* Pin assignments for port PWM
664     Pins are all GPIO inputs
665   */
666  MCF_GPIO_PDDR_PWM = 0;
667  MCF_GPIO_PAR_PWM = 0;
668
669  /* Pin assignments for port QSPI
670     Pins are all GPIO inputs
671   */
672  MCF_GPIO_PDDR_QSPI = 0;
673  MCF_GPIO_PAR_QSPI = 0;
674
675  /* Pin assignments for port SSI
676     Pins are all GPIO inputs
677   */
678  MCF_GPIO_PDDR_SSI = 0;
679  MCF_GPIO_PAR_SSI = 0;
680
681  /* Pin assignments for port TIMER
682     Pins are all GPIO outputs
683   */
684  MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
685    MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 |
686    MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
687  MCF_GPIO_PAR_TIMER = 0;
688
689  /* Pin assignments for port UART
690     Pin UART7 : UART 1 clear-to-send, /U1CTS
691     Pin UART6 : UART 1 request-to-send, /U1RTS
692     Pin UART5 : UART 1 transmit data, U1TXD
693     Pin UART4 : UART 1 receive data, U1RXD
694     Pin UART3 : UART 0 clear-to-send, /U0CTS
695     Pin UART2 : UART 0 request-to-send, /U0RTS
696     Pin UART1 : UART 0 transmit data, U0TXD
697     Pin UART0 : UART 0 receive data, U0RXD
698   */
699  MCF_GPIO_PDDR_UART = 0;
700  MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) |
701    MCF_GPIO_PAR_UART_PAR_URTS1(0x3) |
702    MCF_GPIO_PAR_UART_PAR_URXD1(0x3) |
703    MCF_GPIO_PAR_UART_PAR_UTXD1(0x3) |
704    MCF_GPIO_PAR_UART_PAR_UCTS0 |
705    MCF_GPIO_PAR_UART_PAR_URTS0 |
706    MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0;
707}
Note: See TracBrowser for help on using the repository browser.