1 | /********************************************************************* |
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2 | * Initialisation Code for ColdFire MCF5329 Processor * |
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3 | ********************************************************************** |
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4 | Generated by ColdFire Initialisation Utility 2.10.8 |
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5 | Wed Jul 02 14:26:25 2008 |
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6 | |
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7 | MicroAPL Ltd makes no warranties in respect of the suitability |
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8 | of this code for any particular purpose, and accepts |
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9 | no liability for any loss arising out of its use. The person or |
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10 | persons making use of this file must make the final evaluation |
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11 | as to its suitability and correctness for a particular application. |
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12 | |
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13 | */ |
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14 | |
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15 | /* External reference frequency is 16.0000 MHz |
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16 | Internal bus clock frequency = 80.00 MHz |
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17 | Processor core frequency = 240.00 MHz |
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18 | */ |
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19 | |
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20 | #include <bsp.h> |
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21 | |
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22 | /* eDMA Transfer Control Descriptor definitions */ |
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23 | #define MCF_EDMA_TCD_W0(channel) (*(vuint32 *)(0xFC045000+((channel)*0x20))) /* Transfer Control Descriptor Word 0 */ |
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24 | #define MCF_EDMA_TCD_W1(channel) (*(vuint32 *)(0xFC045004+((channel)*0x20))) /* Transfer Control Descriptor Word 1 */ |
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25 | #define MCF_EDMA_TCD_W2(channel) (*(vuint32 *)(0xFC045008+((channel)*0x20))) /* Transfer Control Descriptor Word 2 */ |
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26 | #define MCF_EDMA_TCD_W3(channel) (*(vuint32 *)(0xFC04500C+((channel)*0x20))) /* Transfer Control Descriptor Word 3 */ |
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27 | #define MCF_EDMA_TCD_W4(channel) (*(vuint32 *)(0xFC045010+((channel)*0x20))) /* Transfer Control Descriptor Word 4 */ |
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28 | #define MCF_EDMA_TCD_W5(channel) (*(vuint32 *)(0xFC045014+((channel)*0x20))) /* Transfer Control Descriptor Word 5 */ |
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29 | #define MCF_EDMA_TCD_W6(channel) (*(vuint32 *)(0xFC045018+((channel)*0x20))) /* Transfer Control Descriptor Word 6 */ |
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30 | #define MCF_EDMA_TCD_W7(channel) (*(vuint32 *)(0xFC04501C+((channel)*0x20))) /* Transfer Control Descriptor Word 7 */ |
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31 | |
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32 | /* Function prototypes */ |
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33 | void init_main(void); |
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34 | static void disable_interrupts(void); |
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35 | static void disable_watchdog_timer(void); |
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36 | static void disable_cache(void); |
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37 | extern void init_clock_config(void) __attribute__ ((section(".ram_code"))); |
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38 | static void init_cache(void); |
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39 | static void init_crossbar(void); |
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40 | extern void init_chip_selects(void) __attribute__ ((section(".ram_code"))); |
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41 | static void init_eport(void); |
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42 | static void init_flexcan(void); |
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43 | static void init_dma_timers(void); |
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44 | static void init_interrupt_timers(void); |
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45 | static void init_real_time_clock(void); |
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46 | static void init_watchdog_timers(void); |
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47 | static void init_edma(void); |
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48 | static void init_pin_assignments(void); |
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49 | extern void init_sdram_controller(void) |
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50 | __attribute__ ((section(".ram_code"))); |
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51 | static void init_interrupt_controller(void); |
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52 | |
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53 | /********************************************************************* |
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54 | * init_main - Main entry point for initialisation code * |
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55 | **********************************************************************/ |
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56 | void init_main(void) |
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57 | { |
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58 | init_clock_config(); |
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59 | |
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60 | /* Disable interrupts, watchdog timer, cache */ |
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61 | disable_interrupts(); |
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62 | disable_watchdog_timer(); |
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63 | disable_cache(); |
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64 | |
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65 | /* Initialise individual modules */ |
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66 | init_cache(); |
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67 | init_crossbar(); |
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68 | init_chip_selects(); |
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69 | init_eport(); |
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70 | init_flexcan(); |
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71 | init_dma_timers(); |
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72 | init_interrupt_timers(); |
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73 | init_real_time_clock(); |
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74 | init_watchdog_timers(); |
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75 | init_edma(); |
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76 | init_pin_assignments(); |
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77 | |
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78 | /* Initialise SDRAM controller (must be done after pin assignments) */ |
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79 | init_sdram_controller(); |
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80 | |
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81 | /* Initialise interrupt controller */ |
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82 | init_interrupt_controller(); |
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83 | } |
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84 | |
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85 | /********************************************************************* |
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86 | * disable_interrupts - Disable all interrupt sources * |
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87 | **********************************************************************/ |
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88 | static void disable_interrupts(void) |
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89 | { |
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90 | vuint8 *p; |
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91 | int i; |
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92 | |
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93 | /* Set ICR001-ICR063 to 0x0 */ |
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94 | p = (vuint8 *) & MCF_INTC0_ICR1; |
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95 | for (i = 1; i <= 63; i++) |
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96 | *p++ = 0x0; |
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97 | |
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98 | /* Set ICR100-ICR163 to 0x0 */ |
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99 | p = (vuint8 *) & MCF_INTC1_ICR0; |
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100 | for (i = 100; i <= 163; i++) |
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101 | *p++ = 0x0; |
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102 | } |
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103 | |
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104 | /********************************************************************* |
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105 | * disable_watchdog_timer - Disable system watchdog timer * |
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106 | **********************************************************************/ |
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107 | static void disable_watchdog_timer(void) |
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108 | { |
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109 | /* Disable Core Watchdog Timer */ |
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110 | MCF_SCM_CWCR = 0; |
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111 | } |
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112 | |
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113 | /********************************************************************* |
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114 | * disable_cache - Disable and invalidate cache * |
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115 | **********************************************************************/ |
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116 | static void disable_cache(void) |
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117 | { |
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118 | __asm__ ("move.l #0x01000000,%d0"); |
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119 | __asm__ ("movec %d0,%CACR"); |
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120 | } |
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121 | |
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122 | /********************************************************************* |
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123 | * init_clock_config - Clock Module * |
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124 | **********************************************************************/ |
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125 | void init_clock_config(void) |
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126 | { |
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127 | /* Clock module uses normal PLL mode with 16.0000 MHz external reference |
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128 | Bus clock frequency = 80.00 MHz |
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129 | Processor clock frequency = 3 x bus clock = 240.00 MHz |
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130 | Dithering disabled |
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131 | */ |
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132 | |
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133 | /* Check to see if the SDRAM has already been initialized |
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134 | by a run control tool. If it has, put SDRAM into self-refresh mode before |
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135 | initializing the PLL |
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136 | */ |
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137 | if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) |
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138 | MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE; |
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139 | |
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140 | /* Temporarily switch to LIMP mode |
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141 | NOTE: Ensure that this code is not executing from SDRAM, since the |
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142 | SDRAM Controller is disabled in LIMP mode |
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143 | */ |
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144 | MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2); |
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145 | MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP; |
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146 | |
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147 | /* Configure the PLL settings */ |
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148 | MCF_PLL_PODR = MCF_PLL_PODR_CPUDIV(0x2) | MCF_PLL_PODR_BUSDIV(0x6); |
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149 | MCF_PLL_PFDR = MCF_PLL_PFDR_MFD(0x78); |
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150 | MCF_PLL_PLLCR = 0; |
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151 | MCF_PLL_PMDR = 0; |
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152 | |
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153 | /* Enable PLL and wait for lock */ |
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154 | MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP; |
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155 | while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ; |
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156 | |
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157 | /* From the Device Errata: |
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158 | |
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159 | "After exiting LIMP mode, the value of 0x40000000 should be written |
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160 | to address 0xFC0B8080 before attempting to initialize the SDRAMC |
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161 | or exit the SDRAM from self-refresh mode." |
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162 | */ |
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163 | *(vuint32 *) 0xfc0b8080 = 0x40000000; |
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164 | |
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165 | /* If we put the SDRAM into self-refresh mode earlier, restore mode now */ |
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166 | if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) |
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167 | MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE; |
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168 | } |
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169 | |
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170 | /********************************************************************* |
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171 | * init_cache - Unified (Instruction and Data) Cache * |
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172 | **********************************************************************/ |
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173 | static void init_cache(void) |
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174 | { |
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175 | /* ACR0: Cache accesses to 32 MB memory region at address $40000000 |
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176 | CACR: Don't cache accesses to the rest of memory |
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177 | */ |
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178 | /* |
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179 | * Cache is enabled in bspstart.c |
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180 | */ |
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181 | #if 0 |
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182 | __asm__ ("move.l #0xa0000600,%d0"); |
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183 | __asm__ ("movec %d0,%CACR"); |
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184 | #endif |
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185 | __asm__ ("move.l #0x4001c020,%d0"); |
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186 | __asm__ ("movec %d0,%ACR0"); |
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187 | __asm__ ("move.l #0x00000000,%d0"); |
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188 | __asm__ ("movec %d0,%ACR1"); |
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189 | } |
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190 | |
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191 | /********************************************************************* |
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192 | * init_crossbar - Cross-Bar Switch (XBS) Module * |
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193 | **********************************************************************/ |
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194 | static void init_crossbar(void) |
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195 | { |
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196 | /* XBS settings for FlexBus/SDRAM Controller slave: |
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197 | Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core |
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198 | */ |
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199 | MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) | |
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200 | MCF_XBS_PRS_M5(0x4) | |
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201 | MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2); |
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202 | MCF_XBS_CRS1 = 0; |
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203 | |
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204 | /* XBS settings for SRAM Backdoor slave: |
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205 | Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core |
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206 | */ |
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207 | MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) | |
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208 | MCF_XBS_PRS_M5(0x4) | |
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209 | MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1); |
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210 | MCF_XBS_CRS4 = 0; |
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211 | |
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212 | /* XBS settings for Cryptography Modules slave: |
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213 | Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core |
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214 | */ |
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215 | MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) | |
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216 | MCF_XBS_PRS_M5(0x4) | |
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217 | MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1); |
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218 | MCF_XBS_CRS6 = 0; |
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219 | |
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220 | /* XBS settings for On-chip Peripherals slave: |
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221 | Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core |
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222 | */ |
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223 | MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) | |
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224 | MCF_XBS_PRS_M5(0x4) | |
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225 | MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1); |
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226 | MCF_XBS_CRS7 = 0; |
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227 | } |
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228 | |
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229 | /********************************************************************* |
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230 | * init_chip_selects - Chip Select Module (FlexBus) * |
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231 | **********************************************************************/ |
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232 | void init_chip_selects(void) |
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233 | { |
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234 | /* Chip Select 1 disabled (CSMR1[V] = 0) */ |
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235 | MCF_FBCS1_CSMR = 0; |
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236 | |
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237 | /* Chip Select 2 disabled (CSMR2[V] = 0) */ |
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238 | MCF_FBCS2_CSMR = 0; |
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239 | |
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240 | /* Chip Select 3 disabled (CSMR3[V] = 0) */ |
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241 | MCF_FBCS3_CSMR = 0; |
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242 | |
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243 | /* Chip Select 4 disabled (CSMR4[V] = 0) */ |
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244 | MCF_FBCS4_CSMR = 0; |
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245 | |
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246 | /* Chip Select 5 disabled (CSMR5[V] = 0) */ |
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247 | MCF_FBCS5_CSMR = 0; |
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248 | |
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249 | /* Chip Select 0: 2 MB of Flash at base address $00000000 |
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250 | Port size = 16 bits |
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251 | Assert chip select on first rising clock edge after address is asserted |
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252 | Generate internal transfer acknowledge after 7 wait states |
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253 | Address is held for 1 clock at end of read and write cycles |
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254 | */ |
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255 | MCF_FBCS0_CSAR = 0; |
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256 | MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) | |
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257 | (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM; |
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258 | MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V; |
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259 | } |
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260 | |
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261 | /********************************************************************* |
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262 | * init_eport - Edge Port Module (EPORT) * |
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263 | **********************************************************************/ |
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264 | static void init_eport(void) |
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265 | { |
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266 | /* Pins 1-7 configured as GPIO inputs */ |
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267 | MCF_EPORT_EPPAR = 0; |
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268 | MCF_EPORT_EPDDR = 0; |
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269 | MCF_EPORT_EPIER = 0; |
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270 | } |
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271 | |
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272 | /********************************************************************* |
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273 | * init_flexcan - FlexCAN Module * |
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274 | **********************************************************************/ |
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275 | static void init_flexcan(void) |
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276 | { |
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277 | /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */ |
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278 | MCF_CAN_IMASK = 0; |
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279 | MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff); |
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280 | MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff); |
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281 | MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff); |
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282 | MCF_CAN_CANCTRL = 0; |
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283 | MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS | |
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284 | MCF_CAN_CANMCR_FRZ | |
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285 | MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf); |
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286 | } |
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287 | |
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288 | /********************************************************************* |
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289 | * init_sdram_controller - SDRAM Controller * |
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290 | **********************************************************************/ |
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291 | void init_sdram_controller(void) |
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292 | { |
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293 | /* Check to see if the SDRAM has already been initialized |
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294 | by a run control tool and skip if so |
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295 | */ |
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296 | if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) |
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297 | return; |
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298 | |
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299 | /* Ensure that there is a delay from processor reset of the time recommended in |
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300 | the SDRAM data sheet (typically 100-200 microseconds) until the following |
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301 | code so that the SDRAM is ready for commands... |
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302 | */ |
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303 | |
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304 | /* SDRAM controller configured for Double-data rate (DDR) SDRAM |
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305 | Bus width = 16 bits |
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306 | SDRAM specification: |
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307 | SDRAM clock frequency = 80.00 MHz |
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308 | CASL = 2.5 |
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309 | ACTV-to-read/write delay, tRCD = 20.0 nanoseconds |
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310 | Write recovery time, tWR = 15.0 nanoseconds |
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311 | Precharge comand to ACTV command, tRP = 20.0 nanoseconds |
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312 | Auto refresh command period, tRFC = 75.0 nanoseconds |
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313 | Average periodic refresh interval, tREFI = 7.8 microseconds |
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314 | */ |
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315 | |
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316 | /* Memory block 0 enabled - 32 MBytes at address $40000000 |
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317 | Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks) |
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318 | */ |
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319 | MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18); |
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320 | |
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321 | /* Memory block 1 disabled */ |
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322 | MCF_SDRAMC_SDCS1 = 0; |
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323 | |
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324 | /* Initialise SDCFG1 register with delay and timing values |
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325 | SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2 |
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326 | PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3 |
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327 | */ |
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328 | MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) | |
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329 | MCF_SDRAMC_SDCFG1_SWT2RD(0x3) | |
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330 | MCF_SDRAMC_SDCFG1_RDLAT(0x7) | |
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331 | MCF_SDRAMC_SDCFG1_ACT2RW(0x2) | |
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332 | MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) | |
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333 | MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3); |
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334 | |
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335 | /* Initialise SDCFG2 register with delay and timing values |
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336 | BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7 |
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337 | */ |
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338 | MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) | |
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339 | MCF_SDRAMC_SDCFG2_BWT2RW(0x6) | |
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340 | MCF_SDRAMC_SDCFG2_BRD2WT(0x6) | MCF_SDRAMC_SDCFG2_BL(0x7); |
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341 | |
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342 | /* Issue a Precharge All command */ |
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343 | MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN | |
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344 | MCF_SDRAMC_SDCR_CKE | |
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345 | MCF_SDRAMC_SDCR_DDR | |
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346 | MCF_SDRAMC_SDCR_MUX(0x1) | |
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347 | MCF_SDRAMC_SDCR_RCNT(0x8) | MCF_SDRAMC_SDCR_PS_16 | MCF_SDRAMC_SDCR_IPALL; |
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348 | |
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349 | /* Write Extended Mode Register */ |
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350 | MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_CMD; |
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351 | |
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352 | /* Write Mode Register and Reset DLL */ |
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353 | MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR | |
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354 | MCF_SDRAMC_SDMR_AD(0x163) | MCF_SDRAMC_SDMR_CMD; |
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355 | |
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356 | /* Insert code here to pause for DLL lock time specified by memory... */ |
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357 | |
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358 | /* Issue a second Precharge All command */ |
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359 | MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; |
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360 | |
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361 | /* Refresh sequence... |
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362 | (check the number of refreshes required by the SDRAM manufacturer) |
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363 | */ |
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364 | MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; |
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365 | MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; |
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366 | |
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367 | /* Write Mode Register and clear the Reset DLL bit */ |
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368 | MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR | |
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369 | MCF_SDRAMC_SDMR_AD(0x63) | MCF_SDRAMC_SDMR_CMD; |
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370 | |
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371 | /* Enable automatic refresh and lock SDMR */ |
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372 | MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; |
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373 | MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_REF | |
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374 | MCF_SDRAMC_SDCR_DQS_OE(0x8) | MCF_SDRAMC_SDCR_DQS_OE(0x4); |
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375 | |
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376 | } |
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377 | |
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378 | /********************************************************************* |
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379 | * init_dma_timers - DMA Timers * |
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380 | **********************************************************************/ |
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381 | static void init_dma_timers(void) |
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382 | { |
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383 | /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ |
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384 | MCF_DTIM0_DTMR = 0; |
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385 | MCF_DTIM0_DTXMR = 0; |
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386 | MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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387 | |
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388 | /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ |
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389 | MCF_DTIM1_DTMR = 0; |
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390 | MCF_DTIM1_DTXMR = 0; |
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391 | MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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392 | |
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393 | /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ |
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394 | MCF_DTIM2_DTMR = 0; |
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395 | MCF_DTIM2_DTXMR = 0; |
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396 | MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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397 | |
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398 | /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ |
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399 | MCF_DTIM3_DTMR = 0; |
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400 | MCF_DTIM3_DTXMR = 0; |
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401 | MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff); |
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402 | } |
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403 | |
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404 | /********************************************************************* |
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405 | * init_interrupt_timers - Programmable Interrupt Timers (PIT) * |
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406 | **********************************************************************/ |
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407 | static void init_interrupt_timers(void) |
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408 | { |
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409 | /* PIT0 disabled (PCSR0[EN]=0) */ |
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410 | MCF_PIT0_PCSR = 0; |
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411 | |
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412 | /* PIT1 disabled (PCSR1[EN]=0) */ |
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413 | MCF_PIT1_PCSR = 0; |
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414 | |
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415 | /* PIT2 disabled (PCSR2[EN]=0) */ |
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416 | MCF_PIT2_PCSR = 0; |
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417 | |
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418 | /* PIT3 disabled (PCSR3[EN]=0) */ |
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419 | MCF_PIT3_PCSR = 0; |
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420 | } |
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421 | |
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422 | /********************************************************************* |
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423 | * init_real_time_clock - Real-Time Clock (RTC) * |
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424 | **********************************************************************/ |
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425 | static void init_real_time_clock(void) |
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426 | { |
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427 | /* Disable the RTC */ |
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428 | MCF_RTC_CR = 0; |
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429 | } |
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430 | |
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431 | /********************************************************************* |
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432 | * init_watchdog_timers - Watchdog Timers * |
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433 | **********************************************************************/ |
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434 | static void init_watchdog_timers(void) |
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435 | { |
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436 | /* Watchdog Timer disabled (WCR[EN]=0) |
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437 | NOTE: WCR and WMR cannot be written again until after the |
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438 | processor is reset. |
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439 | */ |
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440 | MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED; |
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441 | MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff); |
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442 | |
---|
443 | /* Core watchdog timer disabled */ |
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444 | MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8); |
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445 | } |
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446 | |
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447 | /********************************************************************* |
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448 | * init_edma - eDMA Controller * |
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449 | **********************************************************************/ |
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450 | static void init_edma(void) |
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451 | { |
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452 | /* Associate eDMA channels 9-12 with SSI signals */ |
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453 | MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA; |
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454 | |
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455 | /* Configured for round-robin arbitration mode */ |
---|
456 | MCF_EDMA_CR = MCF_EDMA_CR_ERCA; |
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457 | |
---|
458 | /* All error interrupts are disabled */ |
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459 | MCF_EDMA_EEI = 0; |
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460 | |
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461 | /* All DMA requests from peripherals are masked */ |
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462 | MCF_EDMA_ERQ = 0; |
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463 | } |
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464 | |
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465 | /********************************************************************* |
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466 | * init_interrupt_controller - Interrupt Controller * |
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467 | **********************************************************************/ |
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468 | static void init_interrupt_controller(void) |
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469 | { |
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470 | /* No interrupt sources configured */ |
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471 | MCF_INTC1_ICR0 = 0; |
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472 | MCF_INTC1_ICR1 = 0; |
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473 | MCF_INTC1_ICR3 = 0; |
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474 | MCF_INTC1_ICR4 = 0; |
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475 | MCF_INTC1_ICR5 = 0; |
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476 | MCF_INTC1_ICR6 = 0; |
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477 | MCF_INTC1_ICR7 = 0; |
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478 | MCF_INTC1_ICR8 = 0; |
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479 | MCF_INTC1_ICR9 = 0; |
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480 | MCF_INTC1_ICR10 = 0; |
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481 | MCF_INTC1_ICR11 = 0; |
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482 | MCF_INTC1_ICR12 = 0; |
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483 | MCF_INTC1_ICR13 = 0; |
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484 | MCF_INTC1_ICR14 = 0; |
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485 | MCF_INTC1_ICR15 = 0; |
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486 | MCF_INTC1_ICR16 = 0; |
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487 | MCF_INTC1_ICR17 = 0; |
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488 | MCF_INTC1_ICR18 = 0; |
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489 | MCF_INTC1_ICR19 = 0; |
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490 | MCF_INTC1_ICR40 = 0; |
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491 | MCF_INTC1_ICR41 = 0; |
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492 | MCF_INTC1_ICR42 = 0; |
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493 | MCF_INTC1_ICR43 = 0; |
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494 | MCF_INTC1_ICR44 = 0; |
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495 | MCF_INTC1_ICR45 = 0; |
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496 | MCF_INTC1_ICR46 = 0; |
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497 | MCF_INTC1_ICR47 = 0; |
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498 | MCF_INTC1_ICR48 = 0; |
---|
499 | MCF_INTC1_ICR49 = 0; |
---|
500 | MCF_INTC1_ICR50 = 0; |
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501 | MCF_INTC1_ICR51 = 0; |
---|
502 | MCF_INTC1_ICR52 = 0; |
---|
503 | MCF_INTC1_ICR53 = 0; |
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504 | MCF_INTC0_ICR1 = 0; |
---|
505 | MCF_INTC0_ICR2 = 0; |
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506 | MCF_INTC0_ICR3 = 0; |
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507 | MCF_INTC0_ICR4 = 0; |
---|
508 | MCF_INTC0_ICR5 = 0; |
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509 | MCF_INTC0_ICR6 = 0; |
---|
510 | MCF_INTC0_ICR7 = 0; |
---|
511 | MCF_INTC0_ICR8 = 0; |
---|
512 | MCF_INTC0_ICR9 = 0; |
---|
513 | MCF_INTC0_ICR10 = 0; |
---|
514 | MCF_INTC0_ICR11 = 0; |
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515 | MCF_INTC0_ICR12 = 0; |
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516 | MCF_INTC0_ICR13 = 0; |
---|
517 | MCF_INTC0_ICR14 = 0; |
---|
518 | MCF_INTC0_ICR15 = 0; |
---|
519 | MCF_INTC0_ICR16 = 0; |
---|
520 | MCF_INTC0_ICR17 = 0; |
---|
521 | MCF_INTC0_ICR18 = 0; |
---|
522 | MCF_INTC0_ICR19 = 0; |
---|
523 | MCF_INTC0_ICR20 = 0; |
---|
524 | MCF_INTC0_ICR21 = 0; |
---|
525 | MCF_INTC0_ICR22 = 0; |
---|
526 | MCF_INTC0_ICR23 = 0; |
---|
527 | MCF_INTC0_ICR24 = 0; |
---|
528 | MCF_INTC0_ICR25 = 0; |
---|
529 | MCF_INTC0_ICR26 = 0; |
---|
530 | MCF_INTC0_ICR27 = 0; |
---|
531 | MCF_INTC0_ICR28 = 0; |
---|
532 | MCF_INTC0_ICR30 = 0; |
---|
533 | MCF_INTC0_ICR31 = 0; |
---|
534 | MCF_INTC0_ICR32 = 0; |
---|
535 | MCF_INTC0_ICR33 = 0; |
---|
536 | MCF_INTC0_ICR34 = 0; |
---|
537 | MCF_INTC0_ICR35 = 0; |
---|
538 | MCF_INTC0_ICR36 = 0; |
---|
539 | MCF_INTC0_ICR37 = 0; |
---|
540 | MCF_INTC0_ICR38 = 0; |
---|
541 | MCF_INTC0_ICR39 = 0; |
---|
542 | MCF_INTC0_ICR40 = 0; |
---|
543 | MCF_INTC0_ICR41 = 0; |
---|
544 | MCF_INTC0_ICR42 = 0; |
---|
545 | MCF_INTC0_ICR43 = 0; |
---|
546 | MCF_INTC0_ICR44 = 0; |
---|
547 | MCF_INTC0_ICR45 = 0; |
---|
548 | MCF_INTC0_ICR46 = 0; |
---|
549 | MCF_INTC0_ICR47 = 0; |
---|
550 | MCF_INTC0_ICR48 = 0; |
---|
551 | MCF_INTC0_ICR62 = 0; |
---|
552 | MCF_INTC0_IMRH = 0xffffffff; |
---|
553 | MCF_INTC0_IMRL = 0xffffffff; |
---|
554 | MCF_INTC1_IMRH = 0xffffffff; |
---|
555 | MCF_INTC1_IMRL = 0xffffffff; |
---|
556 | } |
---|
557 | |
---|
558 | /********************************************************************* |
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559 | * init_pin_assignments - Pin Assignment and General Purpose I/O * |
---|
560 | **********************************************************************/ |
---|
561 | static void init_pin_assignments(void) |
---|
562 | { |
---|
563 | /* Pin assignments for port BUSCTL |
---|
564 | Pin BUSCTL3 : External bus output enable, /OE |
---|
565 | Pin BUSCTL2 : External bus transfer acknowledge, /TA |
---|
566 | Pin BUSCTL1 : External bus read/write, R/W |
---|
567 | Pin BUSCTL0 : External bus transfer start, /TS |
---|
568 | */ |
---|
569 | MCF_GPIO_PDDR_BUSCTL = 0; |
---|
570 | MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE | |
---|
571 | MCF_GPIO_PAR_BUSCTL_PAR_TA | |
---|
572 | MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3); |
---|
573 | |
---|
574 | /* Pin assignments for port BE |
---|
575 | Pin BE3 : External bus byte enable BW/BWE3 |
---|
576 | Pin BE2 : External bus byte enable BW/BWE2 |
---|
577 | Pin BE1 : External bus byte enable BW/BWE1 |
---|
578 | Pin BE0 : External bus byte enable BW/BWE0 |
---|
579 | */ |
---|
580 | MCF_GPIO_PDDR_BE = 0; |
---|
581 | MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 | |
---|
582 | MCF_GPIO_PAR_BE_PAR_BE2 | |
---|
583 | MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0; |
---|
584 | |
---|
585 | /* Pin assignments for port CS |
---|
586 | Pin CS5 : Flex bus chip select /FB_CS5 |
---|
587 | Pin CS4 : Flex bus chip select /FB_CS4 |
---|
588 | Pin CS3 : Flex bus chip select /FB_CS3 |
---|
589 | Pin CS2 : Flex bus chip select /FB_CS2 |
---|
590 | Pin CS1 : Flex bus chip select /FB_CS1 |
---|
591 | */ |
---|
592 | MCF_GPIO_PDDR_CS = 0; |
---|
593 | MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 | |
---|
594 | MCF_GPIO_PAR_CS_PAR_CS4 | |
---|
595 | MCF_GPIO_PAR_CS_PAR_CS3 | |
---|
596 | MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1; |
---|
597 | |
---|
598 | /* Pin assignments for port FECI2C |
---|
599 | Pin FECI2C3 : FEC management data clock, FEC_MDC |
---|
600 | Pin FECI2C2 : FEC management data, FEC_MDIO |
---|
601 | Pin FECI2C1 : GPIO input |
---|
602 | Pin FECI2C0 : GPIO input |
---|
603 | */ |
---|
604 | MCF_GPIO_PDDR_FECI2C = 0; |
---|
605 | MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) | |
---|
606 | MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3); |
---|
607 | |
---|
608 | /* Pin assignments for ports FECH and FECL |
---|
609 | Pin FECH7 : FEC transmit clock, FEC_TXCLK |
---|
610 | Pin FECH6 : FEC transmit enable, FEC_TXEN |
---|
611 | Pin FECH5 : FEC transmit data 0, FEC_TXD0 |
---|
612 | Pin FECH4 : FEC collision, FEC_COL |
---|
613 | Pin FECH3 : FEC receive clock, FEC_RXCLK |
---|
614 | Pin FECH2 : FEC receive data valid, FEC_RXDV |
---|
615 | Pin FECH1 : FEC receive data 0, FEC_RXD0 |
---|
616 | Pin FECH0 : FEC carrier receive sense, FEC_CRS |
---|
617 | Pin FECL7 : FEC transmit data 3, FEC_TXD3 |
---|
618 | Pin FECL6 : FEC transmit data 2, FEC_TXD2 |
---|
619 | Pin FECL5 : FEC transmit data 1, FEC_TXD1 |
---|
620 | Pin FECL4 : FEC transmit error, FEC_TXER |
---|
621 | Pin FECL3 : FEC receive data 3, FEX_RXD3 |
---|
622 | Pin FECL2 : FEC receive data 2, FEX_RXD2 |
---|
623 | Pin FECL1 : FEC receive data 1, FEX_RXD1 |
---|
624 | Pin FECL0 : FEC receive error, FEC_RXER |
---|
625 | */ |
---|
626 | MCF_GPIO_PDDR_FECH = 0; |
---|
627 | MCF_GPIO_PDDR_FECL = 0; |
---|
628 | MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) | |
---|
629 | MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3); |
---|
630 | |
---|
631 | /* Pin assignments for port IRQ |
---|
632 | Pins are all used for EdgePort GPIO/IRQ |
---|
633 | */ |
---|
634 | MCF_GPIO_PAR_IRQ = 0; |
---|
635 | |
---|
636 | /* Pin assignments for port LCDDATAH |
---|
637 | Pins are all GPIO inputs |
---|
638 | */ |
---|
639 | MCF_GPIO_PDDR_LCDDATAH = 0; |
---|
640 | MCF_GPIO_PAR_LCDDATA = 0; |
---|
641 | |
---|
642 | /* Pin assignments for port LCDDATAM |
---|
643 | Port LCDDATAM pins are all GPIO inputs |
---|
644 | */ |
---|
645 | MCF_GPIO_PDDR_LCDDATAM = 0; |
---|
646 | |
---|
647 | /* Pin assignments for port LCDDATAL |
---|
648 | Port LCDDATAL pins are all GPIO inputs |
---|
649 | */ |
---|
650 | MCF_GPIO_PDDR_LCDDATAL = 0; |
---|
651 | |
---|
652 | /* Pin assignments for port LCDCTLH |
---|
653 | Pins are all GPIO inputs |
---|
654 | */ |
---|
655 | MCF_GPIO_PDDR_LCDCTLH = 0; |
---|
656 | MCF_GPIO_PAR_LCDCTL = 0; |
---|
657 | |
---|
658 | /* Pin assignments for port LCDCTLL |
---|
659 | Pins are all GPIO inputs |
---|
660 | */ |
---|
661 | MCF_GPIO_PDDR_LCDCTLL = 0; |
---|
662 | |
---|
663 | /* Pin assignments for port PWM |
---|
664 | Pins are all GPIO inputs |
---|
665 | */ |
---|
666 | MCF_GPIO_PDDR_PWM = 0; |
---|
667 | MCF_GPIO_PAR_PWM = 0; |
---|
668 | |
---|
669 | /* Pin assignments for port QSPI |
---|
670 | Pins are all GPIO inputs |
---|
671 | */ |
---|
672 | MCF_GPIO_PDDR_QSPI = 0; |
---|
673 | MCF_GPIO_PAR_QSPI = 0; |
---|
674 | |
---|
675 | /* Pin assignments for port SSI |
---|
676 | Pins are all GPIO inputs |
---|
677 | */ |
---|
678 | MCF_GPIO_PDDR_SSI = 0; |
---|
679 | MCF_GPIO_PAR_SSI = 0; |
---|
680 | |
---|
681 | /* Pin assignments for port TIMER |
---|
682 | Pins are all GPIO outputs |
---|
683 | */ |
---|
684 | MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 | |
---|
685 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 | |
---|
686 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0; |
---|
687 | MCF_GPIO_PAR_TIMER = 0; |
---|
688 | |
---|
689 | /* Pin assignments for port UART |
---|
690 | Pin UART7 : UART 1 clear-to-send, /U1CTS |
---|
691 | Pin UART6 : UART 1 request-to-send, /U1RTS |
---|
692 | Pin UART5 : UART 1 transmit data, U1TXD |
---|
693 | Pin UART4 : UART 1 receive data, U1RXD |
---|
694 | Pin UART3 : UART 0 clear-to-send, /U0CTS |
---|
695 | Pin UART2 : UART 0 request-to-send, /U0RTS |
---|
696 | Pin UART1 : UART 0 transmit data, U0TXD |
---|
697 | Pin UART0 : UART 0 receive data, U0RXD |
---|
698 | */ |
---|
699 | MCF_GPIO_PDDR_UART = 0; |
---|
700 | MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) | |
---|
701 | MCF_GPIO_PAR_UART_PAR_URTS1(0x3) | |
---|
702 | MCF_GPIO_PAR_UART_PAR_URXD1(0x3) | |
---|
703 | MCF_GPIO_PAR_UART_PAR_UTXD1(0x3) | |
---|
704 | MCF_GPIO_PAR_UART_PAR_UCTS0 | |
---|
705 | MCF_GPIO_PAR_UART_PAR_URTS0 | |
---|
706 | MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0; |
---|
707 | } |
---|