source: rtems/bsps/m68k/mcf5329/start/bspstart.c

Last change on this file was c46ec2b, checked in by Joel Sherrill <joel@…>, on 07/08/22 at 13:57:11

bsps/m68k/mcf5329: Change license to BSD-2

Updates #3053.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 *  This routine does the bulk of the system initialisation.
5 */
6
7/*
8 *  Author:
9 *    David Fiddes, D.J@fiddes.surfaid.org
10 *    http://www.calm.hw.ac.uk/davidf/coldfire/
11 *
12 *  COPYRIGHT (c) 1989-1998.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <bsp.h>
38#include <bsp/bootcard.h>
39#include <rtems/rtems/cache.h>
40
41void bsp_start(void)
42{
43  /* cfinit invalidates cache and sets acr registers */
44
45  /*
46   * Enable the cache, we only need to enable the instruction cache as the
47   * 532x has a unified data and instruction cache.
48   */
49  rtems_cache_enable_instruction();
50}
51
52uint32_t bsp_get_CPU_clock_speed(void)
53{
54  return 240000000;
55}
56
57uint32_t bsp_get_BUS_clock_speed(void)
58{
59  return 80000000;
60}
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