[c991eeec] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup RTEMSBSPsM68kMCF5206Elite |
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| 5 | * |
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| 6 | * @brief Global BSP definitions. |
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| 7 | */ |
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| 8 | |
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[e56c3546] | 9 | /* |
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| 10 | * Board Support Package for MCF5206eLITE evaluation board |
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| 11 | * BSP definitions |
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| 12 | * |
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| 13 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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| 14 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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| 15 | * |
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| 16 | * The license and distribution terms for this file may be |
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| 17 | * found in the file LICENSE in this distribution or at |
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| 18 | * |
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[c499856] | 19 | * http://www.rtems.org/license/LICENSE. |
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[e56c3546] | 20 | */ |
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| 21 | |
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[9cff822a] | 22 | #ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H |
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| 23 | #define LIBBSP_M68K_MCF5206ELITE_BSP_H |
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[e56c3546] | 24 | |
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[c991eeec] | 25 | /** |
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| 26 | * @defgroup RTEMSBSPsM68kMCF5206Elite MCF5206eLite |
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| 27 | * |
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| 28 | * @ingroup RTEMSBSPsM68k |
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| 29 | * |
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| 30 | * @brief MCF5206eLite Board Support Package. |
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| 31 | * |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |
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[e56c3546] | 35 | #include "mcf5206/mcf5206e.h" |
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| 36 | |
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| 37 | /*** Board resources allocation ***/ |
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| 38 | |
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[6128a4a] | 39 | /* |
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[e56c3546] | 40 | * To achieve some compatibility with dBUG monitor, we use the same |
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| 41 | * memory resources allocation as it is used in dBUG. |
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| 42 | * |
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| 43 | * If this definitions will be changed, change the linker script also. |
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| 44 | */ |
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[6128a4a] | 45 | |
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[e56c3546] | 46 | /* Memory mapping */ |
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| 47 | /* CS0: Boot Flash */ |
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| 48 | #define BSP_MEM_ADDR_FLASH (0xFFE00000) |
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[ccceaf3] | 49 | #define BSP_MEM_SIZE_FLASH (1*1024*1024) |
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[e56c3546] | 50 | #define BSP_MEM_MASK_FLASH (MCF5206E_CSMR_MASK_1M) |
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| 51 | |
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| 52 | /* CS2: External SRAM */ |
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| 53 | #define BSP_MEM_ADDR_ESRAM (0x30000000) |
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[ccceaf3] | 54 | #define BSP_MEM_SIZE_ESRAM (1*1024*1024) |
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[e56c3546] | 55 | #define BSP_MEM_MASK_ESRAM (MCF5206E_CSMR_MASK_1M) |
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| 56 | |
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| 57 | /* CS3: General-Purpose I/O register */ |
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| 58 | #define BSP_MEM_ADDR_GPIO (0x40000000) |
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[ccceaf3] | 59 | #define BSP_MEM_SIZE_GPIO (64*1024) |
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[e56c3546] | 60 | #define BSP_MEM_MASK_GPIO (MCF5206E_CSMR_MASK_64K) |
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| 61 | |
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| 62 | /* DRAM0: Dynamic RAM */ |
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| 63 | #define BSP_MEM_ADDR_DRAM (0x00000000) |
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[ccceaf3] | 64 | #define BSP_MEM_SIZE_DRAM (16*1024*1024) |
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[e56c3546] | 65 | #define BSP_MEM_MASK_DRAM (MCF5206E_DCMR_MASK_16M) |
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| 66 | |
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| 67 | /* On-chip SRAM */ |
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| 68 | #define BSP_MEM_ADDR_SRAM (0x20000000) |
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[ccceaf3] | 69 | #define BSP_MEM_SIZE_SRAM (8*1024) |
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[e56c3546] | 70 | |
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| 71 | /* On-chip peripherial registers */ |
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| 72 | #define BSP_MEM_ADDR_IMM (0x10000000) |
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[ccceaf3] | 73 | #define BSP_MEM_SIZE_IMM (1*1024) |
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[e56c3546] | 74 | #define MBAR BSP_MEM_ADDR_IMM |
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| 75 | |
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| 76 | /* Interrupt vector assignment */ |
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| 77 | #define BSP_INTVEC_AVEC1 (25) |
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| 78 | #define BSP_INTLVL_AVEC1 (1) |
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| 79 | #define BSP_INTPRIO_AVEC1 (3) |
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| 80 | |
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| 81 | #define BSP_INTVEC_AVEC2 (26) |
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| 82 | #define BSP_INTLVL_AVEC2 (2) |
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| 83 | #define BSP_INTPRIO_AVEC2 (3) |
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| 84 | |
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| 85 | #define BSP_INTVEC_AVEC3 (27) |
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| 86 | #define BSP_INTLVL_AVEC3 (3) |
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| 87 | #define BSP_INTPRIO_AVEC3 (3) |
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| 88 | |
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| 89 | #define BSP_INTVEC_AVEC4 (28) |
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| 90 | #define BSP_INTLVL_AVEC4 (4) |
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| 91 | #define BSP_INTPRIO_AVEC4 (3) |
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| 92 | |
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| 93 | #define BSP_INTVEC_AVEC5 (29) |
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| 94 | #define BSP_INTLVL_AVEC5 (5) |
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| 95 | #define BSP_INTPRIO_AVEC5 (3) |
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| 96 | |
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| 97 | #define BSP_INTVEC_AVEC6 (30) |
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| 98 | #define BSP_INTLVL_AVEC6 (6) |
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| 99 | #define BSP_INTPRIO_AVEC6 (3) |
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| 100 | |
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| 101 | #define BSP_INTVEC_AVEC7 (31) |
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| 102 | #define BSP_INTLVL_AVEC7 (7) |
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| 103 | #define BSP_INTPRIO_AVEC7 (3) |
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| 104 | |
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| 105 | #define BSP_INTVEC_TIMER1 (BSP_INTVEC_AVEC5) |
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| 106 | #define BSP_INTLVL_TIMER1 (BSP_INTLVL_AVEC5) |
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| 107 | #define BSP_INTPRIO_TIMER1 (2) |
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| 108 | |
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| 109 | #define BSP_INTVEC_TIMER2 (BSP_INTVEC_AVEC6) |
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| 110 | #define BSP_INTLVL_TIMER2 (BSP_INTLVL_AVEC6) |
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| 111 | #define BSP_INTPRIO_TIMER2 (2) |
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| 112 | |
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| 113 | #define BSP_INTVEC_MBUS (BSP_INTVEC_AVEC4) |
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| 114 | #define BSP_INTLVL_MBUS (BSP_INTLVL_AVEC4) |
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| 115 | #define BSP_INTPRIO_MBUS (2) |
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| 116 | |
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| 117 | #define BSP_INTVEC_UART1 (64) |
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| 118 | #define BSP_INTLVL_UART1 (4) |
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| 119 | #define BSP_INTPRIO_UART1 (0) |
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| 120 | |
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| 121 | #define BSP_INTVEC_UART2 (65) |
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| 122 | #define BSP_INTLVL_UART2 (4) |
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| 123 | #define BSP_INTPRIO_UART2 (1) |
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| 124 | |
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| 125 | #define BSP_INTVEC_DMA0 (66) |
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| 126 | #define BSP_INTLVL_DMA0 (3) |
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| 127 | #define BSP_INTPRIO_DMA0 (1) |
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| 128 | |
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| 129 | #define BSP_INTVEC_DMA1 (67) |
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| 130 | #define BSP_INTLVL_DMA1 (3) |
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| 131 | #define BSP_INTPRIO_DMA1 (2) |
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| 132 | |
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| 133 | /* Location of DS1307 Real-Time Clock/NVRAM chip */ |
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| 134 | #define DS1307_I2C_BUS_NUMBER (0) |
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| 135 | |
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| 136 | #ifndef ASM |
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| 137 | |
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| 138 | #include <bspopts.h> |
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| 139 | #include <rtems.h> |
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[a052181] | 140 | #include <bsp/default-initial-extension.h> |
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[e56c3546] | 141 | |
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[46dde0fc] | 142 | #ifdef __cplusplus |
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| 143 | extern "C" { |
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| 144 | #endif |
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| 145 | |
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[e56c3546] | 146 | /* System frequency */ |
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| 147 | #define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY) |
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| 148 | extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */ |
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| 149 | |
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| 150 | /* MBUS I2C bus clock default frequency */ |
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| 151 | #define BSP_MBUS_FREQUENCY (16000) |
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| 152 | |
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| 153 | /* Number of I2C buses supported in this board */ |
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| 154 | #define I2C_NUMBER_OF_BUSES (1) |
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| 155 | |
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| 156 | /* I2C bus selection */ |
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| 157 | #define I2C_SELECT_BUS(bus) |
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| 158 | |
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| 159 | /* |
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| 160 | * Simple spin delay in microsecond units for device drivers. |
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| 161 | * This is very dependent on the clock speed of the target. |
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| 162 | */ |
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| 163 | |
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[cba8970e] | 164 | #define rtems_bsp_delay( microseconds ) \ |
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[b7044dc] | 165 | { register uint32_t _delay=(microseconds); \ |
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| 166 | register uint32_t _tmp=123; \ |
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[abc8ad0f] | 167 | __asm__ volatile( "0: \ |
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[e56c3546] | 168 | nbcd %0 ; \ |
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| 169 | nbcd %0 ; \ |
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| 170 | dbf %1,0b" \ |
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| 171 | : "=d" (_tmp), "=d" (_delay) \ |
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| 172 | : "0" (_tmp), "1" (_delay) ); \ |
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| 173 | } |
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| 174 | |
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| 175 | |
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[1fec9e0] | 176 | extern rtems_isr_entry M68Kvec[]; /* vector table address */ |
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[e56c3546] | 177 | |
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| 178 | extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); |
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| 179 | |
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| 180 | /* functions */ |
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| 181 | |
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[1fec9e0] | 182 | rtems_isr_entry set_vector( |
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[e56c3546] | 183 | rtems_isr_entry handler, |
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| 184 | rtems_vector_number vector, |
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| 185 | int type |
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| 186 | ); |
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| 187 | |
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[a94fb39] | 188 | /* |
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| 189 | * Prototypes for BSP methods that cross file boundaries |
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| 190 | */ |
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| 191 | void Init5206e(void); |
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| 192 | |
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[e56c3546] | 193 | #ifdef __cplusplus |
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| 194 | } |
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| 195 | #endif |
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| 196 | |
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| 197 | #endif /* ASM */ |
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| 198 | |
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[c991eeec] | 199 | /** @} */ |
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| 200 | |
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[e56c3546] | 201 | #endif |
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