source: rtems/bsps/m68k/include/mvme16x_hw.h

Last change on this file was 62f31d05, checked in by Joel Sherrill <joel@…>, on 07/08/22 at 13:54:31

bsps/m68k/include: Change license to BSD-2

Updates #3053.
  • Property mode set to 100644
File size: 9.8 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 *  @file
5 *
6 *  @ingroup m68k_mvme
7 *
8 *  @brief MVME16x IO definitions
9 */
10
11/*  mvme16x_hw.h
12 *
13 *  This include file contains all MVME16x board IO definitions
14 *  and was derived by combining the common items in the
15 *  mvme162 and mvme167 BSPs.
16 *
17 *  COPYRIGHT (c) 1989-2000.
18 *  On-Line Applications Research Corporation (OAR).
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 * 1. Redistributions of source code must retain the above copyright
24 *    notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 *    notice, this list of conditions and the following disclaimer in the
27 *    documentation and/or other materials provided with the distribution.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
33 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MVME16xHW_h
43#define __MVME16xHW_h
44
45#include <bsp.h>
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51/**
52 *  @defgroup m68k_mvme MVME16X IO Support
53 *
54 *  @ingroup RTEMSBSPsM68kShared
55 *
56 *  @brief IO Support Package
57 */
58
59struct rtems_bsdnet_ifconfig;
60int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
61#define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
62#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
63
64/*
65 *  This is NOT the base address of local RAM!
66 *  This is the base local address of the VMEbus short I/O space. A local
67 *  access to this space results in a A16 VMEbus I/O cycle. This base address
68 *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
69 *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
70 *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
71 *  GCSRs of other boards are accessible only through the VMEbus short I/O
72 *  space. See pages 2-45 and 2-7.
73 */
74#define BOARD_BASE_ADDRESS 0xFFFF0000
75
76/*
77 *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
78 *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
79 *  VMEbus short I/O space. It also should represent the group address of this
80 *  MVME167! The group address is configurable, and must match the address
81 *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
82 *  recommended by Motorola. It is arbitrary.
83 *  See pages 2-42 and 2-97 to 2-104.
84 */
85#define GROUP_BASE_ADDRESS 0x0000CC00
86
87/*
88 *  Representation of the VMEchip2 LCSR.
89 *  Could be made more detailed.
90 */
91
92typedef volatile struct {
93  unsigned long     slave_adr[2];
94  unsigned long     slave_trn[2];
95  unsigned long     slave_ctl;
96  unsigned long     mastr_adr[4];
97  unsigned long     mastr_trn;
98  unsigned long     mastr_att;
99  unsigned long     mastr_ctl;
100  unsigned long     dma_ctl_1;
101  unsigned long     dma_ctl_2;
102  unsigned long     dma_loc_cnt;
103  unsigned long     dma_vme_cnt;
104  unsigned long     dma_byte_cnt;
105  unsigned long     dma_adr_cnt;
106  unsigned long     dma_status;
107  unsigned long     to_ctl;
108  unsigned long     timer_cmp_1;
109  unsigned long     timer_cnt_1;
110  unsigned long     timer_cmp_2;
111  unsigned long     timer_cnt_2;
112  unsigned long     board_ctl;
113  unsigned long     prescaler_cnt;
114  unsigned long     intr_stat;
115  unsigned long     intr_ena;
116  unsigned long     intr_soft_set;
117  unsigned long     intr_clear;
118  unsigned long     intr_level[4];
119  unsigned long     vector_base;
120} lcsr_regs;
121
122/*
123 *  Base address of VMEchip2 LCSR
124 *  Not configurable on the MVME167.
125 *  XXX what about 162?
126 */
127#define lcsr        ((lcsr_regs * const) 0xFFF40000)
128
129/*
130 *  Vector numbers for the interrupts from the VMEchip2. Use the values
131 *  "recommended" by Motorola.
132 *  See pages 2-70 to 2-92, and table 2-3.
133 */
134
135/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
136#define MASK_INT    0x00800000
137
138/* The content of VBR0 corresponds to "X" in table 2-3 */
139#define VBR0        0x6
140
141/* The content of VBR1 corresponds to "Y" in table 2-3 */
142#define VBR1        0x7
143
144/*
145 *  Representation of the PCCchip2
146 */
147typedef volatile struct pccchip2_regs_ {
148  unsigned char     chip_id;            /* 0xFFF42000 */
149  unsigned char     chip_revision;      /* 0xFFF42001 */
150  unsigned char     gen_control;        /* 0xFFF42002 */
151  unsigned char     vector_base;        /* 0xFFF42003 */
152  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
153  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
154  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
155  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
156  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
157  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
158  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
159  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
160  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
161  unsigned char     gpio_ctl;           /* 0xFFF42019 */
162  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
163  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
164  unsigned char     SCC_error;          /* 0xFFF4201C */
165  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
166  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
167  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
168  unsigned char     reserved1[3];
169  unsigned char     modem_piack;        /* 0xFFF42023 */
170  unsigned char     reserved2;
171  unsigned char     tx_piack;           /* 0xFFF42025 */
172  unsigned char     reserved3;
173  unsigned char     rx_piack;           /* 0xFFF42027 */
174  unsigned char     LANC_error;         /* 0xFFF42028 */
175  unsigned char     reserved4;
176  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
177  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
178  unsigned char     SCSI_error;         /* 0xFFF4202C */
179  unsigned char     reserved5[2];
180  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
181  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
182  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
183  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
184  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
185  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
186  unsigned char     reserved6;
187  unsigned char     print_input_status; /* 0xFFF42036 */
188  unsigned char     print_ctl;          /* 0xFFF42037 */
189  unsigned char     chip_speed;         /* 0xFFF42038 */
190  unsigned char     reserved7;
191  unsigned char     print_data;         /* 0xFFF4203A */
192  unsigned char     reserved8[3];
193  unsigned char     int_level;          /* 0xFFF4203E */
194  unsigned char     int_mask;           /* 0xFFF4203F */
195} pccchip2_regs;
196
197/*
198 *  Base address of the PCCchip2.
199 *  This is not configurable in the MVME167.
200 */
201#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
202
203/*
204 *  On the MVME162, we have the mcchip and the pccchip2 on
205 *  the 167.  They are similar but different enough where
206 *  we have to reconcile them later.
207 */
208
209/*
210 * Vector numbers for the interrupts from the PCCchip2. Use the values
211 * "recommended" by Motorola.
212 * See page 3-15.
213 */
214#define PCCCHIP2_VBR    0x5
215
216/*
217 * The following registers are located in the VMEbus short
218 * IO space and respond to address modifier codes $29 and $2D.
219 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
220 */
221
222typedef volatile struct {
223  unsigned char       chip_revision;
224  unsigned char       chip_id;
225  unsigned char       lmsig;
226  unsigned char       board_scr;
227  unsigned short      gpr[6];
228} gcsr_regs;
229
230#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
231#define gcsr     ((gcsr_regs * const) 0xFFF40100)
232
233/*
234 *  Representation of 82596CA LAN controller: Memory Map
235 */
236typedef volatile struct i82596_regs_ {
237  unsigned short  port_lower;             /* 0xFFF46000 */
238  unsigned short  port_upper;             /* 0xFFF46002 */
239  unsigned long   chan_attn;              /* 0xFFF46004 */
240} i82596_regs;
241
242/*
243 *  Base address of the 82596.
244 */
245
246#define i82596    ((i82596_regs * const) 0xFFF46000)
247
248/*
249 *  Representation of initialization data in NVRAM
250 */
251
252#if defined(mvme167)
253typedef volatile struct nvram_config_ {
254  unsigned char   cache_mode;          /* 0xFFFC0000 */
255  unsigned char   console_mode;        /* 0xFFFC0001 */
256  unsigned char   console_printk_port; /* 0xFFFC0002 */
257  unsigned char   pad1;                /* 0xFFFC0003 */
258  unsigned long   ipaddr;              /* 0xFFFC0004 */
259  unsigned long   netmask;             /* 0xFFFC0008 */
260  unsigned char   enaddr[6];           /* 0xFFFC000C */
261  unsigned short  processor_id;        /* 0xFFFC0012 */
262  unsigned long   rma_start;           /* 0xFFFC0014 */
263  unsigned long   vma_start;           /* 0xFFFC0018 */
264  unsigned long   ramsize;             /* 0xFFFC001C */
265} nvram_config;
266
267/*
268 *  Pointer to the base of User Area NVRAM
269 */
270
271#define nvram      ((nvram_config * const) 0xFFFC0000)
272
273#endif
274
275/*
276 *  Flag to indicate if J1-4 is on (and parameters should be
277 *  sought in User Area NVRAM)
278 *
279 *  NOTE:  If NVRAM has bad settings, the you want to disable this
280 *         on the MVME167.
281 */
282#if defined(mvme167)
283  #define NVRAM_CONFIGURE \
284    ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
285#else
286  #define NVRAM_CONFIGURE 0
287#endif
288
289#ifdef __cplusplus
290}
291#endif
292
293#endif
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