source: rtems/bsps/m68k/include/mcf5272/mcf5272.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 20.0 KB
Line 
1/*
2 *  Coldfire MCF5272 definitions.
3 *  Contents of this file based on information provided in
4 *  Motorola MCF5272 User's Manual.
5 *
6 *  Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com>
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.org/license/LICENSE.
11 */
12
13#ifndef __MCF5272_H__
14#define __MCF5272_H__
15
16#ifndef ASM
17#include <rtems.h>
18#endif
19
20#define bit(x) (1 << (x))
21
22#define MCF5272_SIM_BASE(mbar)    ((mbar) + 0x0000)
23#define MCF5272_INT_BASE(mbar)    ((mbar) + 0x0020)
24#define MCF5272_CS_BASE(mbar)     ((mbar) + 0x0040)
25#define MCF5272_GPIO_BASE(mbar)   ((mbar) + 0x0080)
26#define MCF5272_QSPI_BASE(mbar)   ((mbar) + 0x00A0)
27#define MCF5272_PWM_BASE(mbar)    ((mbar) + 0x00C0)
28#define MCF5272_DMAC_BASE(mbar)   ((mbar) + 0x00E0)
29#define MCF5272_UART0_BASE(mbar)  ((mbar) + 0x0100)
30#define MCF5272_UART1_BASE(mbar)  ((mbar) + 0x0140)
31#define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180)
32#define MCF5272_TIMER_BASE(mbar)  ((mbar) + 0x0200)
33#define MCF5272_PLIC_BASE(mbar)   ((mbar) + 0x0300)
34#define MCF5272_ENET_BASE(mbar)   ((mbar) + 0x0840)
35#define MCF5272_USB_BASE(mbar)    ((mbar) + 0x1000)
36
37
38/* RAMBAR - SRAM Base Address Register */
39#define MCF5272_RAMBAR_BA  (0xfffff000) /* SRAM Base Address */
40#define MCF5272_RAMBAR_WP  (0x00000100) /* Write Protect */
41#define MCF5272_RAMBAR_CI  (0x00000020) /* CPU Space mask */
42#define MCF5272_RAMBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
43#define MCF5272_RAMBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
44#define MCF5272_RAMBAR_UC  (0x00000004) /* User Code Space Mask */
45#define MCF5272_RAMBAR_UD  (0x00000002) /* User Data Space Mask */
46#define MCF5272_RAMBAR_V   (0x00000001) /* Contents of RAMBAR are valid */
47
48/* MBAR - Module Base Address Register */
49#define MCF5272_MBAR_BA  (0xffff0000) /* Base Address */
50#define MCF5272_MBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
51#define MCF5272_MBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
52#define MCF5272_MBAR_UC  (0x00000004) /* User Code Space Mask */
53#define MCF5272_MBAR_UD  (0x00000002) /* User Data Space Mask */
54#define MCF5272_MBAR_V   (0x00000001) /* Contents of MBAR are valid */
55
56/* CACR - Cache Control Register */
57#define MCF5272_CACR_CENB  (0x80000000) /* Cache Enable */
58#define MCF5272_CACR_CPDI  (0x10000000) /* Disable CPUSHL Invalidation */
59#define MCF5272_CACR_CFRZ  (0x08000000) /* Cache Freeze */
60#define MCF5272_CACR_CINV  (0x01000000) /* Cache Invalidate */
61#define MCF5272_CACR_CEIB  (0x00000400) /* Cache Enable Noncacheable
62                                           instruction bursting */
63#define MCF5272_CACR_DCM   (0x00000200) /* Default cache mode - noncacheable*/
64#define MCF5272_CACR_DBWE  (0x00000100) /* Default Buffered Write Enable */
65#define MCF5272_CACR_DWP   (0x00000020) /* Default Write Protection */
66#define MCF5272_CACR_CLNF  (0x00000003) /* Cache Line Fill */
67
68/* ACRx - Cache Access Control Registers */
69#define MCF5272_ACR_BA        (0xff000000) /* Address Base */
70#define MCF5272_ACR_BAM       (0x00ff0000) /* Address Mask */
71#define MCF5272_ACR_EN        (0x00008000) /* Enable */
72#define MCF5272_ACR_SM_USR    (0x00000000) /* Match if user mode */
73#define MCF5272_ACR_SM_SVR    (0x00002000) /* Match if supervisor mode */
74#define MCF5272_ACR_SM_ANY    (0x00004000) /* Match Always */
75#define MCF527_ACR_CM         (0x00000040) /* Cache Mode (1 - noncacheable) */
76#define MCF5272_ACR_BWE       (0x00000020) /* Buffered Write Enable */
77#define MCF5272_ACR_WP        (0x00000004) /* Write Protect */
78#define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA)
79#define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM)
80
81
82#define MCF5272_ICR1_INT1_PI     (bit(31))
83#define MCF5272_ICR1_INT1_IPL(x) ((x) << 28)
84#define MCF5272_ICR1_INT1_MASK   ((7) << 28)
85#define MCF5272_ICR1_INT2_PI     (bit(27))
86#define MCF5272_ICR1_INT2_IPL(x) ((x) << 24)
87#define MCF5272_ICR1_INT2_MASK   ((7) << 24)
88#define MCF5272_ICR1_INT3_PI     (bit(23))
89#define MCF5272_ICR1_INT3_IPL(x) ((x) << 20)
90#define MCF5272_ICR1_INT3_MASK   ((7) << 20)
91#define MCF5272_ICR1_INT3_PI     (bit(19))
92#define MCF5272_ICR1_INT3_IPL(x) ((x) << 16)
93#define MCF5272_ICR1_INT3_MASK   ((7) << 16)
94#define MCF5272_ICR1_TMR0_PI     (bit(15))
95#define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12)
96#define MCF5272_ICR1_TMR0_MASK   ((7) << 12)
97#define MCF5272_ICR1_TMR1_PI     (bit(11))
98#define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8)
99#define MCF5272_ICR1_TMR1_MASK   ((7) << 8)
100#define MCF5272_ICR1_TMR2_PI     (bit(7))
101#define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4)
102#define MCF5272_ICR1_TMR2_MASK   ((7) << 4)
103#define MCF5272_ICR1_TMR3_PI     (bit(3))
104#define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0)
105#define MCF5272_ICR1_TMR3_MASK   ((7) << 0)
106
107#define MCF5272_ICR3_USB4_PI     (bit(31))
108#define MCF5272_ICR3_USB4_IPL(x) ((x) << 28)
109#define MCF5272_ICR3_USB4_MASK   ((7) << 28)
110#define MCF5272_ICR3_USB5_PI     (bit(27))
111#define MCF5272_ICR3_USB5_IPL(x) ((x) << 24)
112#define MCF5272_ICR3_USB5_MASK   ((7) << 24)
113#define MCF5272_ICR3_USB6_PI     (bit(23))
114#define MCF5272_ICR3_USB6_IPL(x) ((x) << 20)
115#define MCF5272_ICR3_USB6_MASK   ((7) << 20)
116#define MCF5272_ICR3_USB7_PI     (bit(19))
117#define MCF5272_ICR3_USB7_IPL(x) ((x) << 16)
118#define MCF5272_ICR3_USB7_MASK   ((7) << 16)
119#define MCF5272_ICR3_DMA_PI     (bit(15))
120#define MCF5272_ICR3_DMA_IPL(x) ((x) << 12)
121#define MCF5272_ICR3_DMA_MASK   ((7) << 12)
122#define MCF5272_ICR3_ERX_PI     (bit(11))
123#define MCF5272_ICR3_ERX_IPL(x) ((x) << 8)
124#define MCF5272_ICR3_ERX_MASK   ((7) << 8)
125#define MCF5272_ICR3_ETX_PI     (bit(7))
126#define MCF5272_ICR3_ETX_IPL(x) ((x) << 4)
127#define MCF5272_ICR3_ETX_MASK   ((7) << 4)
128#define MCF5272_ICR3_ENTC_PI     (bit(3))
129#define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0)
130#define MCF5272_ICR3_ENTC_MASK   ((7) << 0)
131
132
133#define MCF5272_USR_RB        (bit(7))
134#define MCF5272_USR_FE        (bit(6))
135#define MCF5272_USR_PE        (bit(5))
136#define MCF5272_USR_OE        (bit(4))
137#define MCF5272_USR_TXEMP     (bit(3))
138#define MCF5272_USR_TXRDY     (bit(2))
139#define MCF5272_USR_FFULL     (bit(1))
140#define MCF5272_USR_RXRDY     (bit(0))
141
142#define MCF5272_TMR_PS_MASK     0xff00
143#define MCF5272_TMR_PS_SHIFT    8
144#define MCF5272_TMR_CE_DISABLE  (0 << 6)
145#define MCF5272_TMR_CE_RISING   (1 << 6)
146#define MCF5272_TMR_CE_FALLING  (2 << 6)
147#define MCF5272_TMR_CE_ANY      (3 << 6)
148#define MCF5272_TMR_OM          (bit(5))
149#define MCF5272_TMR_ORI         (bit(4))
150#define MCF5272_TMR_FRR         (bit(3))
151#define MCF5272_TMR_CLK_STOP    (0 << 1)
152#define MCF5272_TMR_CLK_MSTR    (1 << 1)
153#define MCF5272_TMR_CLK_MSTR16  (2 << 1)
154#define MCF5272_TMR_CLK_TIN     (3 << 1)
155#define MCF5272_TMR_RST         (bit(0))
156#define MCF5272_TER_REF (bit(1))
157#define MCF5272_TER_CAP (bit(0))
158
159#define MCF5272_SCR_PRI         (bit(8))
160#define MCF5272_SCR_AR          (bit(7))
161#define MCF5272_SCR_SRST        (bit(6))
162#define MCF5272_SCR_BUSLOCK     (bit(3))
163#define MCF5272_SCR_HWR_128     (0)
164#define MCF5272_SCR_HWR_256     (1)
165#define MCF5272_SCR_HWR_512     (2)
166#define MCF5272_SCR_HWR_1024    (3)
167#define MCF5272_SCR_HWR_2048    (4)
168#define MCF5272_SCR_HWR_4096    (5)
169#define MCF5272_SCR_HWR_8192    (6)
170#define MCF5272_SCR_HWR_16384   (7)
171
172#define MCF5272_SPR_ADC         (bit(15))
173#define MCF5272_SPR_WPV         (bit(15))
174#define MCF5272_SPR_SMV         (bit(15))
175#define MCF5272_SPR_PE          (bit(15))
176#define MCF5272_SPR_HWT         (bit(15))
177#define MCF5272_SPR_RPV         (bit(15))
178#define MCF5272_SPR_EXT         (bit(15))
179#define MCF5272_SPR_SUV         (bit(15))
180#define MCF5272_SPR_ADCEN       (bit(15))
181#define MCF5272_SPR_WPVEN       (bit(15))
182#define MCF5272_SPR_SMVEN       (bit(15))
183#define MCF5272_SPR_PEEN        (bit(15))
184#define MCF5272_SPR_HWTEN       (bit(15))
185#define MCF5272_SPR_RPVEN       (bit(15))
186#define MCF5272_SPR_EXTEN       (bit(15))
187#define MCF5272_SPR_SUVEN       (bit(15))
188
189#define MCF5272_ENET_TX_RT      (bit(25))
190#define MCF5272_ENET_ETHERN_EN  (bit(1))
191#define MCF5272_ENET_RESET      (bit(0))
192
193#define MCF5272_ENET_EIR_HBERR  (bit(31))
194#define MCF5272_ENET_EIR_BABR   (bit(30))
195#define MCF5272_ENET_EIR_BABT   (bit(29))
196#define MCF5272_ENET_EIR_GRA    (bit(28))
197#define MCF5272_ENET_EIR_TXF    (bit(27))
198#define MCF5272_ENET_EIR_TXB    (bit(26))
199#define MCF5272_ENET_EIR_RXF    (bit(25))
200#define MCF5272_ENET_EIR_RXB    (bit(24))
201#define MCF5272_ENET_EIR_MII    (bit(23))
202#define MCF5272_ENET_EIR_EBERR  (bit(22))
203#define MCF5272_ENET_EIR_UMINT  (bit(21))
204
205#define MCF5272_ENET_RCR_PROM   (bit(3))
206#define MCF5272_ENET_RCR_MII    (bit(2))
207#define MCF5272_ENET_RCR_DRT    (bit(1))
208#define MCF5272_ENET_RCR_LOOP   (bit(0))
209
210#define MCF5272_ENET_TCR_FDEN   (bit(2))
211#define MCF5272_ENET_TCR_HBC    (bit(1))
212#define MCF5272_ENET_TCR_GTS    (bit(0))
213
214
215#ifndef ASM
216typedef struct {
217    volatile uint32_t mbar;       /* READ ONLY!! */
218
219    volatile uint16_t scr;
220    volatile uint16_t _res0;
221
222    volatile uint16_t _res1;
223    volatile uint16_t spr;
224
225    volatile uint32_t pmr;
226
227    volatile uint16_t _res2;
228    volatile uint16_t alpr;
229
230    volatile uint32_t dir;
231} sim_regs_t;
232
233typedef struct {
234    volatile uint32_t icr1;
235    volatile uint32_t icr2;
236    volatile uint32_t icr3;
237    volatile uint32_t icr4;
238    volatile uint32_t isr;
239    volatile uint32_t pitr;
240    volatile uint32_t piwr;
241    volatile uint8_t  _res0[3];
242    volatile uint8_t  pivr;
243} intctrl_regs_t;
244
245typedef struct {
246    volatile uint32_t csbr0;
247    volatile uint32_t csor0;
248    volatile uint32_t csbr1;
249    volatile uint32_t csor1;
250    volatile uint32_t csbr2;
251    volatile uint32_t csor2;
252    volatile uint32_t csbr3;
253    volatile uint32_t csor3;
254    volatile uint32_t csbr4;
255    volatile uint32_t csor4;
256    volatile uint32_t csbr5;
257    volatile uint32_t csor5;
258    volatile uint32_t csbr6;
259    volatile uint32_t csor6;
260    volatile uint32_t csbr7;
261    volatile uint32_t csor7;
262} chipsel_regs_t;
263
264typedef struct {
265    volatile uint32_t pacnt;
266
267    volatile uint16_t paddr;
268    volatile uint16_t _res0;
269
270    volatile uint16_t _res1;
271    volatile uint16_t padat;
272
273    volatile uint32_t pbcnt;
274
275    volatile uint16_t pbddr;
276    volatile uint16_t _res2;
277
278    volatile uint16_t _res3;
279    volatile uint16_t pbdat;
280
281    volatile uint16_t pcddr;
282    volatile uint16_t _res4;
283
284    volatile uint16_t _res5;
285    volatile uint16_t pcdat;
286
287    volatile uint32_t pdcnt;
288} gpio_regs_t;
289
290typedef struct {
291    volatile uint32_t qmr;
292    volatile uint32_t qdlyr;
293    volatile uint32_t qwr;
294    volatile uint32_t qir;
295    volatile uint32_t qar;
296    volatile uint32_t qdr;
297} qspi_regs_t;
298
299typedef struct {
300    volatile uint8_t pwcr1;
301    volatile uint8_t _res0[3];
302
303    volatile uint8_t pwcr2;
304    volatile uint8_t _res1[3];
305
306    volatile uint8_t pwcr3;
307    volatile uint8_t _res2[3];
308
309    volatile uint8_t pwwd1;
310    volatile uint8_t _res3[3];
311
312    volatile uint8_t pwwd2;
313    volatile uint8_t _res4[3];
314
315    volatile uint8_t pwwd3;
316    volatile uint8_t _res5[3];
317} pwm_regs_t;
318
319typedef struct {
320    volatile uint32_t dcmr;
321
322    volatile uint16_t _res0;
323    volatile uint16_t dcir;
324
325    volatile uint32_t dbcr;
326
327    volatile uint32_t dsar;
328
329    volatile uint32_t ddar;
330} dma_regs_t;
331
332typedef struct {
333    volatile uint8_t umr;              /* 0x000 */
334    volatile uint8_t _res0[3];
335
336    volatile uint8_t ucsr;             /* 0x004 */
337    volatile uint8_t _res2[3];
338
339    volatile uint8_t ucr;              /* 0x008 */
340    volatile uint8_t _res3[3];
341
342    volatile uint8_t udata;            /* 0x00c */
343    volatile uint8_t _res4[3];
344
345    volatile uint8_t uccr;             /* 0x010 */
346    volatile uint8_t _res6[3];
347
348    volatile uint8_t uisr;             /* 0x014 */
349    volatile uint8_t _res8[3];
350
351    volatile uint8_t ubg1;             /* 0x018 */
352    volatile uint8_t _res10[3];
353
354    volatile uint8_t ubg2;             /* 0x01c */
355    volatile uint8_t _res11[3];
356
357    volatile uint8_t uabr1;            /* 0x020 */
358    volatile uint8_t _res12[3];
359
360    volatile uint8_t uabr2;            /* 0x024 */
361    volatile uint8_t _res13[3];
362
363    volatile uint8_t utxfcsr;          /* 0x028 */
364    volatile uint8_t _res14[3];
365
366    volatile uint8_t urxfcsr;          /* 0x02c */
367    volatile uint8_t _res15[3];
368
369    volatile uint8_t ufpdn;            /* 0x030 */
370    volatile uint8_t _res16[3];
371
372    volatile uint8_t uip;              /* 0x034 */
373    volatile uint8_t _res17[3];
374
375    volatile uint8_t uop1;             /* 0x038 */
376    volatile uint8_t _res18[3];
377
378    volatile uint8_t uop0;             /* 0x03c */
379    volatile uint8_t _res19[3];
380} uart_regs_t;
381
382typedef struct {
383    volatile uint16_t tmr0;
384    volatile uint16_t _res0;
385
386    volatile uint16_t trr0;
387    volatile uint16_t _res1;
388
389    volatile uint16_t tcap0;
390    volatile uint16_t _res2;
391
392    volatile uint16_t tcn0;
393    volatile uint16_t _res3;
394
395    volatile uint16_t ter0;
396    volatile uint16_t _res4;
397
398    volatile uint8_t  _res40[12];
399
400    volatile uint16_t tmr1;
401    volatile uint16_t _res5;
402
403    volatile uint16_t trr1;
404    volatile uint16_t _res6;
405
406    volatile uint16_t tcap1;
407    volatile uint16_t _res7;
408
409    volatile uint16_t tcn1;
410    volatile uint16_t _res8;
411
412    volatile uint16_t ter1;
413    volatile uint16_t _res9;
414
415    volatile uint8_t  _res91[12];
416
417    volatile uint16_t tmr2;
418    volatile uint16_t _res10;
419
420    volatile uint16_t trr2;
421    volatile uint16_t _res11;
422
423    volatile uint16_t tcap2;
424    volatile uint16_t _res12;
425
426    volatile uint16_t tcn2;
427    volatile uint16_t _res13;
428
429    volatile uint16_t ter2;
430    volatile uint16_t _res14;
431
432    volatile uint8_t  _res140[12];
433
434    volatile uint16_t tmr3;
435    volatile uint16_t _res15;
436
437    volatile uint16_t trr3;
438    volatile uint16_t _res16;
439
440    volatile uint16_t tcap3;
441    volatile uint16_t _res17;
442
443    volatile uint16_t tcn3;
444    volatile uint16_t _res18;
445
446    volatile uint16_t ter3;
447    volatile uint16_t _res19;
448
449    volatile uint8_t  _res190[12];
450
451    volatile uint16_t wrrr;
452    volatile uint16_t _res20;
453
454    volatile uint16_t wirr;
455    volatile uint16_t _res21;
456
457    volatile uint16_t wcr;
458    volatile uint16_t _res22;
459
460    volatile uint16_t wer;
461    volatile uint16_t _res23;
462} timer_regs_t;
463
464typedef struct {
465    volatile uint32_t p0b1rr;
466    volatile uint32_t p1b1rr;
467    volatile uint32_t p2b1rr;
468    volatile uint32_t p3b1rr;
469    volatile uint32_t p0b2rr;
470    volatile uint32_t p1b2rr;
471    volatile uint32_t p2b2rr;
472    volatile uint32_t p3b2rr;
473
474    volatile uint8_t  p0drr;
475    volatile uint8_t  p1drr;
476    volatile uint8_t  p2drr;
477    volatile uint8_t  p3drr;
478
479    volatile uint32_t p0b1tr;
480    volatile uint32_t p1b1tr;
481    volatile uint32_t p2b1tr;
482    volatile uint32_t p3b1tr;
483    volatile uint32_t p0b2tr;
484    volatile uint32_t p1b2tr;
485    volatile uint32_t p2b2tr;
486    volatile uint32_t p3b2tr;
487
488    volatile uint8_t  p0dtr;
489    volatile uint8_t  p1dtr;
490    volatile uint8_t  p2dtr;
491    volatile uint8_t  p3dtr;
492
493    volatile uint16_t p0cr;
494    volatile uint16_t p1cr;
495    volatile uint16_t p2cr;
496    volatile uint16_t p3cr;
497    volatile uint16_t p0icr;
498    volatile uint16_t p1icr;
499    volatile uint16_t p2icr;
500    volatile uint16_t p3icr;
501    volatile uint16_t p0gmr;
502    volatile uint16_t p1gmr;
503    volatile uint16_t p2gmr;
504    volatile uint16_t p3gmr;
505    volatile uint16_t p0gmt;
506    volatile uint16_t p1gmt;
507    volatile uint16_t p2gmt;
508    volatile uint16_t p3gmt;
509
510    volatile uint8_t  _res0;
511    volatile uint8_t  pgmts;
512    volatile uint8_t  pgmta;
513    volatile uint8_t  _res1;
514    volatile uint8_t  p0gcir;
515    volatile uint8_t  p1gcir;
516    volatile uint8_t  p2gcir;
517    volatile uint8_t  p3gcir;
518    volatile uint8_t  p0gcit;
519    volatile uint8_t  p1gcit;
520    volatile uint8_t  p2gcit;
521    volatile uint8_t  p3gcit;
522    volatile uint8_t  _res3[3];
523    volatile uint8_t  pgcitsr;
524    volatile uint8_t  _res4[3];
525    volatile uint8_t  pdcsr;
526
527    volatile uint16_t p0psr;
528    volatile uint16_t p1psr;
529    volatile uint16_t p2psr;
530    volatile uint16_t p3psr;
531    volatile uint16_t pasr;
532    volatile uint8_t  _res5;
533    volatile uint8_t  plcr;
534    volatile uint16_t _res6;
535    volatile uint16_t pdrqr;
536    volatile uint16_t p0sdr;
537    volatile uint16_t p1sdr;
538    volatile uint16_t p2sdr;
539    volatile uint16_t p3sdr;
540    volatile uint16_t _res7;
541    volatile uint16_t pcsr;
542} plic_regs_t;
543
544typedef struct {
545    volatile uint32_t ecr;
546    volatile uint32_t eir;
547    volatile uint32_t eimr;
548    volatile uint32_t ivsr;
549    volatile uint32_t rdar;
550    volatile uint32_t tdar;
551    volatile uint32_t _res0[10];
552    volatile uint32_t mmfr;
553    volatile uint32_t mscr;
554    volatile uint32_t _res1[17];
555    volatile uint32_t frbr;
556    volatile uint32_t frsr;
557    volatile uint32_t _res2[4];
558    volatile uint32_t tfwr;
559    volatile uint32_t _res3[1];
560    volatile uint32_t tfsr;
561    volatile uint32_t _res4[21];
562    volatile uint32_t rcr;
563    volatile uint32_t mflr;
564    volatile uint32_t _res5[14];
565    volatile uint32_t tcr;
566    volatile uint32_t _res6[158];
567    volatile uint32_t malr;
568    volatile uint32_t maur;
569    volatile uint32_t htur;
570    volatile uint32_t htlr;
571    volatile uint32_t erdsr;
572    volatile uint32_t etdsr;
573    volatile uint32_t emrbr;
574/*    volatile uint8_t  fifo[448]; */
575} enet_regs_t;
576
577typedef struct {
578    volatile uint16_t _res0;
579    volatile uint16_t fnr;
580    volatile uint16_t _res1;
581    volatile uint16_t fnmr;
582    volatile uint16_t _res2;
583    volatile uint16_t rfmr;
584    volatile uint16_t _res3;
585    volatile uint16_t rfmmr;
586    volatile uint8_t  _res4[3];
587    volatile uint8_t  far;
588    volatile uint32_t asr;
589    volatile uint32_t drr1;
590    volatile uint32_t drr2;
591    volatile uint16_t _res5;
592    volatile uint16_t specr;
593    volatile uint16_t _res6;
594    volatile uint16_t ep0sr;
595
596    volatile uint32_t iep0cfg;
597    volatile uint32_t oep0cfg;
598    volatile uint32_t ep1cfg;
599    volatile uint32_t ep2cfg;
600    volatile uint32_t ep3cfg;
601    volatile uint32_t ep4cfg;
602    volatile uint32_t ep5cfg;
603    volatile uint32_t ep6cfg;
604    volatile uint32_t ep7cfg;
605    volatile uint32_t ep0ctl;
606
607    volatile uint16_t _res7;
608    volatile uint16_t ep1ctl;
609    volatile uint16_t _res8;
610    volatile uint16_t ep2ctl;
611    volatile uint16_t _res9;
612    volatile uint16_t ep3ctl;
613    volatile uint16_t _res10;
614    volatile uint16_t ep4ctl;
615    volatile uint16_t _res11;
616    volatile uint16_t ep5ctl;
617    volatile uint16_t _res12;
618    volatile uint16_t ep6ctl;
619    volatile uint16_t _res13;
620    volatile uint16_t ep7ctl;
621
622    volatile uint32_t ep0isr;
623
624    volatile uint16_t _res14;
625    volatile uint16_t ep1isr;
626    volatile uint16_t _res15;
627    volatile uint16_t ep2isr;
628    volatile uint16_t _res16;
629    volatile uint16_t ep3isr;
630    volatile uint16_t _res17;
631    volatile uint16_t ep4isr;
632    volatile uint16_t _res18;
633    volatile uint16_t ep5isr;
634    volatile uint16_t _res19;
635    volatile uint16_t ep6isr;
636    volatile uint16_t _res20;
637    volatile uint16_t ep7isr;
638
639    volatile uint32_t ep0imr;
640
641    volatile uint16_t _res21;
642    volatile uint16_t ep1imr;
643    volatile uint16_t _res22;
644    volatile uint16_t ep2imr;
645    volatile uint16_t _res23;
646    volatile uint16_t ep3imr;
647    volatile uint16_t _res24;
648    volatile uint16_t ep4imr;
649    volatile uint16_t _res25;
650    volatile uint16_t ep5imr;
651    volatile uint16_t _res26;
652    volatile uint16_t ep6imr;
653    volatile uint16_t _res27;
654    volatile uint16_t ep7imr;
655
656    volatile uint32_t ep0dr;
657    volatile uint32_t ep1dr;
658    volatile uint32_t ep2dr;
659    volatile uint32_t ep3dr;
660    volatile uint32_t ep4dr;
661    volatile uint32_t ep5dr;
662    volatile uint32_t ep6dr;
663    volatile uint32_t ep7dr;
664
665    volatile uint16_t _res28;
666    volatile uint16_t ep0dpr;
667    volatile uint16_t _res29;
668    volatile uint16_t ep1dpr;
669    volatile uint16_t _res30;
670    volatile uint16_t ep2dpr;
671    volatile uint16_t _res31;
672    volatile uint16_t ep3dpr;
673    volatile uint16_t _res32;
674    volatile uint16_t ep4dpr;
675    volatile uint16_t _res33;
676    volatile uint16_t ep5dpr;
677    volatile uint16_t _res34;
678    volatile uint16_t ep6dpr;
679    volatile uint16_t _res35;
680    volatile uint16_t ep7dpr;
681/*    uint8_t  ram[1024]; */
682} usb_regs_t;
683
684extern intctrl_regs_t *g_intctrl_regs;
685extern chipsel_regs_t *g_chipsel_regs;
686extern gpio_regs_t *g_gpio_regs;
687extern qspi_regs_t *g_qspi_regs;
688extern pwm_regs_t *g_pwm_regs;
689extern dma_regs_t *g_dma_regs;
690extern uart_regs_t *g_uart0_regs;
691extern uart_regs_t *g_uart1_regs;
692extern timer_regs_t *g_timer_regs;
693extern plic_regs_t *g_plic_regs;
694extern enet_regs_t *g_enet_regs;
695extern usb_regs_t *g_usb_regs;
696
697#endif /* ASM */
698
699#endif /* __MCF5272_H__ */
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