[14782ec0] | 1 | /* |
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| 2 | * File: mcf5225x.h |
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| 3 | * Purpose: Register and bit definitions |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __MCF5225x_H__ |
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| 7 | #define __MCF5225x_H__ |
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| 8 | |
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| 9 | typedef volatile unsigned char vuint8; |
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| 10 | typedef volatile unsigned short vuint16; |
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| 11 | typedef volatile unsigned long vuint32; |
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| 12 | |
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| 13 | /********************************************************************* |
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| 14 | * |
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| 15 | * System Control Module (SCM) |
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| 16 | * |
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| 17 | *********************************************************************/ |
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| 18 | |
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| 19 | /* Register read/write macros */ |
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| 20 | #define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) |
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| 21 | #define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) |
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| 22 | #define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) |
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| 23 | #define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) |
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| 24 | #define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) |
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| 25 | #define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) |
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| 26 | #define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) |
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| 27 | #define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) |
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| 28 | #define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) |
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| 29 | #define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) |
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| 30 | #define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) |
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| 31 | #define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) |
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| 32 | #define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) |
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| 33 | #define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) |
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| 34 | #define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) |
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| 35 | #define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) |
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| 36 | #define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) |
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| 37 | #define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) |
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| 38 | #define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) |
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| 39 | #define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) |
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| 40 | #define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) |
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| 41 | #define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) |
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| 42 | #define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) |
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| 43 | #define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) |
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| 44 | |
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| 45 | /* Bit definitions and macros for MCF_SCM_IPSBAR */ |
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| 46 | #define MCF_SCM_IPSBAR_V (0x00000001) |
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| 47 | #define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) |
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| 48 | |
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| 49 | /* Bit definitions and macros for MCF_SCM_RAMBAR */ |
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| 50 | #define MCF_SCM_RAMBAR_BDE (0x00000200) |
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| 51 | #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) |
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| 52 | |
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| 53 | /* Bit definitions and macros for MCF_SCM_CRSR */ |
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| 54 | #define MCF_SCM_CRSR_CWDR (0x20) |
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| 55 | #define MCF_SCM_CRSR_EXT (0x80) |
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| 56 | |
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| 57 | /* Bit definitions and macros for MCF_SCM_CWCR */ |
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| 58 | #define MCF_SCM_CWCR_CWTIC (0x01) |
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| 59 | #define MCF_SCM_CWCR_CWTAVAL (0x02) |
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| 60 | #define MCF_SCM_CWCR_CWTA (0x04) |
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| 61 | #define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) |
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| 62 | #define MCF_SCM_CWCR_CWRI (0x40) |
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| 63 | #define MCF_SCM_CWCR_CWE (0x80) |
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| 64 | |
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| 65 | /* Bit definitions and macros for MCF_SCM_LPICR */ |
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| 66 | #define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) |
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| 67 | #define MCF_SCM_LPICR_ENBSTOP (0x80) |
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| 68 | |
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| 69 | /* Bit definitions and macros for MCF_SCM_CWSR */ |
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| 70 | #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) |
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| 71 | |
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| 72 | /* Bit definitions and macros for MCF_SCM_PPMRH */ |
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| 73 | #define MCF_SCM_PPMRH_CDPORTS (0x00000001) |
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| 74 | #define MCF_SCM_PPMRH_CDEPORT (0x00000002) |
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| 75 | #define MCF_SCM_PPMRH_CDPIT0 (0x00000008) |
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| 76 | #define MCF_SCM_PPMRH_CDPIT1 (0x00000010) |
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| 77 | #define MCF_SCM_PPMRH_CDCAN (0x00000020) |
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| 78 | #define MCF_SCM_PPMRH_CDADC (0x00000080) |
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| 79 | #define MCF_SCM_PPMRH_CDGPT (0x00000100) |
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| 80 | #define MCF_SCM_PPMRH_CDPWN (0x00000200) |
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| 81 | #define MCF_SCM_PPMRH_CDFCAN (0x00000400) |
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| 82 | #define MCF_SCM_PPMRH_CDCFM (0x00000800) |
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| 83 | |
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| 84 | /* Bit definitions and macros for MCF_SCM_PPMRL */ |
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| 85 | #define MCF_SCM_PPMRL_CDG (0x00000002) |
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| 86 | #define MCF_SCM_PPMRL_CDEIM (0x00000008) |
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| 87 | #define MCF_SCM_PPMRL_CDDMA (0x00000010) |
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| 88 | #define MCF_SCM_PPMRL_CDUART0 (0x00000020) |
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| 89 | #define MCF_SCM_PPMRL_CDUART1 (0x00000040) |
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| 90 | #define MCF_SCM_PPMRL_CDUART2 (0x00000080) |
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| 91 | #define MCF_SCM_PPMRL_CDI2C0 (0x00000200) |
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| 92 | #define MCF_SCM_PPMRL_CDI2C1 (0x00000800) |
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| 93 | #define MCF_SCM_PPMRL_CDQSPI (0x00000400) |
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| 94 | #define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) |
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| 95 | #define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) |
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| 96 | #define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) |
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| 97 | #define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) |
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| 98 | #define MCF_SCM_PPMRL_CDINTC0 (0x00020000) |
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| 99 | #define MCF_SCM_PPMRL_CDINTC1 (0x00040000) |
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| 100 | #define MCF_SCM_PPMRL_CDFEC (0x00200000) |
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| 101 | |
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| 102 | /* Bit definitions and macros for MCF_SCM_MPARK */ |
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| 103 | #define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) |
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| 104 | #define MCF_SCM_MPARK_PRKLAST (0x00001000) |
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| 105 | #define MCF_SCM_MPARK_TIMEOUT (0x00002000) |
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| 106 | #define MCF_SCM_MPARK_FIXED (0x00004000) |
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| 107 | #define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) |
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| 108 | #define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) |
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| 109 | #define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) |
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| 110 | #define MCF_SCM_MPARK_BCR24BIT (0x01000000) |
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| 111 | #define MCF_SCM_MPARK_M2_P_EN (0x02000000) |
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| 112 | |
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| 113 | /* Bit definitions and macros for MCF_SCM_PPMRS */ |
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| 114 | #define MCF_SCM_PPMRS_DISABLE_ALL (64) |
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| 115 | #define MCF_SCM_PPMRS_DISABLE_CFM (43) |
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| 116 | #define MCF_SCM_PPMRS_DISABLE_CAN (42) |
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| 117 | #define MCF_SCM_PPMRS_DISABLE_PWM (41) |
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| 118 | #define MCF_SCM_PPMRS_DISABLE_GPT (40) |
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| 119 | #define MCF_SCM_PPMRS_DISABLE_ADC (39) |
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| 120 | #define MCF_SCM_PPMRS_DISABLE_PIT1 (36) |
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| 121 | #define MCF_SCM_PPMRS_DISABLE_PIT0 (35) |
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| 122 | #define MCF_SCM_PPMRS_DISABLE_EPORT (33) |
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| 123 | #define MCF_SCM_PPMRS_DISABLE_PORTS (32) |
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| 124 | #define MCF_SCM_PPMRS_DISABLE_INTC (17) |
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| 125 | #define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) |
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| 126 | #define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) |
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| 127 | #define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) |
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| 128 | #define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) |
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| 129 | #define MCF_SCM_PPMRS_DISABLE_QSPI (10) |
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| 130 | #define MCF_SCM_PPMRS_DISABLE_I2C (9) |
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| 131 | #define MCF_SCM_PPMRS_DISABLE_UART2 (7) |
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| 132 | #define MCF_SCM_PPMRS_DISABLE_UART1 (6) |
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| 133 | #define MCF_SCM_PPMRS_DISABLE_UART0 (5) |
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| 134 | #define MCF_SCM_PPMRS_DISABLE_DMA (4) |
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| 135 | #define MCF_SCM_PPMRS_SET_CDG (1) |
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| 136 | |
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| 137 | /* Bit definitions and macros for MCF_SCM_PPMRC */ |
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| 138 | #define MCF_SCM_PPMRC_ENABLE_ALL (64) |
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| 139 | #define MCF_SCM_PPMRC_ENABLE_CFM (43) |
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| 140 | #define MCF_SCM_PPMRC_ENABLE_CAN (42) |
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| 141 | #define MCF_SCM_PPMRC_ENABLE_PWM (41) |
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| 142 | #define MCF_SCM_PPMRC_ENABLE_GPT (40) |
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| 143 | #define MCF_SCM_PPMRC_ENABLE_ADC (39) |
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| 144 | #define MCF_SCM_PPMRC_ENABLE_PIT1 (36) |
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| 145 | #define MCF_SCM_PPMRC_ENABLE_PIT0 (35) |
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| 146 | #define MCF_SCM_PPMRC_ENABLE_EPORT (33) |
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| 147 | #define MCF_SCM_PPMRC_ENABLE_PORTS (32) |
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| 148 | #define MCF_SCM_PPMRC_ENABLE_INTC (17) |
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| 149 | #define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) |
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| 150 | #define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) |
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| 151 | #define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) |
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| 152 | #define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) |
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| 153 | #define MCF_SCM_PPMRC_ENABLE_QSPI (10) |
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| 154 | #define MCF_SCM_PPMRC_ENABLE_I2C (9) |
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| 155 | #define MCF_SCM_PPMRC_ENABLE_UART2 (7) |
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| 156 | #define MCF_SCM_PPMRC_ENABLE_UART1 (6) |
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| 157 | #define MCF_SCM_PPMRC_ENABLE_UART0 (5) |
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| 158 | #define MCF_SCM_PPMRC_ENABLE_DMA (4) |
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| 159 | #define MCF_SCM_PPMRC_CLEAR_CDG (1) |
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| 160 | |
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| 161 | |
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| 162 | /********************************************************************* |
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| 163 | * |
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| 164 | * Power Management Module (PMM) |
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| 165 | * |
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| 166 | *********************************************************************/ |
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| 167 | |
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| 168 | /* Register read/write macros */ |
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| 169 | #define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) |
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| 170 | #define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) |
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| 171 | #define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) |
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| 172 | #define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) |
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| 173 | |
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| 174 | /* Bit definitions and macros for MCF_PMM_PPMRH */ |
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| 175 | #define MCF_PMM_PPMRH_CDPORTS (0x00000001) |
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| 176 | #define MCF_PMM_PPMRH_CDEPORT (0x00000002) |
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| 177 | #define MCF_PMM_PPMRH_CDPIT0 (0x00000008) |
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| 178 | #define MCF_PMM_PPMRH_CDPIT1 (0x00000010) |
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| 179 | #define MCF_PMM_PPMRH_CDADC (0x00000080) |
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| 180 | #define MCF_PMM_PPMRH_CDGPT (0x00000100) |
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| 181 | #define MCF_PMM_PPMRH_CDPWM (0x00000200) |
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| 182 | #define MCF_PMM_PPMRH_CDFCAN (0x00000400) |
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| 183 | #define MCF_PMM_PPMRH_CDCFM (0x00000800) |
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| 184 | |
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| 185 | /* Bit definitions and macros for MCF_PMM_PPMRL */ |
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| 186 | #define MCF_PMM_PPMRL_CDG (0x00000002) |
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| 187 | #define MCF_PMM_PPMRL_CDEIM (0x00000008) |
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| 188 | #define MCF_PMM_PPMRL_CDDMA (0x00000010) |
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| 189 | #define MCF_PMM_PPMRL_CDUART0 (0x00000020) |
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| 190 | #define MCF_PMM_PPMRL_CDUART1 (0x00000040) |
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| 191 | #define MCF_PMM_PPMRL_CDUART2 (0x00000080) |
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| 192 | #define MCF_PMM_PPMRL_CDI2C (0x00000200) |
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| 193 | #define MCF_PMM_PPMRL_CDQSPI (0x00000400) |
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| 194 | #define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) |
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| 195 | #define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) |
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| 196 | #define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) |
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| 197 | #define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) |
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| 198 | #define MCF_PMM_PPMRL_CDINTC0 (0x00020000) |
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| 199 | |
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| 200 | /* Bit definitions and macros for MCF_PMM_LPICR */ |
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| 201 | #define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) |
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| 202 | #define MCF_PMM_LPICR_ENBSTOP (0x80) |
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| 203 | |
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| 204 | /* Bit definitions and macros for MCF_PMM_LPCR */ |
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| 205 | #define MCF_PMM_LPCR_LVDSE (0x02) |
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| 206 | #define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) |
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| 207 | #define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) |
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| 208 | #define MCF_PMM_LPCR_LPMD_STOP (0xC0) |
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| 209 | #define MCF_PMM_LPCR_LPMD_WAIT (0x80) |
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| 210 | #define MCF_PMM_LPCR_LPMD_DOZE (0x40) |
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| 211 | #define MCF_PMM_LPCR_LPMD_RUN (0x00) |
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| 212 | |
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| 213 | |
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| 214 | /********************************************************************* |
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| 215 | * |
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| 216 | * DMA Controller Module (DMA) |
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| 217 | * |
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| 218 | *********************************************************************/ |
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| 219 | |
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| 220 | /* Register read/write macros */ |
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| 221 | #define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) |
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| 222 | #define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) |
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| 223 | #define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) |
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| 224 | #define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) |
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| 225 | #define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) |
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| 226 | #define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) |
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| 227 | #define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) |
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| 228 | #define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) |
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| 229 | #define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) |
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| 230 | #define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) |
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| 231 | #define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) |
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| 232 | #define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) |
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| 233 | #define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) |
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| 234 | #define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) |
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| 235 | #define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) |
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| 236 | #define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) |
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| 237 | #define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) |
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| 238 | #define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) |
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| 239 | #define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) |
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| 240 | #define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) |
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| 241 | #define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) |
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| 242 | #define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) |
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| 243 | #define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) |
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| 244 | #define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) |
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| 245 | #define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) |
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| 246 | #define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) |
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| 247 | |
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| 248 | /* Bit definitions and macros for MCF_DMA_DMAREQC */ |
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| 249 | #define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) |
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| 250 | #define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) |
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| 251 | #define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) |
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| 252 | #define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) |
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| 253 | #define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) |
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| 254 | |
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| 255 | /* Bit definitions and macros for MCF_DMA_SAR */ |
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| 256 | #define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) |
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| 257 | |
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| 258 | /* Bit definitions and macros for MCF_DMA_DAR */ |
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| 259 | #define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) |
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| 260 | |
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| 261 | /* Bit definitions and macros for MCF_DMA_DSR */ |
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| 262 | #define MCF_DMA_DSR_DONE (0x01) |
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| 263 | #define MCF_DMA_DSR_BSY (0x02) |
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| 264 | #define MCF_DMA_DSR_REQ (0x04) |
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| 265 | #define MCF_DMA_DSR_BED (0x10) |
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| 266 | #define MCF_DMA_DSR_BES (0x20) |
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| 267 | #define MCF_DMA_DSR_CE (0x40) |
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| 268 | |
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| 269 | /* Bit definitions and macros for MCF_DMA_BCR */ |
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| 270 | #define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) |
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| 271 | #define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) |
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| 272 | |
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| 273 | /* Bit definitions and macros for MCF_DMA_DCR */ |
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| 274 | #define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) |
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| 275 | #define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) |
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| 276 | #define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) |
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| 277 | #define MCF_DMA_DCR_D_REQ (0x00000080) |
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| 278 | #define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) |
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| 279 | #define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) |
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| 280 | #define MCF_DMA_DCR_START (0x00010000) |
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| 281 | #define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) |
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| 282 | #define MCF_DMA_DCR_DINC (0x00080000) |
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| 283 | #define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) |
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| 284 | #define MCF_DMA_DCR_SINC (0x00400000) |
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| 285 | #define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) |
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| 286 | #define MCF_DMA_DCR_AA (0x10000000) |
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| 287 | #define MCF_DMA_DCR_CS (0x20000000) |
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| 288 | #define MCF_DMA_DCR_EEXT (0x40000000) |
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| 289 | #define MCF_DMA_DCR_INT (0x80000000) |
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| 290 | #define MCF_DMA_DCR_BWC_16K (0x1) |
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| 291 | #define MCF_DMA_DCR_BWC_32K (0x2) |
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| 292 | #define MCF_DMA_DCR_BWC_64K (0x3) |
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| 293 | #define MCF_DMA_DCR_BWC_128K (0x4) |
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| 294 | #define MCF_DMA_DCR_BWC_256K (0x5) |
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| 295 | #define MCF_DMA_DCR_BWC_512K (0x6) |
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| 296 | #define MCF_DMA_DCR_BWC_1024K (0x7) |
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| 297 | #define MCF_DMA_DCR_DMOD_DIS (0x0) |
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| 298 | #define MCF_DMA_DCR_DMOD_16 (0x1) |
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| 299 | #define MCF_DMA_DCR_DMOD_32 (0x2) |
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| 300 | #define MCF_DMA_DCR_DMOD_64 (0x3) |
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| 301 | #define MCF_DMA_DCR_DMOD_128 (0x4) |
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| 302 | #define MCF_DMA_DCR_DMOD_256 (0x5) |
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| 303 | #define MCF_DMA_DCR_DMOD_512 (0x6) |
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| 304 | #define MCF_DMA_DCR_DMOD_1K (0x7) |
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| 305 | #define MCF_DMA_DCR_DMOD_2K (0x8) |
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| 306 | #define MCF_DMA_DCR_DMOD_4K (0x9) |
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| 307 | #define MCF_DMA_DCR_DMOD_8K (0xA) |
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| 308 | #define MCF_DMA_DCR_DMOD_16K (0xB) |
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| 309 | #define MCF_DMA_DCR_DMOD_32K (0xC) |
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| 310 | #define MCF_DMA_DCR_DMOD_64K (0xD) |
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| 311 | #define MCF_DMA_DCR_DMOD_128K (0xE) |
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| 312 | #define MCF_DMA_DCR_DMOD_256K (0xF) |
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| 313 | #define MCF_DMA_DCR_SMOD_DIS (0x0) |
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| 314 | #define MCF_DMA_DCR_SMOD_16 (0x1) |
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| 315 | #define MCF_DMA_DCR_SMOD_32 (0x2) |
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| 316 | #define MCF_DMA_DCR_SMOD_64 (0x3) |
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| 317 | #define MCF_DMA_DCR_SMOD_128 (0x4) |
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| 318 | #define MCF_DMA_DCR_SMOD_256 (0x5) |
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| 319 | #define MCF_DMA_DCR_SMOD_512 (0x6) |
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| 320 | #define MCF_DMA_DCR_SMOD_1K (0x7) |
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| 321 | #define MCF_DMA_DCR_SMOD_2K (0x8) |
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| 322 | #define MCF_DMA_DCR_SMOD_4K (0x9) |
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| 323 | #define MCF_DMA_DCR_SMOD_8K (0xA) |
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| 324 | #define MCF_DMA_DCR_SMOD_16K (0xB) |
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| 325 | #define MCF_DMA_DCR_SMOD_32K (0xC) |
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| 326 | #define MCF_DMA_DCR_SMOD_64K (0xD) |
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| 327 | #define MCF_DMA_DCR_SMOD_128K (0xE) |
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| 328 | #define MCF_DMA_DCR_SMOD_256K (0xF) |
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| 329 | #define MCF_DMA_DCR_SSIZE_LONG (0x0) |
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| 330 | #define MCF_DMA_DCR_SSIZE_BYTE (0x1) |
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| 331 | #define MCF_DMA_DCR_SSIZE_WORD (0x2) |
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| 332 | #define MCF_DMA_DCR_SSIZE_LINE (0x3) |
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| 333 | #define MCF_DMA_DCR_DSIZE_LONG (0x0) |
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| 334 | #define MCF_DMA_DCR_DSIZE_BYTE (0x1) |
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| 335 | #define MCF_DMA_DCR_DSIZE_WORD (0x2) |
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| 336 | #define MCF_DMA_DCR_DSIZE_LINE (0x3) |
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| 337 | #define MCF_DMA_DCR_LCH1_CH0 (0x0) |
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| 338 | #define MCF_DMA_DCR_LCH1_CH1 (0x1) |
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| 339 | #define MCF_DMA_DCR_LCH1_CH2 (0x2) |
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| 340 | #define MCF_DMA_DCR_LCH1_CH3 (0x3) |
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| 341 | #define MCF_DMA_DCR_LCH2_CH0 (0x0) |
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| 342 | #define MCF_DMA_DCR_LCH2_CH1 (0x1) |
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| 343 | #define MCF_DMA_DCR_LCH2_CH2 (0x2) |
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| 344 | #define MCF_DMA_DCR_LCH2_CH3 (0x3) |
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| 345 | |
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| 346 | |
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| 347 | /********************************************************************* |
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| 348 | * |
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| 349 | * Universal Asynchronous Receiver Transmitter (UART) |
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| 350 | * |
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| 351 | *********************************************************************/ |
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| 352 | |
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| 353 | /* Register read/write macros */ |
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| 354 | #define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) |
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| 355 | #define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) |
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| 356 | #define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) |
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| 357 | #define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) |
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| 358 | #define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) |
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| 359 | #define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) |
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| 360 | #define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) |
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| 361 | #define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) |
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| 362 | #define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) |
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| 363 | #define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) |
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| 364 | #define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) |
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| 365 | #define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) |
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| 366 | #define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) |
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| 367 | #define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) |
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| 368 | #define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) |
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| 369 | #define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) |
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| 370 | #define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) |
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| 371 | #define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) |
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| 372 | #define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) |
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| 373 | #define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) |
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| 374 | #define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) |
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| 375 | #define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) |
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| 376 | #define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) |
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| 377 | #define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) |
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| 378 | #define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) |
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| 379 | #define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) |
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| 380 | #define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) |
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| 381 | #define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) |
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| 382 | #define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) |
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| 383 | #define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) |
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| 384 | #define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) |
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| 385 | #define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) |
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| 386 | #define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) |
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| 387 | #define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) |
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| 388 | #define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) |
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| 389 | #define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) |
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| 390 | #define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) |
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| 391 | #define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) |
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| 392 | #define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) |
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| 393 | #define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) |
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| 394 | #define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) |
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| 395 | #define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) |
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| 396 | #define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) |
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| 397 | #define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) |
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| 398 | #define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) |
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| 399 | #define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) |
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| 400 | #define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) |
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| 401 | #define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) |
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| 402 | #define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) |
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| 403 | #define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) |
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| 404 | #define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) |
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| 405 | #define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) |
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| 406 | #define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) |
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| 407 | #define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) |
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| 408 | #define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) |
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| 409 | #define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) |
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| 410 | #define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) |
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| 411 | #define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) |
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| 412 | #define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) |
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| 413 | #define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) |
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| 414 | |
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| 415 | /* Bit definitions and macros for MCF_UART_UMR */ |
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| 416 | #define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) |
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| 417 | #define MCF_UART_UMR_PT (0x04) |
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| 418 | #define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) |
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| 419 | #define MCF_UART_UMR_ERR (0x20) |
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| 420 | #define MCF_UART_UMR_RXIRQ (0x40) |
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| 421 | #define MCF_UART_UMR_RXRTS (0x80) |
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| 422 | #define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) |
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| 423 | #define MCF_UART_UMR_TXCTS (0x10) |
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| 424 | #define MCF_UART_UMR_TXRTS (0x20) |
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| 425 | #define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) |
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| 426 | #define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) |
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| 427 | #define MCF_UART_UMR_PM_MULTI_DATA (0x18) |
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| 428 | #define MCF_UART_UMR_PM_NONE (0x10) |
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| 429 | #define MCF_UART_UMR_PM_FORCE_HI (0x0C) |
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| 430 | #define MCF_UART_UMR_PM_FORCE_LO (0x08) |
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| 431 | #define MCF_UART_UMR_PM_ODD (0x04) |
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| 432 | #define MCF_UART_UMR_PM_EVEN (0x00) |
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| 433 | #define MCF_UART_UMR_BC_5 (0x00) |
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| 434 | #define MCF_UART_UMR_BC_6 (0x01) |
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| 435 | #define MCF_UART_UMR_BC_7 (0x02) |
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| 436 | #define MCF_UART_UMR_BC_8 (0x03) |
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| 437 | #define MCF_UART_UMR_CM_NORMAL (0x00) |
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| 438 | #define MCF_UART_UMR_CM_ECHO (0x40) |
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| 439 | #define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) |
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| 440 | #define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) |
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| 441 | #define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) |
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| 442 | #define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) |
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| 443 | #define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) |
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| 444 | |
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| 445 | /* Bit definitions and macros for MCF_UART_USR */ |
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| 446 | #define MCF_UART_USR_RXRDY (0x01) |
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| 447 | #define MCF_UART_USR_FFULL (0x02) |
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| 448 | #define MCF_UART_USR_TXRDY (0x04) |
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| 449 | #define MCF_UART_USR_TXEMP (0x08) |
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| 450 | #define MCF_UART_USR_OE (0x10) |
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| 451 | #define MCF_UART_USR_PE (0x20) |
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| 452 | #define MCF_UART_USR_FE (0x40) |
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| 453 | #define MCF_UART_USR_RB (0x80) |
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| 454 | |
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| 455 | /* Bit definitions and macros for MCF_UART_UCSR */ |
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| 456 | #define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) |
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| 457 | #define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) |
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| 458 | #define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) |
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| 459 | #define MCF_UART_UCSR_RCS_CTM16 (0xE0) |
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| 460 | #define MCF_UART_UCSR_RCS_CTM (0xF0) |
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| 461 | #define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) |
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| 462 | #define MCF_UART_UCSR_TCS_CTM16 (0x0E) |
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| 463 | #define MCF_UART_UCSR_TCS_CTM (0x0F) |
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| 464 | |
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| 465 | /* Bit definitions and macros for MCF_UART_UCR */ |
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| 466 | #define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) |
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| 467 | #define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) |
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| 468 | #define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) |
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| 469 | #define MCF_UART_UCR_NONE (0x00) |
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| 470 | #define MCF_UART_UCR_STOP_BREAK (0x70) |
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| 471 | #define MCF_UART_UCR_START_BREAK (0x60) |
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| 472 | #define MCF_UART_UCR_BKCHGINT (0x50) |
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| 473 | #define MCF_UART_UCR_RESET_ERROR (0x40) |
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| 474 | #define MCF_UART_UCR_RESET_TX (0x30) |
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| 475 | #define MCF_UART_UCR_RESET_RX (0x20) |
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| 476 | #define MCF_UART_UCR_RESET_MR (0x10) |
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| 477 | #define MCF_UART_UCR_TX_DISABLED (0x08) |
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| 478 | #define MCF_UART_UCR_TX_ENABLED (0x04) |
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| 479 | #define MCF_UART_UCR_RX_DISABLED (0x02) |
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| 480 | #define MCF_UART_UCR_RX_ENABLED (0x01) |
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| 481 | |
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| 482 | /* Bit definitions and macros for MCF_UART_UIPCR */ |
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| 483 | #define MCF_UART_UIPCR_CTS (0x01) |
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| 484 | #define MCF_UART_UIPCR_COS (0x10) |
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| 485 | |
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| 486 | /* Bit definitions and macros for MCF_UART_UACR */ |
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| 487 | #define MCF_UART_UACR_IEC (0x01) |
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| 488 | |
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| 489 | /* Bit definitions and macros for MCF_UART_UISR */ |
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| 490 | #define MCF_UART_UISR_TXRDY (0x01) |
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| 491 | #define MCF_UART_UISR_RXRDY_FU (0x02) |
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| 492 | #define MCF_UART_UISR_DB (0x04) |
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| 493 | #define MCF_UART_UISR_RXFTO (0x08) |
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| 494 | #define MCF_UART_UISR_TXFIFO (0x10) |
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| 495 | #define MCF_UART_UISR_RXFIFO (0x20) |
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| 496 | #define MCF_UART_UISR_COS (0x80) |
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| 497 | |
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| 498 | /* Bit definitions and macros for MCF_UART_UIMR */ |
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| 499 | #define MCF_UART_UIMR_TXRDY (0x01) |
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| 500 | #define MCF_UART_UIMR_RXRDY_FU (0x02) |
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| 501 | #define MCF_UART_UIMR_DB (0x04) |
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| 502 | #define MCF_UART_UIMR_COS (0x80) |
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| 503 | |
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| 504 | /* Bit definitions and macros for MCF_UART_UIP */ |
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| 505 | #define MCF_UART_UIP_CTS (0x01) |
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| 506 | |
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| 507 | /* Bit definitions and macros for MCF_UART_UOP1 */ |
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| 508 | #define MCF_UART_UOP1_RTS (0x01) |
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| 509 | |
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| 510 | /* Bit definitions and macros for MCF_UART_UOP0 */ |
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| 511 | #define MCF_UART_UOP0_RTS (0x01) |
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| 512 | |
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| 513 | /********************************************************************* |
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| 514 | * |
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| 515 | * I2C Module (I2C) |
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| 516 | * |
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| 517 | *********************************************************************/ |
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| 518 | |
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| 519 | /* Register read/write macros */ |
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| 520 | #define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) |
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| 521 | #define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) |
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| 522 | #define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) |
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| 523 | #define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) |
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| 524 | #define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) |
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| 525 | |
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| 526 | /* Bit definitions and macros for MCF_I2C_I2AR */ |
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| 527 | #define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) |
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| 528 | |
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| 529 | /* Bit definitions and macros for MCF_I2C_I2FDR */ |
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| 530 | #define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) |
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| 531 | |
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| 532 | /* Bit definitions and macros for MCF_I2C_I2CR */ |
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| 533 | #define MCF_I2C_I2CR_RSTA (0x04) |
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| 534 | #define MCF_I2C_I2CR_TXAK (0x08) |
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| 535 | #define MCF_I2C_I2CR_MTX (0x10) |
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| 536 | #define MCF_I2C_I2CR_MSTA (0x20) |
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| 537 | #define MCF_I2C_I2CR_IIEN (0x40) |
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| 538 | #define MCF_I2C_I2CR_IEN (0x80) |
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| 539 | |
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| 540 | /* Bit definitions and macros for MCF_I2C_I2SR */ |
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| 541 | #define MCF_I2C_I2SR_RXAK (0x01) |
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| 542 | #define MCF_I2C_I2SR_IIF (0x02) |
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| 543 | #define MCF_I2C_I2SR_SRW (0x04) |
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| 544 | #define MCF_I2C_I2SR_IAL (0x10) |
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| 545 | #define MCF_I2C_I2SR_IBB (0x20) |
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| 546 | #define MCF_I2C_I2SR_IAAS (0x40) |
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| 547 | #define MCF_I2C_I2SR_ICF (0x80) |
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| 548 | |
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| 549 | /* Bit definitions and macros for MCF_I2C_I2DR */ |
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| 550 | #define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) |
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| 551 | |
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| 552 | /* Bit definitions and macros for MCF_I2C_I2ICR */ |
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| 553 | #define MCF_I2C_I2ICR_IE (0x01) |
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| 554 | #define MCF_I2C_I2ICR_RE (0x02) |
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| 555 | #define MCF_I2C_I2ICR_TE (0x04) |
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| 556 | #define MCF_I2C_I2ICR_BNBE (0x08) |
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| 557 | |
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| 558 | /********************************************************************* |
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| 559 | * |
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| 560 | * Queued Serial Peripheral Interface (QSPI) |
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| 561 | * |
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| 562 | *********************************************************************/ |
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| 563 | |
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| 564 | /* Register read/write macros */ |
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| 565 | #define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) |
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| 566 | #define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) |
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| 567 | #define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) |
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| 568 | #define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) |
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| 569 | #define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) |
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| 570 | #define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) |
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| 571 | |
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| 572 | /* Bit definitions and macros for MCF_QSPI_QMR */ |
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| 573 | #define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) |
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| 574 | #define MCF_QSPI_QMR_CPHA (0x0100) |
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| 575 | #define MCF_QSPI_QMR_CPOL (0x0200) |
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| 576 | #define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) |
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| 577 | #define MCF_QSPI_QMR_DOHIE (0x4000) |
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| 578 | #define MCF_QSPI_QMR_MSTR (0x8000) |
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| 579 | |
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| 580 | /* Bit definitions and macros for MCF_QSPI_QDLYR */ |
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| 581 | #define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) |
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| 582 | #define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) |
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| 583 | #define MCF_QSPI_QDLYR_SPE (0x8000) |
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| 584 | |
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| 585 | /* Bit definitions and macros for MCF_QSPI_QWR */ |
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| 586 | #define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) |
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| 587 | #define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) |
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| 588 | #define MCF_QSPI_QWR_CSIV (0x1000) |
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| 589 | #define MCF_QSPI_QWR_WRTO (0x2000) |
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| 590 | #define MCF_QSPI_QWR_WREN (0x4000) |
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| 591 | #define MCF_QSPI_QWR_HALT (0x8000) |
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| 592 | |
---|
| 593 | /* Bit definitions and macros for MCF_QSPI_QIR */ |
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| 594 | #define MCF_QSPI_QIR_SPIF (0x0001) |
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| 595 | #define MCF_QSPI_QIR_ABRT (0x0004) |
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| 596 | #define MCF_QSPI_QIR_WCEF (0x0008) |
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| 597 | #define MCF_QSPI_QIR_SPIFE (0x0100) |
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| 598 | #define MCF_QSPI_QIR_ABRTE (0x0400) |
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| 599 | #define MCF_QSPI_QIR_WCEFE (0x0800) |
---|
| 600 | #define MCF_QSPI_QIR_ABRTL (0x1000) |
---|
| 601 | #define MCF_QSPI_QIR_ABRTB (0x4000) |
---|
| 602 | #define MCF_QSPI_QIR_WCEFB (0x8000) |
---|
| 603 | |
---|
| 604 | /* Bit definitions and macros for MCF_QSPI_QAR */ |
---|
| 605 | #define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) |
---|
| 606 | |
---|
| 607 | /* Bit definitions and macros for MCF_QSPI_QDR */ |
---|
| 608 | #define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) |
---|
| 609 | |
---|
| 610 | /********************************************************************* |
---|
| 611 | * |
---|
| 612 | * DMA Timers (DTIM) |
---|
| 613 | * |
---|
| 614 | *********************************************************************/ |
---|
| 615 | |
---|
| 616 | /* Register read/write macros */ |
---|
| 617 | #define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) |
---|
| 618 | #define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) |
---|
| 619 | #define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) |
---|
| 620 | #define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) |
---|
| 621 | #define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) |
---|
| 622 | #define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) |
---|
| 623 | #define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) |
---|
| 624 | #define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) |
---|
| 625 | #define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) |
---|
| 626 | #define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) |
---|
| 627 | #define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) |
---|
| 628 | #define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) |
---|
| 629 | #define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) |
---|
| 630 | #define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) |
---|
| 631 | #define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) |
---|
| 632 | #define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) |
---|
| 633 | #define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) |
---|
| 634 | #define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) |
---|
| 635 | #define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) |
---|
| 636 | #define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) |
---|
| 637 | #define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) |
---|
| 638 | #define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) |
---|
| 639 | #define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) |
---|
| 640 | #define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) |
---|
| 641 | #define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) |
---|
| 642 | #define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) |
---|
| 643 | #define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) |
---|
| 644 | #define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) |
---|
| 645 | #define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) |
---|
| 646 | #define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) |
---|
| 647 | |
---|
| 648 | /* Bit definitions and macros for MCF_DTIM_DTMR */ |
---|
| 649 | #define MCF_DTIM_DTMR_RST (0x0001) |
---|
| 650 | #define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) |
---|
| 651 | #define MCF_DTIM_DTMR_FRR (0x0008) |
---|
| 652 | #define MCF_DTIM_DTMR_ORRI (0x0010) |
---|
| 653 | #define MCF_DTIM_DTMR_OM (0x0020) |
---|
| 654 | #define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) |
---|
| 655 | #define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) |
---|
| 656 | #define MCF_DTIM_DTMR_CE_ANY (0x00C0) |
---|
| 657 | #define MCF_DTIM_DTMR_CE_FALL (0x0080) |
---|
| 658 | #define MCF_DTIM_DTMR_CE_RISE (0x0040) |
---|
| 659 | #define MCF_DTIM_DTMR_CE_NONE (0x0000) |
---|
| 660 | #define MCF_DTIM_DTMR_CLK_DTIN (0x0006) |
---|
| 661 | #define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) |
---|
| 662 | #define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) |
---|
| 663 | #define MCF_DTIM_DTMR_CLK_STOP (0x0000) |
---|
| 664 | |
---|
| 665 | /* Bit definitions and macros for MCF_DTIM_DTXMR */ |
---|
| 666 | #define MCF_DTIM_DTXMR_MODE16 (0x01) |
---|
| 667 | #define MCF_DTIM_DTXMR_DMAEN (0x80) |
---|
| 668 | |
---|
| 669 | /* Bit definitions and macros for MCF_DTIM_DTER */ |
---|
| 670 | #define MCF_DTIM_DTER_CAP (0x01) |
---|
| 671 | #define MCF_DTIM_DTER_REF (0x02) |
---|
| 672 | |
---|
| 673 | /* Bit definitions and macros for MCF_DTIM_DTRR */ |
---|
| 674 | #define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 675 | |
---|
| 676 | /* Bit definitions and macros for MCF_DTIM_DTCR */ |
---|
| 677 | #define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 678 | |
---|
| 679 | /* Bit definitions and macros for MCF_DTIM_DTCN */ |
---|
| 680 | #define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 681 | |
---|
| 682 | /********************************************************************* |
---|
| 683 | * |
---|
| 684 | * Interrupt Controller (INTC) |
---|
| 685 | * |
---|
| 686 | *********************************************************************/ |
---|
| 687 | |
---|
| 688 | /* Register read/write macros */ |
---|
| 689 | #define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) |
---|
| 690 | #define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) |
---|
| 691 | #define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) |
---|
| 692 | #define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) |
---|
| 693 | #define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) |
---|
| 694 | #define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) |
---|
| 695 | #define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) |
---|
| 696 | #define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) |
---|
| 697 | #define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) |
---|
| 698 | #define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) |
---|
| 699 | #define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) |
---|
| 700 | #define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) |
---|
| 701 | #define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) |
---|
| 702 | #define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) |
---|
| 703 | #define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) |
---|
| 704 | #define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) |
---|
| 705 | #define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) |
---|
| 706 | #define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) |
---|
| 707 | #define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) |
---|
| 708 | #define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) |
---|
| 709 | #define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) |
---|
| 710 | #define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) |
---|
| 711 | #define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) |
---|
| 712 | #define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) |
---|
| 713 | #define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) |
---|
| 714 | #define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) |
---|
| 715 | #define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) |
---|
| 716 | #define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) |
---|
| 717 | #define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) |
---|
| 718 | #define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) |
---|
| 719 | #define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) |
---|
| 720 | #define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) |
---|
| 721 | #define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) |
---|
| 722 | #define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) |
---|
| 723 | #define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) |
---|
| 724 | #define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) |
---|
| 725 | #define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) |
---|
| 726 | #define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) |
---|
| 727 | #define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) |
---|
| 728 | #define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) |
---|
| 729 | #define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) |
---|
| 730 | #define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) |
---|
| 731 | #define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) |
---|
| 732 | #define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) |
---|
| 733 | #define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) |
---|
| 734 | #define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) |
---|
| 735 | #define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) |
---|
| 736 | #define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) |
---|
| 737 | #define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) |
---|
| 738 | #define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) |
---|
| 739 | #define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) |
---|
| 740 | #define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) |
---|
| 741 | #define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) |
---|
| 742 | #define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) |
---|
| 743 | #define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) |
---|
| 744 | #define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) |
---|
| 745 | #define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) |
---|
| 746 | #define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) |
---|
| 747 | #define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) |
---|
| 748 | #define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) |
---|
| 749 | #define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) |
---|
| 750 | #define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) |
---|
| 751 | #define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) |
---|
| 752 | #define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) |
---|
| 753 | #define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) |
---|
| 754 | #define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) |
---|
| 755 | #define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) |
---|
| 756 | #define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) |
---|
| 757 | #define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) |
---|
| 758 | #define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) |
---|
| 759 | #define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) |
---|
| 760 | #define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) |
---|
| 761 | #define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) |
---|
| 762 | #define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) |
---|
| 763 | #define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) |
---|
| 764 | #define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) |
---|
| 765 | #define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) |
---|
| 766 | #define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) |
---|
| 767 | #define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) |
---|
| 768 | #define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) |
---|
| 769 | #define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) |
---|
| 770 | #define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) |
---|
| 771 | #define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) |
---|
| 772 | #define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) |
---|
| 773 | #define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) |
---|
| 774 | #define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) |
---|
| 775 | #define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) |
---|
| 776 | #define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) |
---|
| 777 | #define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) |
---|
| 778 | #define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) |
---|
| 779 | #define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) |
---|
| 780 | #define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) |
---|
| 781 | #define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) |
---|
| 782 | #define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) |
---|
| 783 | #define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) |
---|
| 784 | #define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) |
---|
| 785 | #define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) |
---|
| 786 | #define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) |
---|
| 787 | #define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) |
---|
| 788 | #define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) |
---|
| 789 | #define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) |
---|
| 790 | #define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) |
---|
| 791 | #define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) |
---|
| 792 | #define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) |
---|
| 793 | #define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) |
---|
| 794 | #define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) |
---|
| 795 | #define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) |
---|
| 796 | #define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) |
---|
| 797 | #define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) |
---|
| 798 | #define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) |
---|
| 799 | #define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) |
---|
| 800 | #define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) |
---|
| 801 | #define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) |
---|
| 802 | #define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) |
---|
| 803 | #define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) |
---|
| 804 | #define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) |
---|
| 805 | #define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) |
---|
| 806 | #define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) |
---|
| 807 | #define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) |
---|
| 808 | #define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) |
---|
| 809 | #define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) |
---|
| 810 | #define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) |
---|
| 811 | #define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) |
---|
| 812 | #define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) |
---|
| 813 | #define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) |
---|
| 814 | #define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) |
---|
| 815 | #define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) |
---|
| 816 | #define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) |
---|
| 817 | #define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) |
---|
| 818 | #define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) |
---|
| 819 | #define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) |
---|
| 820 | #define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) |
---|
| 821 | #define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) |
---|
| 822 | #define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) |
---|
| 823 | #define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) |
---|
| 824 | #define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) |
---|
| 825 | #define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) |
---|
| 826 | #define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) |
---|
| 827 | #define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) |
---|
| 828 | #define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) |
---|
| 829 | #define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) |
---|
| 830 | #define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) |
---|
| 831 | #define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) |
---|
| 832 | #define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) |
---|
| 833 | #define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) |
---|
| 834 | #define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) |
---|
| 835 | #define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) |
---|
| 836 | #define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) |
---|
| 837 | #define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) |
---|
| 838 | #define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) |
---|
| 839 | #define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) |
---|
| 840 | #define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) |
---|
| 841 | #define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) |
---|
| 842 | #define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) |
---|
| 843 | #define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) |
---|
| 844 | #define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) |
---|
| 845 | #define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) |
---|
| 846 | #define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) |
---|
| 847 | #define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) |
---|
| 848 | #define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) |
---|
| 849 | #define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) |
---|
| 850 | #define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) |
---|
| 851 | #define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) |
---|
| 852 | #define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) |
---|
| 853 | #define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) |
---|
| 854 | #define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) |
---|
| 855 | #define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) |
---|
| 856 | #define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) |
---|
| 857 | #define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) |
---|
| 858 | #define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) |
---|
| 859 | #define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) |
---|
| 860 | #define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) |
---|
| 861 | #define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) |
---|
| 862 | #define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) |
---|
| 863 | #define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) |
---|
| 864 | #define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) |
---|
| 865 | #define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) |
---|
| 866 | #define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) |
---|
| 867 | #define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) |
---|
| 868 | #define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) |
---|
| 869 | #define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) |
---|
| 870 | #define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) |
---|
| 871 | #define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) |
---|
| 872 | #define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) |
---|
| 873 | #define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) |
---|
| 874 | #define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) |
---|
| 875 | #define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) |
---|
| 876 | #define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) |
---|
| 877 | #define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) |
---|
| 878 | #define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) |
---|
| 879 | #define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) |
---|
| 880 | #define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) |
---|
| 881 | #define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) |
---|
| 882 | #define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) |
---|
| 883 | #define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) |
---|
| 884 | #define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) |
---|
| 885 | #define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) |
---|
| 886 | #define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) |
---|
| 887 | #define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) |
---|
| 888 | #define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) |
---|
| 889 | #define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) |
---|
| 890 | #define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) |
---|
| 891 | #define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) |
---|
| 892 | #define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) |
---|
| 893 | #define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) |
---|
| 894 | #define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) |
---|
| 895 | #define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) |
---|
| 896 | #define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) |
---|
| 897 | #define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) |
---|
| 898 | #define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) |
---|
| 899 | #define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) |
---|
| 900 | #define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) |
---|
| 901 | #define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) |
---|
| 902 | #define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) |
---|
| 903 | #define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) |
---|
| 904 | #define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) |
---|
| 905 | #define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) |
---|
| 906 | #define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) |
---|
| 907 | #define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) |
---|
| 908 | #define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) |
---|
| 909 | #define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) |
---|
| 910 | #define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) |
---|
| 911 | #define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) |
---|
| 912 | #define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) |
---|
| 913 | #define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) |
---|
| 914 | #define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) |
---|
| 915 | #define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) |
---|
| 916 | #define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) |
---|
| 917 | #define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) |
---|
| 918 | #define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) |
---|
| 919 | #define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) |
---|
| 920 | #define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) |
---|
| 921 | #define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) |
---|
| 922 | #define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) |
---|
| 923 | #define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) |
---|
| 924 | #define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) |
---|
| 925 | #define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) |
---|
| 926 | #define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) |
---|
| 927 | #define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) |
---|
| 928 | #define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) |
---|
| 929 | #define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) |
---|
| 930 | |
---|
| 931 | /* Bit definitions and macros for MCF_INTC_IPRH */ |
---|
| 932 | #define MCF_INTC_IPRH_INT32 (0x00000001) |
---|
| 933 | #define MCF_INTC_IPRH_INT33 (0x00000002) |
---|
| 934 | #define MCF_INTC_IPRH_INT34 (0x00000004) |
---|
| 935 | #define MCF_INTC_IPRH_INT35 (0x00000008) |
---|
| 936 | #define MCF_INTC_IPRH_INT36 (0x00000010) |
---|
| 937 | #define MCF_INTC_IPRH_INT37 (0x00000020) |
---|
| 938 | #define MCF_INTC_IPRH_INT38 (0x00000040) |
---|
| 939 | #define MCF_INTC_IPRH_INT39 (0x00000080) |
---|
| 940 | #define MCF_INTC_IPRH_INT40 (0x00000100) |
---|
| 941 | #define MCF_INTC_IPRH_INT41 (0x00000200) |
---|
| 942 | #define MCF_INTC_IPRH_INT42 (0x00000400) |
---|
| 943 | #define MCF_INTC_IPRH_INT43 (0x00000800) |
---|
| 944 | #define MCF_INTC_IPRH_INT44 (0x00001000) |
---|
| 945 | #define MCF_INTC_IPRH_INT45 (0x00002000) |
---|
| 946 | #define MCF_INTC_IPRH_INT46 (0x00004000) |
---|
| 947 | #define MCF_INTC_IPRH_INT47 (0x00008000) |
---|
| 948 | #define MCF_INTC_IPRH_INT48 (0x00010000) |
---|
| 949 | #define MCF_INTC_IPRH_INT49 (0x00020000) |
---|
| 950 | #define MCF_INTC_IPRH_INT50 (0x00040000) |
---|
| 951 | #define MCF_INTC_IPRH_INT51 (0x00080000) |
---|
| 952 | #define MCF_INTC_IPRH_INT52 (0x00100000) |
---|
| 953 | #define MCF_INTC_IPRH_INT53 (0x00200000) |
---|
| 954 | #define MCF_INTC_IPRH_INT54 (0x00400000) |
---|
| 955 | #define MCF_INTC_IPRH_INT55 (0x00800000) |
---|
| 956 | #define MCF_INTC_IPRH_INT56 (0x01000000) |
---|
| 957 | #define MCF_INTC_IPRH_INT57 (0x02000000) |
---|
| 958 | #define MCF_INTC_IPRH_INT58 (0x04000000) |
---|
| 959 | #define MCF_INTC_IPRH_INT59 (0x08000000) |
---|
| 960 | #define MCF_INTC_IPRH_INT60 (0x10000000) |
---|
| 961 | #define MCF_INTC_IPRH_INT61 (0x20000000) |
---|
| 962 | #define MCF_INTC_IPRH_INT62 (0x40000000) |
---|
| 963 | #define MCF_INTC_IPRH_INT63 (0x80000000) |
---|
| 964 | |
---|
| 965 | /* Bit definitions and macros for MCF_INTC_IPRL */ |
---|
| 966 | #define MCF_INTC_IPRL_INT1 (0x00000002) |
---|
| 967 | #define MCF_INTC_IPRL_INT2 (0x00000004) |
---|
| 968 | #define MCF_INTC_IPRL_INT3 (0x00000008) |
---|
| 969 | #define MCF_INTC_IPRL_INT4 (0x00000010) |
---|
| 970 | #define MCF_INTC_IPRL_INT5 (0x00000020) |
---|
| 971 | #define MCF_INTC_IPRL_INT6 (0x00000040) |
---|
| 972 | #define MCF_INTC_IPRL_INT7 (0x00000080) |
---|
| 973 | #define MCF_INTC_IPRL_INT8 (0x00000100) |
---|
| 974 | #define MCF_INTC_IPRL_INT9 (0x00000200) |
---|
| 975 | #define MCF_INTC_IPRL_INT10 (0x00000400) |
---|
| 976 | #define MCF_INTC_IPRL_INT11 (0x00000800) |
---|
| 977 | #define MCF_INTC_IPRL_INT12 (0x00001000) |
---|
| 978 | #define MCF_INTC_IPRL_INT13 (0x00002000) |
---|
| 979 | #define MCF_INTC_IPRL_INT14 (0x00004000) |
---|
| 980 | #define MCF_INTC_IPRL_INT15 (0x00008000) |
---|
| 981 | #define MCF_INTC_IPRL_INT16 (0x00010000) |
---|
| 982 | #define MCF_INTC_IPRL_INT17 (0x00020000) |
---|
| 983 | #define MCF_INTC_IPRL_INT18 (0x00040000) |
---|
| 984 | #define MCF_INTC_IPRL_INT19 (0x00080000) |
---|
| 985 | #define MCF_INTC_IPRL_INT20 (0x00100000) |
---|
| 986 | #define MCF_INTC_IPRL_INT21 (0x00200000) |
---|
| 987 | #define MCF_INTC_IPRL_INT22 (0x00400000) |
---|
| 988 | #define MCF_INTC_IPRL_INT23 (0x00800000) |
---|
| 989 | #define MCF_INTC_IPRL_INT24 (0x01000000) |
---|
| 990 | #define MCF_INTC_IPRL_INT25 (0x02000000) |
---|
| 991 | #define MCF_INTC_IPRL_INT26 (0x04000000) |
---|
| 992 | #define MCF_INTC_IPRL_INT27 (0x08000000) |
---|
| 993 | #define MCF_INTC_IPRL_INT28 (0x10000000) |
---|
| 994 | #define MCF_INTC_IPRL_INT29 (0x20000000) |
---|
| 995 | #define MCF_INTC_IPRL_INT30 (0x40000000) |
---|
| 996 | #define MCF_INTC_IPRL_INT31 (0x80000000) |
---|
| 997 | |
---|
| 998 | /* Bit definitions and macros for MCF_INTC_IMRH */ |
---|
| 999 | #define MCF_INTC_IMRH_MASK32 (0x00000001) |
---|
| 1000 | #define MCF_INTC_IMRH_MASK33 (0x00000002) |
---|
| 1001 | #define MCF_INTC_IMRH_MASK34 (0x00000004) |
---|
| 1002 | #define MCF_INTC_IMRH_MASK35 (0x00000008) |
---|
| 1003 | #define MCF_INTC_IMRH_MASK36 (0x00000010) |
---|
| 1004 | #define MCF_INTC_IMRH_MASK37 (0x00000020) |
---|
| 1005 | #define MCF_INTC_IMRH_MASK38 (0x00000040) |
---|
| 1006 | #define MCF_INTC_IMRH_MASK39 (0x00000080) |
---|
| 1007 | #define MCF_INTC_IMRH_MASK40 (0x00000100) |
---|
| 1008 | #define MCF_INTC_IMRH_MASK41 (0x00000200) |
---|
| 1009 | #define MCF_INTC_IMRH_MASK42 (0x00000400) |
---|
| 1010 | #define MCF_INTC_IMRH_MASK43 (0x00000800) |
---|
| 1011 | #define MCF_INTC_IMRH_MASK44 (0x00001000) |
---|
| 1012 | #define MCF_INTC_IMRH_MASK45 (0x00002000) |
---|
| 1013 | #define MCF_INTC_IMRH_MASK46 (0x00004000) |
---|
| 1014 | #define MCF_INTC_IMRH_MASK47 (0x00008000) |
---|
| 1015 | #define MCF_INTC_IMRH_MASK48 (0x00010000) |
---|
| 1016 | #define MCF_INTC_IMRH_MASK49 (0x00020000) |
---|
| 1017 | #define MCF_INTC_IMRH_MASK50 (0x00040000) |
---|
| 1018 | #define MCF_INTC_IMRH_MASK51 (0x00080000) |
---|
| 1019 | #define MCF_INTC_IMRH_MASK52 (0x00100000) |
---|
| 1020 | #define MCF_INTC_IMRH_MASK53 (0x00200000) |
---|
| 1021 | #define MCF_INTC_IMRH_MASK54 (0x00400000) |
---|
| 1022 | #define MCF_INTC_IMRH_MASK55 (0x00800000) |
---|
| 1023 | #define MCF_INTC_IMRH_MASK56 (0x01000000) |
---|
| 1024 | #define MCF_INTC_IMRH_MASK57 (0x02000000) |
---|
| 1025 | #define MCF_INTC_IMRH_MASK58 (0x04000000) |
---|
| 1026 | #define MCF_INTC_IMRH_MASK59 (0x08000000) |
---|
| 1027 | #define MCF_INTC_IMRH_MASK60 (0x10000000) |
---|
| 1028 | #define MCF_INTC_IMRH_MASK61 (0x20000000) |
---|
| 1029 | #define MCF_INTC_IMRH_MASK62 (0x40000000) |
---|
| 1030 | #define MCF_INTC_IMRH_MASK63 (0x80000000) |
---|
| 1031 | |
---|
| 1032 | /* Bit definitions and macros for MCF_INTC_IMRL */ |
---|
| 1033 | #define MCF_INTC_IMRL_MASKALL (0x00000001) |
---|
| 1034 | #define MCF_INTC_IMRL_MASK1 (0x00000002) |
---|
| 1035 | #define MCF_INTC_IMRL_MASK2 (0x00000004) |
---|
| 1036 | #define MCF_INTC_IMRL_MASK3 (0x00000008) |
---|
| 1037 | #define MCF_INTC_IMRL_MASK4 (0x00000010) |
---|
| 1038 | #define MCF_INTC_IMRL_MASK5 (0x00000020) |
---|
| 1039 | #define MCF_INTC_IMRL_MASK6 (0x00000040) |
---|
| 1040 | #define MCF_INTC_IMRL_MASK7 (0x00000080) |
---|
| 1041 | #define MCF_INTC_IMRL_MASK8 (0x00000100) |
---|
| 1042 | #define MCF_INTC_IMRL_MASK9 (0x00000200) |
---|
| 1043 | #define MCF_INTC_IMRL_MASK10 (0x00000400) |
---|
| 1044 | #define MCF_INTC_IMRL_MASK11 (0x00000800) |
---|
| 1045 | #define MCF_INTC_IMRL_MASK12 (0x00001000) |
---|
| 1046 | #define MCF_INTC_IMRL_MASK13 (0x00002000) |
---|
| 1047 | #define MCF_INTC_IMRL_MASK14 (0x00004000) |
---|
| 1048 | #define MCF_INTC_IMRL_MASK15 (0x00008000) |
---|
| 1049 | #define MCF_INTC_IMRL_MASK16 (0x00010000) |
---|
| 1050 | #define MCF_INTC_IMRL_MASK17 (0x00020000) |
---|
| 1051 | #define MCF_INTC_IMRL_MASK18 (0x00040000) |
---|
| 1052 | #define MCF_INTC_IMRL_MASK19 (0x00080000) |
---|
| 1053 | #define MCF_INTC_IMRL_MASK20 (0x00100000) |
---|
| 1054 | #define MCF_INTC_IMRL_MASK21 (0x00200000) |
---|
| 1055 | #define MCF_INTC_IMRL_MASK22 (0x00400000) |
---|
| 1056 | #define MCF_INTC_IMRL_MASK23 (0x00800000) |
---|
| 1057 | #define MCF_INTC_IMRL_MASK24 (0x01000000) |
---|
| 1058 | #define MCF_INTC_IMRL_MASK25 (0x02000000) |
---|
| 1059 | #define MCF_INTC_IMRL_MASK26 (0x04000000) |
---|
| 1060 | #define MCF_INTC_IMRL_MASK27 (0x08000000) |
---|
| 1061 | #define MCF_INTC_IMRL_MASK28 (0x10000000) |
---|
| 1062 | #define MCF_INTC_IMRL_MASK29 (0x20000000) |
---|
| 1063 | #define MCF_INTC_IMRL_MASK30 (0x40000000) |
---|
| 1064 | #define MCF_INTC_IMRL_MASK31 (0x80000000) |
---|
| 1065 | |
---|
| 1066 | /* Bit definitions and macros for MCF_INTC_INTFRCH */ |
---|
| 1067 | #define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) |
---|
| 1068 | #define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) |
---|
| 1069 | #define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) |
---|
| 1070 | #define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) |
---|
| 1071 | #define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) |
---|
| 1072 | #define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) |
---|
| 1073 | #define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) |
---|
| 1074 | #define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) |
---|
| 1075 | #define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) |
---|
| 1076 | #define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) |
---|
| 1077 | #define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) |
---|
| 1078 | #define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) |
---|
| 1079 | #define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) |
---|
| 1080 | #define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) |
---|
| 1081 | #define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) |
---|
| 1082 | #define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) |
---|
| 1083 | #define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) |
---|
| 1084 | #define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) |
---|
| 1085 | #define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) |
---|
| 1086 | #define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) |
---|
| 1087 | #define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) |
---|
| 1088 | #define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) |
---|
| 1089 | #define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) |
---|
| 1090 | #define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) |
---|
| 1091 | #define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) |
---|
| 1092 | #define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) |
---|
| 1093 | #define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) |
---|
| 1094 | #define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) |
---|
| 1095 | #define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) |
---|
| 1096 | #define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) |
---|
| 1097 | #define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) |
---|
| 1098 | #define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) |
---|
| 1099 | |
---|
| 1100 | /* Bit definitions and macros for MCF_INTC_INTFRCL */ |
---|
| 1101 | #define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) |
---|
| 1102 | #define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) |
---|
| 1103 | #define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) |
---|
| 1104 | #define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) |
---|
| 1105 | #define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) |
---|
| 1106 | #define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) |
---|
| 1107 | #define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) |
---|
| 1108 | #define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) |
---|
| 1109 | #define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) |
---|
| 1110 | #define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) |
---|
| 1111 | #define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) |
---|
| 1112 | #define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) |
---|
| 1113 | #define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) |
---|
| 1114 | #define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) |
---|
| 1115 | #define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) |
---|
| 1116 | #define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) |
---|
| 1117 | #define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) |
---|
| 1118 | #define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) |
---|
| 1119 | #define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) |
---|
| 1120 | #define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) |
---|
| 1121 | #define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) |
---|
| 1122 | #define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) |
---|
| 1123 | #define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) |
---|
| 1124 | #define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) |
---|
| 1125 | #define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) |
---|
| 1126 | #define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) |
---|
| 1127 | #define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) |
---|
| 1128 | #define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) |
---|
| 1129 | #define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) |
---|
| 1130 | #define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) |
---|
| 1131 | #define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) |
---|
| 1132 | |
---|
| 1133 | /* Bit definitions and macros for MCF_INTC_IRLR */ |
---|
| 1134 | #define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) |
---|
| 1135 | |
---|
| 1136 | /* Bit definitions and macros for MCF_INTC_IACKLPR */ |
---|
| 1137 | #define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) |
---|
| 1138 | #define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) |
---|
| 1139 | |
---|
| 1140 | /* Bit definitions and macros for MCF_INTC_ICR */ |
---|
| 1141 | #define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) |
---|
| 1142 | #define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) |
---|
| 1143 | |
---|
| 1144 | /* Bit definitions and macros for MCF_INTC_SWIACK */ |
---|
| 1145 | #define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) |
---|
| 1146 | |
---|
| 1147 | /* Bit definitions and macros for MCF_INTC_LIACK */ |
---|
| 1148 | #define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) |
---|
| 1149 | |
---|
| 1150 | /********************************************************************* |
---|
| 1151 | * |
---|
| 1152 | * General Purpose I/O (GPIO) |
---|
| 1153 | * |
---|
| 1154 | *********************************************************************/ |
---|
| 1155 | |
---|
| 1156 | /* Register read/write macros */ |
---|
| 1157 | #define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) |
---|
| 1158 | #define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) |
---|
| 1159 | #define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) |
---|
| 1160 | #define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) |
---|
| 1161 | #define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) |
---|
| 1162 | #define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) |
---|
| 1163 | #define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) |
---|
| 1164 | #define MCF_GPIO_PORTTE (*(vuint8 *)(&__IPSBAR[0x100000])) |
---|
| 1165 | #define MCF_GPIO_PORTTF (*(vuint8 *)(&__IPSBAR[0x100001])) |
---|
| 1166 | #define MCF_GPIO_PORTTG (*(vuint8 *)(&__IPSBAR[0x100002])) |
---|
| 1167 | #define MCF_GPIO_PORTTH (*(vuint8 *)(&__IPSBAR[0x100003])) |
---|
| 1168 | #define MCF_GPIO_PORTTI (*(vuint8 *)(&__IPSBAR[0x100004])) |
---|
| 1169 | #define MCF_GPIO_PORTTJ (*(vuint8 *)(&__IPSBAR[0x100006])) |
---|
| 1170 | #define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) |
---|
| 1171 | #define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) |
---|
| 1172 | #define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) |
---|
| 1173 | #define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) |
---|
| 1174 | #define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) |
---|
| 1175 | #define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) |
---|
| 1176 | #define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) |
---|
| 1177 | #define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) |
---|
| 1178 | #define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) |
---|
| 1179 | #define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) |
---|
| 1180 | #define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) |
---|
| 1181 | #define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) |
---|
| 1182 | #define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) |
---|
| 1183 | #define MCF_GPIO_DDRTE (*(vuint8 *)(&__IPSBAR[0x100018])) |
---|
| 1184 | #define MCF_GPIO_DDRTF (*(vuint8 *)(&__IPSBAR[0x100019])) |
---|
| 1185 | #define MCF_GPIO_DDRTG (*(vuint8 *)(&__IPSBAR[0x10001A])) |
---|
| 1186 | #define MCF_GPIO_DDRTH (*(vuint8 *)(&__IPSBAR[0x10001B])) |
---|
| 1187 | #define MCF_GPIO_DDRTI (*(vuint8 *)(&__IPSBAR[0x10001C])) |
---|
| 1188 | #define MCF_GPIO_DDRTJ (*(vuint8 *)(&__IPSBAR[0x10001E])) |
---|
| 1189 | #define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) |
---|
| 1190 | #define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) |
---|
| 1191 | #define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) |
---|
| 1192 | #define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) |
---|
| 1193 | #define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) |
---|
| 1194 | #define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) |
---|
| 1195 | #define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) |
---|
| 1196 | #define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) |
---|
| 1197 | #define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) |
---|
| 1198 | #define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) |
---|
| 1199 | #define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) |
---|
| 1200 | #define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) |
---|
| 1201 | #define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) |
---|
| 1202 | #define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) |
---|
| 1203 | #define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) |
---|
| 1204 | #define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) |
---|
| 1205 | #define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) |
---|
| 1206 | #define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) |
---|
| 1207 | #define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) |
---|
| 1208 | #define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) |
---|
| 1209 | #define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) |
---|
| 1210 | #define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) |
---|
| 1211 | #define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) |
---|
| 1212 | #define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) |
---|
| 1213 | #define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) |
---|
| 1214 | #define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) |
---|
| 1215 | #define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) |
---|
| 1216 | #define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) |
---|
| 1217 | #define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) |
---|
| 1218 | #define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) |
---|
| 1219 | #define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) |
---|
| 1220 | #define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) |
---|
| 1221 | #define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) |
---|
| 1222 | #define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) |
---|
| 1223 | #define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) |
---|
| 1224 | #define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) |
---|
| 1225 | #define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) |
---|
| 1226 | #define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) |
---|
| 1227 | #define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) |
---|
| 1228 | #define MCF_GPIO_PTEPAR (*(vuint8 *)(&__IPSBAR[0x100060])) |
---|
| 1229 | #define MCF_GPIO_PTFPAR (*(vuint8 *)(&__IPSBAR[0x100061])) |
---|
| 1230 | #define MCF_GPIO_PTGPAR (*(vuint8 *)(&__IPSBAR[0x100062])) |
---|
| 1231 | #define MCF_GPIO_PTHPAR (*(vuint8 *)(&__IPSBAR[0x100090])) |
---|
| 1232 | #define MCF_GPIO_PTIPAR (*(vuint8*)(&__IPSBAR[0x100064])) |
---|
| 1233 | #define MCF_GPIO_PTJPAR (*(vuint8*)(&__IPSBAR[0x100066])) |
---|
| 1234 | #define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) |
---|
| 1235 | #define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) |
---|
| 1236 | #define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) |
---|
| 1237 | #define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) |
---|
| 1238 | #define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) |
---|
| 1239 | #define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) |
---|
| 1240 | #define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) |
---|
| 1241 | #define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) |
---|
| 1242 | #define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) |
---|
| 1243 | |
---|
| 1244 | /* Bit definitions and macros for MCF_GPIO_PORTNQ */ |
---|
| 1245 | #define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) |
---|
| 1246 | #define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) |
---|
| 1247 | #define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) |
---|
| 1248 | #define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) |
---|
| 1249 | #define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) |
---|
| 1250 | #define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) |
---|
| 1251 | #define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) |
---|
| 1252 | #define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) |
---|
| 1253 | |
---|
| 1254 | /* Bit definitions and macros for MCF_GPIO_PORTAN */ |
---|
| 1255 | #define MCF_GPIO_PORTAN_PORTAN0 (0x01) |
---|
| 1256 | #define MCF_GPIO_PORTAN_PORTAN1 (0x02) |
---|
| 1257 | #define MCF_GPIO_PORTAN_PORTAN2 (0x04) |
---|
| 1258 | #define MCF_GPIO_PORTAN_PORTAN3 (0x08) |
---|
| 1259 | #define MCF_GPIO_PORTAN_PORTAN4 (0x10) |
---|
| 1260 | #define MCF_GPIO_PORTAN_PORTAN5 (0x20) |
---|
| 1261 | #define MCF_GPIO_PORTAN_PORTAN6 (0x40) |
---|
| 1262 | #define MCF_GPIO_PORTAN_PORTAN7 (0x80) |
---|
| 1263 | |
---|
| 1264 | /* Bit definitions and macros for MCF_GPIO_PORTAS */ |
---|
| 1265 | #define MCF_GPIO_PORTAS_PORTAS0 (0x01) |
---|
| 1266 | #define MCF_GPIO_PORTAS_PORTAS1 (0x02) |
---|
| 1267 | #define MCF_GPIO_PORTAS_PORTAS2 (0x04) |
---|
| 1268 | #define MCF_GPIO_PORTAS_PORTAS3 (0x08) |
---|
| 1269 | #define MCF_GPIO_PORTAS_PORTAS4 (0x10) |
---|
| 1270 | #define MCF_GPIO_PORTAS_PORTAS5 (0x20) |
---|
| 1271 | #define MCF_GPIO_PORTAS_PORTAS6 (0x40) |
---|
| 1272 | #define MCF_GPIO_PORTAS_PORTAS7 (0x80) |
---|
| 1273 | |
---|
| 1274 | /* Bit definitions and macros for MCF_GPIO_PORTQS */ |
---|
| 1275 | #define MCF_GPIO_PORTQS_PORTQS0 (0x01) |
---|
| 1276 | #define MCF_GPIO_PORTQS_PORTQS1 (0x02) |
---|
| 1277 | #define MCF_GPIO_PORTQS_PORTQS2 (0x04) |
---|
| 1278 | #define MCF_GPIO_PORTQS_PORTQS3 (0x08) |
---|
| 1279 | #define MCF_GPIO_PORTQS_PORTQS4 (0x10) |
---|
| 1280 | #define MCF_GPIO_PORTQS_PORTQS5 (0x20) |
---|
| 1281 | #define MCF_GPIO_PORTQS_PORTQS6 (0x40) |
---|
| 1282 | #define MCF_GPIO_PORTQS_PORTQS7 (0x80) |
---|
| 1283 | |
---|
| 1284 | /* Bit definitions and macros for MCF_GPIO_PORTTA */ |
---|
| 1285 | #define MCF_GPIO_PORTTA_PORTTA0 (0x01) |
---|
| 1286 | #define MCF_GPIO_PORTTA_PORTTA1 (0x02) |
---|
| 1287 | #define MCF_GPIO_PORTTA_PORTTA2 (0x04) |
---|
| 1288 | #define MCF_GPIO_PORTTA_PORTTA3 (0x08) |
---|
| 1289 | #define MCF_GPIO_PORTTA_PORTTA4 (0x10) |
---|
| 1290 | #define MCF_GPIO_PORTTA_PORTTA5 (0x20) |
---|
| 1291 | #define MCF_GPIO_PORTTA_PORTTA6 (0x40) |
---|
| 1292 | #define MCF_GPIO_PORTTA_PORTTA7 (0x80) |
---|
| 1293 | |
---|
| 1294 | /* Bit definitions and macros for MCF_GPIO_PORTTC */ |
---|
| 1295 | #define MCF_GPIO_PORTTC_PORTTC0 (0x01) |
---|
| 1296 | #define MCF_GPIO_PORTTC_PORTTC1 (0x02) |
---|
| 1297 | #define MCF_GPIO_PORTTC_PORTTC2 (0x04) |
---|
| 1298 | #define MCF_GPIO_PORTTC_PORTTC3 (0x08) |
---|
| 1299 | #define MCF_GPIO_PORTTC_PORTTC4 (0x10) |
---|
| 1300 | #define MCF_GPIO_PORTTC_PORTTC5 (0x20) |
---|
| 1301 | #define MCF_GPIO_PORTTC_PORTTC6 (0x40) |
---|
| 1302 | #define MCF_GPIO_PORTTC_PORTTC7 (0x80) |
---|
| 1303 | |
---|
| 1304 | /* Bit definitions and macros for MCF_GPIO_PORTTD */ |
---|
| 1305 | #define MCF_GPIO_PORTTD_PORTTD0 (0x01) |
---|
| 1306 | #define MCF_GPIO_PORTTD_PORTTD1 (0x02) |
---|
| 1307 | #define MCF_GPIO_PORTTD_PORTTD2 (0x04) |
---|
| 1308 | #define MCF_GPIO_PORTTD_PORTTD3 (0x08) |
---|
| 1309 | #define MCF_GPIO_PORTTD_PORTTD4 (0x10) |
---|
| 1310 | #define MCF_GPIO_PORTTD_PORTTD5 (0x20) |
---|
| 1311 | #define MCF_GPIO_PORTTD_PORTTD6 (0x40) |
---|
| 1312 | #define MCF_GPIO_PORTTD_PORTTD7 (0x80) |
---|
| 1313 | |
---|
| 1314 | /* Bit definitions and macros for MCF_GPIO_PORTTE */ |
---|
| 1315 | #define MCF_GPIO_PORTTE_PORTTE0 (0x01) |
---|
| 1316 | #define MCF_GPIO_PORTTE_PORTTE1 (0x02) |
---|
| 1317 | #define MCF_GPIO_PORTTE_PORTTE2 (0x04) |
---|
| 1318 | #define MCF_GPIO_PORTTE_PORTTE3 (0x08) |
---|
| 1319 | #define MCF_GPIO_PORTTE_PORTTE4 (0x10) |
---|
| 1320 | #define MCF_GPIO_PORTTE_PORTTE5 (0x20) |
---|
| 1321 | #define MCF_GPIO_PORTTE_PORTTE6 (0x40) |
---|
| 1322 | #define MCF_GPIO_PORTTE_PORTTE7 (0x80) |
---|
| 1323 | |
---|
| 1324 | /* Bit definitions and macros for MCF_GPIO_PORTTF */ |
---|
| 1325 | #define MCF_GPIO_PORTTF_PORTTF0 (0x01) |
---|
| 1326 | #define MCF_GPIO_PORTTF_PORTTF1 (0x02) |
---|
| 1327 | #define MCF_GPIO_PORTTF_PORTTF2 (0x04) |
---|
| 1328 | #define MCF_GPIO_PORTTF_PORTTF3 (0x08) |
---|
| 1329 | #define MCF_GPIO_PORTTF_PORTTF4 (0x10) |
---|
| 1330 | #define MCF_GPIO_PORTTF_PORTTF5 (0x20) |
---|
| 1331 | #define MCF_GPIO_PORTTF_PORTTF6 (0x40) |
---|
| 1332 | #define MCF_GPIO_PORTTF_PORTTF7 (0x80) |
---|
| 1333 | |
---|
| 1334 | /* Bit definitions and macros for MCF_GPIO_PORTTG */ |
---|
| 1335 | #define MCF_GPIO_PORTTG_PORTTG0 (0x01) |
---|
| 1336 | #define MCF_GPIO_PORTTG_PORTTG1 (0x02) |
---|
| 1337 | #define MCF_GPIO_PORTTG_PORTTG2 (0x04) |
---|
| 1338 | #define MCF_GPIO_PORTTG_PORTTG3 (0x08) |
---|
| 1339 | #define MCF_GPIO_PORTTG_PORTTG4 (0x10) |
---|
| 1340 | #define MCF_GPIO_PORTTG_PORTTG5 (0x20) |
---|
| 1341 | #define MCF_GPIO_PORTTG_PORTTG6 (0x40) |
---|
| 1342 | #define MCF_GPIO_PORTTG_PORTTG7 (0x80) |
---|
| 1343 | |
---|
| 1344 | /* Bit definitions and macros for MCF_GPIO_PORTTH */ |
---|
| 1345 | #define MCF_GPIO_PORTTH_PORTTH0 (0x01) |
---|
| 1346 | #define MCF_GPIO_PORTTH_PORTTH1 (0x02) |
---|
| 1347 | #define MCF_GPIO_PORTTH_PORTTH2 (0x04) |
---|
| 1348 | #define MCF_GPIO_PORTTH_PORTTH3 (0x08) |
---|
| 1349 | #define MCF_GPIO_PORTTH_PORTTH4 (0x10) |
---|
| 1350 | #define MCF_GPIO_PORTTH_PORTTH5 (0x20) |
---|
| 1351 | #define MCF_GPIO_PORTTH_PORTTH6 (0x40) |
---|
| 1352 | #define MCF_GPIO_PORTTH_PORTTH7 (0x80) |
---|
| 1353 | |
---|
| 1354 | /* Bit definitions and macros for MCF_GPIO_PORTTI */ |
---|
| 1355 | #define MCF_GPIO_PORTTI_PORTTI0 (0x01) |
---|
| 1356 | #define MCF_GPIO_PORTTI_PORTTI1 (0x02) |
---|
| 1357 | #define MCF_GPIO_PORTTI_PORTTI2 (0x04) |
---|
| 1358 | #define MCF_GPIO_PORTTI_PORTTI3 (0x08) |
---|
| 1359 | #define MCF_GPIO_PORTTI_PORTTI4 (0x10) |
---|
| 1360 | #define MCF_GPIO_PORTTI_PORTTI5 (0x20) |
---|
| 1361 | #define MCF_GPIO_PORTTI_PORTTI6 (0x40) |
---|
| 1362 | #define MCF_GPIO_PORTTI_PORTTI7 (0x80) |
---|
| 1363 | |
---|
| 1364 | /* Bit definitions and macros for MCF_GPIO_PORTUA */ |
---|
| 1365 | #define MCF_GPIO_PORTUA_PORTUA0 (0x01) |
---|
| 1366 | #define MCF_GPIO_PORTUA_PORTUA1 (0x02) |
---|
| 1367 | #define MCF_GPIO_PORTUA_PORTUA2 (0x04) |
---|
| 1368 | #define MCF_GPIO_PORTUA_PORTUA3 (0x08) |
---|
| 1369 | #define MCF_GPIO_PORTUA_PORTUA4 (0x10) |
---|
| 1370 | #define MCF_GPIO_PORTUA_PORTUA5 (0x20) |
---|
| 1371 | #define MCF_GPIO_PORTUA_PORTUA6 (0x40) |
---|
| 1372 | #define MCF_GPIO_PORTUA_PORTUA7 (0x80) |
---|
| 1373 | |
---|
| 1374 | /* Bit definitions and macros for MCF_GPIO_PORTUB */ |
---|
| 1375 | #define MCF_GPIO_PORTUB_PORTUB0 (0x01) |
---|
| 1376 | #define MCF_GPIO_PORTUB_PORTUB1 (0x02) |
---|
| 1377 | #define MCF_GPIO_PORTUB_PORTUB2 (0x04) |
---|
| 1378 | #define MCF_GPIO_PORTUB_PORTUB3 (0x08) |
---|
| 1379 | #define MCF_GPIO_PORTUB_PORTUB4 (0x10) |
---|
| 1380 | #define MCF_GPIO_PORTUB_PORTUB5 (0x20) |
---|
| 1381 | #define MCF_GPIO_PORTUB_PORTUB6 (0x40) |
---|
| 1382 | #define MCF_GPIO_PORTUB_PORTUB7 (0x80) |
---|
| 1383 | |
---|
| 1384 | /* Bit definitions and macros for MCF_GPIO_PORTUC */ |
---|
| 1385 | #define MCF_GPIO_PORTUC_PORTUC0 (0x01) |
---|
| 1386 | #define MCF_GPIO_PORTUC_PORTUC1 (0x02) |
---|
| 1387 | #define MCF_GPIO_PORTUC_PORTUC2 (0x04) |
---|
| 1388 | #define MCF_GPIO_PORTUC_PORTUC3 (0x08) |
---|
| 1389 | #define MCF_GPIO_PORTUC_PORTUC4 (0x10) |
---|
| 1390 | #define MCF_GPIO_PORTUC_PORTUC5 (0x20) |
---|
| 1391 | #define MCF_GPIO_PORTUC_PORTUC6 (0x40) |
---|
| 1392 | #define MCF_GPIO_PORTUC_PORTUC7 (0x80) |
---|
| 1393 | |
---|
| 1394 | /* Bit definitions and macros for MCF_GPIO_PORTDD */ |
---|
| 1395 | #define MCF_GPIO_PORTDD_PORTDD0 (0x01) |
---|
| 1396 | #define MCF_GPIO_PORTDD_PORTDD1 (0x02) |
---|
| 1397 | #define MCF_GPIO_PORTDD_PORTDD2 (0x04) |
---|
| 1398 | #define MCF_GPIO_PORTDD_PORTDD3 (0x08) |
---|
| 1399 | #define MCF_GPIO_PORTDD_PORTDD4 (0x10) |
---|
| 1400 | #define MCF_GPIO_PORTDD_PORTDD5 (0x20) |
---|
| 1401 | #define MCF_GPIO_PORTDD_PORTDD6 (0x40) |
---|
| 1402 | #define MCF_GPIO_PORTDD_PORTDD7 (0x80) |
---|
| 1403 | |
---|
| 1404 | /* Bit definitions and macros for MCF_GPIO_PORTLD */ |
---|
| 1405 | #define MCF_GPIO_PORTLD_PORTLD0 (0x01) |
---|
| 1406 | #define MCF_GPIO_PORTLD_PORTLD1 (0x02) |
---|
| 1407 | #define MCF_GPIO_PORTLD_PORTLD2 (0x04) |
---|
| 1408 | #define MCF_GPIO_PORTLD_PORTLD3 (0x08) |
---|
| 1409 | #define MCF_GPIO_PORTLD_PORTLD4 (0x10) |
---|
| 1410 | #define MCF_GPIO_PORTLD_PORTLD5 (0x20) |
---|
| 1411 | #define MCF_GPIO_PORTLD_PORTLD6 (0x40) |
---|
| 1412 | #define MCF_GPIO_PORTLD_PORTLD7 (0x80) |
---|
| 1413 | |
---|
| 1414 | /* Bit definitions and macros for MCF_GPIO_PORTGP */ |
---|
| 1415 | #define MCF_GPIO_PORTGP_PORTGP0 (0x01) |
---|
| 1416 | #define MCF_GPIO_PORTGP_PORTGP1 (0x02) |
---|
| 1417 | #define MCF_GPIO_PORTGP_PORTGP2 (0x04) |
---|
| 1418 | #define MCF_GPIO_PORTGP_PORTGP3 (0x08) |
---|
| 1419 | #define MCF_GPIO_PORTGP_PORTGP4 (0x10) |
---|
| 1420 | #define MCF_GPIO_PORTGP_PORTGP5 (0x20) |
---|
| 1421 | #define MCF_GPIO_PORTGP_PORTGP6 (0x40) |
---|
| 1422 | #define MCF_GPIO_PORTGP_PORTGP7 (0x80) |
---|
| 1423 | |
---|
| 1424 | /* Bit definitions and macros for MCF_GPIO_DDRNQ */ |
---|
| 1425 | #define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) |
---|
| 1426 | #define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) |
---|
| 1427 | #define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) |
---|
| 1428 | #define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) |
---|
| 1429 | #define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) |
---|
| 1430 | #define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) |
---|
| 1431 | #define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) |
---|
| 1432 | #define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) |
---|
| 1433 | |
---|
| 1434 | /* Bit definitions and macros for MCF_GPIO_DDRAN */ |
---|
| 1435 | #define MCF_GPIO_DDRAN_DDRAN0 (0x01) |
---|
| 1436 | #define MCF_GPIO_DDRAN_DDRAN1 (0x02) |
---|
| 1437 | #define MCF_GPIO_DDRAN_DDRAN2 (0x04) |
---|
| 1438 | #define MCF_GPIO_DDRAN_DDRAN3 (0x08) |
---|
| 1439 | #define MCF_GPIO_DDRAN_DDRAN4 (0x10) |
---|
| 1440 | #define MCF_GPIO_DDRAN_DDRAN5 (0x20) |
---|
| 1441 | #define MCF_GPIO_DDRAN_DDRAN6 (0x40) |
---|
| 1442 | #define MCF_GPIO_DDRAN_DDRAN7 (0x80) |
---|
| 1443 | |
---|
| 1444 | /* Bit definitions and macros for MCF_GPIO_DDRAS */ |
---|
| 1445 | #define MCF_GPIO_DDRAS_DDRAS0 (0x01) |
---|
| 1446 | #define MCF_GPIO_DDRAS_DDRAS1 (0x02) |
---|
| 1447 | #define MCF_GPIO_DDRAS_DDRAS2 (0x04) |
---|
| 1448 | #define MCF_GPIO_DDRAS_DDRAS3 (0x08) |
---|
| 1449 | #define MCF_GPIO_DDRAS_DDRAS4 (0x10) |
---|
| 1450 | #define MCF_GPIO_DDRAS_DDRAS5 (0x20) |
---|
| 1451 | #define MCF_GPIO_DDRAS_DDRAS6 (0x40) |
---|
| 1452 | #define MCF_GPIO_DDRAS_DDRAS7 (0x80) |
---|
| 1453 | |
---|
| 1454 | /* Bit definitions and macros for MCF_GPIO_DDRQS */ |
---|
| 1455 | #define MCF_GPIO_DDRQS_DDRQS0 (0x01) |
---|
| 1456 | #define MCF_GPIO_DDRQS_DDRQS1 (0x02) |
---|
| 1457 | #define MCF_GPIO_DDRQS_DDRQS2 (0x04) |
---|
| 1458 | #define MCF_GPIO_DDRQS_DDRQS3 (0x08) |
---|
| 1459 | #define MCF_GPIO_DDRQS_DDRQS4 (0x10) |
---|
| 1460 | #define MCF_GPIO_DDRQS_DDRQS5 (0x20) |
---|
| 1461 | #define MCF_GPIO_DDRQS_DDRQS6 (0x40) |
---|
| 1462 | #define MCF_GPIO_DDRQS_DDRQS7 (0x80) |
---|
| 1463 | |
---|
| 1464 | /* Bit definitions and macros for MCF_GPIO_DDRTA */ |
---|
| 1465 | #define MCF_GPIO_DDRTA_DDRTA0 (0x01) |
---|
| 1466 | #define MCF_GPIO_DDRTA_DDRTA1 (0x02) |
---|
| 1467 | #define MCF_GPIO_DDRTA_DDRTA2 (0x04) |
---|
| 1468 | #define MCF_GPIO_DDRTA_DDRTA3 (0x08) |
---|
| 1469 | #define MCF_GPIO_DDRTA_DDRTA4 (0x10) |
---|
| 1470 | #define MCF_GPIO_DDRTA_DDRTA5 (0x20) |
---|
| 1471 | #define MCF_GPIO_DDRTA_DDRTA6 (0x40) |
---|
| 1472 | #define MCF_GPIO_DDRTA_DDRTA7 (0x80) |
---|
| 1473 | |
---|
| 1474 | /* Bit definitions and macros for MCF_GPIO_DDRTC */ |
---|
| 1475 | #define MCF_GPIO_DDRTC_DDRTC0 (0x01) |
---|
| 1476 | #define MCF_GPIO_DDRTC_DDRTC1 (0x02) |
---|
| 1477 | #define MCF_GPIO_DDRTC_DDRTC2 (0x04) |
---|
| 1478 | #define MCF_GPIO_DDRTC_DDRTC3 (0x08) |
---|
| 1479 | |
---|
| 1480 | /* Bit definitions and macros for MCF_GPIO_DDRTD */ |
---|
| 1481 | #define MCF_GPIO_DDRTD_DDRTD0 (0x01) |
---|
| 1482 | #define MCF_GPIO_DDRTD_DDRTD1 (0x02) |
---|
| 1483 | #define MCF_GPIO_DDRTD_DDRTD2 (0x04) |
---|
| 1484 | #define MCF_GPIO_DDRTD_DDRTD3 (0x08) |
---|
| 1485 | #define MCF_GPIO_DDRTD_DDRTD4 (0x10) |
---|
| 1486 | #define MCF_GPIO_DDRTD_DDRTD5 (0x20) |
---|
| 1487 | #define MCF_GPIO_DDRTD_DDRTD6 (0x40) |
---|
| 1488 | #define MCF_GPIO_DDRTD_DDRTD7 (0x80) |
---|
| 1489 | |
---|
| 1490 | /* Bit definitions and macros for MCF_GPIO_DDRTE */ |
---|
| 1491 | #define MCF_GPIO_DDRTE_DDRTE0 (0x01) |
---|
| 1492 | #define MCF_GPIO_DDRTE_DDRTE1 (0x02) |
---|
| 1493 | #define MCF_GPIO_DDRTE_DDRTE2 (0x04) |
---|
| 1494 | #define MCF_GPIO_DDRTE_DDRTE3 (0x08) |
---|
| 1495 | #define MCF_GPIO_DDRTE_DDRTE4 (0x10) |
---|
| 1496 | #define MCF_GPIO_DDRTE_DDRTE5 (0x20) |
---|
| 1497 | #define MCF_GPIO_DDRTE_DDRTE6 (0x40) |
---|
| 1498 | #define MCF_GPIO_DDRTE_DDRTE7 (0x80) |
---|
| 1499 | |
---|
| 1500 | /* Bit definitions and macros for MCF_GPIO_DDRTF */ |
---|
| 1501 | #define MCF_GPIO_DDRTF_DDRTF0 (0x01) |
---|
| 1502 | #define MCF_GPIO_DDRTF_DDRTF1 (0x02) |
---|
| 1503 | #define MCF_GPIO_DDRTF_DDRTF2 (0x04) |
---|
| 1504 | #define MCF_GPIO_DDRTF_DDRTF3 (0x08) |
---|
| 1505 | #define MCF_GPIO_DDRTF_DDRTF4 (0x10) |
---|
| 1506 | #define MCF_GPIO_DDRTF_DDRTF5 (0x20) |
---|
| 1507 | #define MCF_GPIO_DDRTF_DDRTF6 (0x40) |
---|
| 1508 | #define MCF_GPIO_DDRTF_DDRTF7 (0x80) |
---|
| 1509 | |
---|
| 1510 | /* Bit definitions and macros for MCF_GPIO_DDRTG */ |
---|
| 1511 | #define MCF_GPIO_DDRTG_DDRTG0 (0x01) |
---|
| 1512 | #define MCF_GPIO_DDRTG_DDRTG1 (0x02) |
---|
| 1513 | #define MCF_GPIO_DDRTG_DDRTG2 (0x04) |
---|
| 1514 | #define MCF_GPIO_DDRTG_DDRTG3 (0x08) |
---|
| 1515 | #define MCF_GPIO_DDRTG_DDRTG4 (0x10) |
---|
| 1516 | #define MCF_GPIO_DDRTG_DDRTG5 (0x20) |
---|
| 1517 | #define MCF_GPIO_DDRTG_DDRTG6 (0x40) |
---|
| 1518 | #define MCF_GPIO_DDRTG_DDRTG7 (0x80) |
---|
| 1519 | |
---|
| 1520 | /* Bit definitions and macros for MCF_GPIO_DDRTH */ |
---|
| 1521 | #define MCF_GPIO_DDRTH_DDRTH0 (0x01) |
---|
| 1522 | #define MCF_GPIO_DDRTH_DDRTH1 (0x02) |
---|
| 1523 | #define MCF_GPIO_DDRTH_DDRTH2 (0x04) |
---|
| 1524 | #define MCF_GPIO_DDRTH_DDRTH3 (0x08) |
---|
| 1525 | #define MCF_GPIO_DDRTH_DDRTH4 (0x10) |
---|
| 1526 | #define MCF_GPIO_DDRTH_DDRTH5 (0x20) |
---|
| 1527 | #define MCF_GPIO_DDRTH_DDRTH6 (0x40) |
---|
| 1528 | #define MCF_GPIO_DDRTH_DDRTH7 (0x80) |
---|
| 1529 | |
---|
| 1530 | /* Bit definitions and macros for MCF_GPIO_DDRTI */ |
---|
| 1531 | #define MCF_GPIO_DDRTI_DDRTI0 (0x01) |
---|
| 1532 | #define MCF_GPIO_DDRTI_DDRTI1 (0x02) |
---|
| 1533 | #define MCF_GPIO_DDRTI_DDRTI2 (0x04) |
---|
| 1534 | #define MCF_GPIO_DDRTI_DDRTI3 (0x08) |
---|
| 1535 | #define MCF_GPIO_DDRTI_DDRTI4 (0x10) |
---|
| 1536 | #define MCF_GPIO_DDRTI_DDRTI5 (0x20) |
---|
| 1537 | #define MCF_GPIO_DDRTI_DDRTI6 (0x40) |
---|
| 1538 | #define MCF_GPIO_DDRTI_DDRTI7 (0x80) |
---|
| 1539 | |
---|
| 1540 | /* Bit definiTJons and macros for MCF_GPIO_DDRTJ */ |
---|
| 1541 | #define MCF_GPIO_DDRTJ_DDRTJ0 (0x01) |
---|
| 1542 | #define MCF_GPIO_DDRTJ_DDRTJ1 (0x02) |
---|
| 1543 | #define MCF_GPIO_DDRTJ_DDRTJ2 (0x04) |
---|
| 1544 | #define MCF_GPIO_DDRTJ_DDRTJ3 (0x08) |
---|
| 1545 | #define MCF_GPIO_DDRTJ_DDRTJ4 (0x10) |
---|
| 1546 | #define MCF_GPIO_DDRTJ_DDRTJ5 (0x20) |
---|
| 1547 | #define MCF_GPIO_DDRTJ_DDRTJ6 (0x40) |
---|
| 1548 | #define MCF_GPIO_DDRTJ_DDRTJ7 (0x80) |
---|
| 1549 | |
---|
| 1550 | /* Bit definitions and macros for MCF_GPIO_DDRUA */ |
---|
| 1551 | #define MCF_GPIO_DDRUA_DDRUA0 (0x01) |
---|
| 1552 | #define MCF_GPIO_DDRUA_DDRUA1 (0x02) |
---|
| 1553 | #define MCF_GPIO_DDRUA_DDRUA2 (0x04) |
---|
| 1554 | #define MCF_GPIO_DDRUA_DDRUA3 (0x08) |
---|
| 1555 | #define MCF_GPIO_DDRUA_DDRUA4 (0x10) |
---|
| 1556 | #define MCF_GPIO_DDRUA_DDRUA5 (0x20) |
---|
| 1557 | #define MCF_GPIO_DDRUA_DDRUA6 (0x40) |
---|
| 1558 | #define MCF_GPIO_DDRUA_DDRUA7 (0x80) |
---|
| 1559 | |
---|
| 1560 | /* Bit definitions and macros for MCF_GPIO_DDRUB */ |
---|
| 1561 | #define MCF_GPIO_DDRUB_DDRUB0 (0x01) |
---|
| 1562 | #define MCF_GPIO_DDRUB_DDRUB1 (0x02) |
---|
| 1563 | #define MCF_GPIO_DDRUB_DDRUB2 (0x04) |
---|
| 1564 | #define MCF_GPIO_DDRUB_DDRUB3 (0x08) |
---|
| 1565 | #define MCF_GPIO_DDRUB_DDRUB4 (0x10) |
---|
| 1566 | #define MCF_GPIO_DDRUB_DDRUB5 (0x20) |
---|
| 1567 | #define MCF_GPIO_DDRUB_DDRUB6 (0x40) |
---|
| 1568 | #define MCF_GPIO_DDRUB_DDRUB7 (0x80) |
---|
| 1569 | |
---|
| 1570 | /* Bit definitions and macros for MCF_GPIO_DDRUC */ |
---|
| 1571 | #define MCF_GPIO_DDRUC_DDRUC0 (0x01) |
---|
| 1572 | #define MCF_GPIO_DDRUC_DDRUC1 (0x02) |
---|
| 1573 | #define MCF_GPIO_DDRUC_DDRUC2 (0x04) |
---|
| 1574 | #define MCF_GPIO_DDRUC_DDRUC3 (0x08) |
---|
| 1575 | #define MCF_GPIO_DDRUC_DDRUC4 (0x10) |
---|
| 1576 | #define MCF_GPIO_DDRUC_DDRUC5 (0x20) |
---|
| 1577 | #define MCF_GPIO_DDRUC_DDRUC6 (0x40) |
---|
| 1578 | #define MCF_GPIO_DDRUC_DDRUC7 (0x80) |
---|
| 1579 | |
---|
| 1580 | /* Bit definitions and macros for MCF_GPIO_DDRDD */ |
---|
| 1581 | #define MCF_GPIO_DDRDD_DDRDD0 (0x01) |
---|
| 1582 | #define MCF_GPIO_DDRDD_DDRDD1 (0x02) |
---|
| 1583 | #define MCF_GPIO_DDRDD_DDRDD2 (0x04) |
---|
| 1584 | #define MCF_GPIO_DDRDD_DDRDD3 (0x08) |
---|
| 1585 | #define MCF_GPIO_DDRDD_DDRDD4 (0x10) |
---|
| 1586 | #define MCF_GPIO_DDRDD_DDRDD5 (0x20) |
---|
| 1587 | #define MCF_GPIO_DDRDD_DDRDD6 (0x40) |
---|
| 1588 | #define MCF_GPIO_DDRDD_DDRDD7 (0x80) |
---|
| 1589 | |
---|
| 1590 | /* Bit definitions and macros for MCF_GPIO_DDRLD */ |
---|
| 1591 | #define MCF_GPIO_DDRLD_DDRLD0 (0x01) |
---|
| 1592 | #define MCF_GPIO_DDRLD_DDRLD1 (0x02) |
---|
| 1593 | #define MCF_GPIO_DDRLD_DDRLD2 (0x04) |
---|
| 1594 | #define MCF_GPIO_DDRLD_DDRLD3 (0x08) |
---|
| 1595 | #define MCF_GPIO_DDRLD_DDRLD4 (0x10) |
---|
| 1596 | #define MCF_GPIO_DDRLD_DDRLD5 (0x20) |
---|
| 1597 | #define MCF_GPIO_DDRLD_DDRLD6 (0x40) |
---|
| 1598 | #define MCF_GPIO_DDRLD_DDRLD7 (0x80) |
---|
| 1599 | |
---|
| 1600 | /* Bit definitions and macros for MCF_GPIO_DDRGP */ |
---|
| 1601 | #define MCF_GPIO_DDRGP_DDRGP0 (0x01) |
---|
| 1602 | #define MCF_GPIO_DDRGP_DDRGP1 (0x02) |
---|
| 1603 | #define MCF_GPIO_DDRGP_DDRGP2 (0x04) |
---|
| 1604 | #define MCF_GPIO_DDRGP_DDRGP3 (0x08) |
---|
| 1605 | #define MCF_GPIO_DDRGP_DDRGP4 (0x10) |
---|
| 1606 | #define MCF_GPIO_DDRGP_DDRGP5 (0x20) |
---|
| 1607 | #define MCF_GPIO_DDRGP_DDRGP6 (0x40) |
---|
| 1608 | #define MCF_GPIO_DDRGP_DDRGP7 (0x80) |
---|
| 1609 | |
---|
| 1610 | /* Bit definitions and macros for MCF_GPIO_SETNQ */ |
---|
| 1611 | #define MCF_GPIO_SETNQ_SETNQ0 (0x01) |
---|
| 1612 | #define MCF_GPIO_SETNQ_SETNQ1 (0x02) |
---|
| 1613 | #define MCF_GPIO_SETNQ_SETNQ2 (0x04) |
---|
| 1614 | #define MCF_GPIO_SETNQ_SETNQ3 (0x08) |
---|
| 1615 | #define MCF_GPIO_SETNQ_SETNQ4 (0x10) |
---|
| 1616 | #define MCF_GPIO_SETNQ_SETNQ5 (0x20) |
---|
| 1617 | #define MCF_GPIO_SETNQ_SETNQ6 (0x40) |
---|
| 1618 | #define MCF_GPIO_SETNQ_SETNQ7 (0x80) |
---|
| 1619 | |
---|
| 1620 | /* Bit definitions and macros for MCF_GPIO_SETAN */ |
---|
| 1621 | #define MCF_GPIO_SETAN_SETAN0 (0x01) |
---|
| 1622 | #define MCF_GPIO_SETAN_SETAN1 (0x02) |
---|
| 1623 | #define MCF_GPIO_SETAN_SETAN2 (0x04) |
---|
| 1624 | #define MCF_GPIO_SETAN_SETAN3 (0x08) |
---|
| 1625 | #define MCF_GPIO_SETAN_SETAN4 (0x10) |
---|
| 1626 | #define MCF_GPIO_SETAN_SETAN5 (0x20) |
---|
| 1627 | #define MCF_GPIO_SETAN_SETAN6 (0x40) |
---|
| 1628 | #define MCF_GPIO_SETAN_SETAN7 (0x80) |
---|
| 1629 | |
---|
| 1630 | /* Bit definitions and macros for MCF_GPIO_SETAS */ |
---|
| 1631 | #define MCF_GPIO_SETAS_SETAS0 (0x01) |
---|
| 1632 | #define MCF_GPIO_SETAS_SETAS1 (0x02) |
---|
| 1633 | #define MCF_GPIO_SETAS_SETAS2 (0x04) |
---|
| 1634 | #define MCF_GPIO_SETAS_SETAS3 (0x08) |
---|
| 1635 | #define MCF_GPIO_SETAS_SETAS4 (0x10) |
---|
| 1636 | #define MCF_GPIO_SETAS_SETAS5 (0x20) |
---|
| 1637 | #define MCF_GPIO_SETAS_SETAS6 (0x40) |
---|
| 1638 | #define MCF_GPIO_SETAS_SETAS7 (0x80) |
---|
| 1639 | |
---|
| 1640 | /* Bit definitions and macros for MCF_GPIO_SETQS */ |
---|
| 1641 | #define MCF_GPIO_SETQS_SETQS0 (0x01) |
---|
| 1642 | #define MCF_GPIO_SETQS_SETQS1 (0x02) |
---|
| 1643 | #define MCF_GPIO_SETQS_SETQS2 (0x04) |
---|
| 1644 | #define MCF_GPIO_SETQS_SETQS3 (0x08) |
---|
| 1645 | #define MCF_GPIO_SETQS_SETQS4 (0x10) |
---|
| 1646 | #define MCF_GPIO_SETQS_SETQS5 (0x20) |
---|
| 1647 | #define MCF_GPIO_SETQS_SETQS6 (0x40) |
---|
| 1648 | #define MCF_GPIO_SETQS_SETQS7 (0x80) |
---|
| 1649 | |
---|
| 1650 | /* Bit definitions and macros for MCF_GPIO_SETTA */ |
---|
| 1651 | #define MCF_GPIO_SETTA_SETTA0 (0x01) |
---|
| 1652 | #define MCF_GPIO_SETTA_SETTA1 (0x02) |
---|
| 1653 | #define MCF_GPIO_SETTA_SETTA2 (0x04) |
---|
| 1654 | #define MCF_GPIO_SETTA_SETTA3 (0x08) |
---|
| 1655 | #define MCF_GPIO_SETTA_SETTA4 (0x10) |
---|
| 1656 | #define MCF_GPIO_SETTA_SETTA5 (0x20) |
---|
| 1657 | #define MCF_GPIO_SETTA_SETTA6 (0x40) |
---|
| 1658 | #define MCF_GPIO_SETTA_SETTA7 (0x80) |
---|
| 1659 | |
---|
| 1660 | /* Bit definitions and macros for MCF_GPIO_SETTC */ |
---|
| 1661 | #define MCF_GPIO_SETTC_SETTC0 (0x01) |
---|
| 1662 | #define MCF_GPIO_SETTC_SETTC1 (0x02) |
---|
| 1663 | #define MCF_GPIO_SETTC_SETTC2 (0x04) |
---|
| 1664 | #define MCF_GPIO_SETTC_SETTC3 (0x08) |
---|
| 1665 | #define MCF_GPIO_SETTC_SETTC4 (0x10) |
---|
| 1666 | #define MCF_GPIO_SETTC_SETTC5 (0x20) |
---|
| 1667 | #define MCF_GPIO_SETTC_SETTC6 (0x40) |
---|
| 1668 | #define MCF_GPIO_SETTC_SETTC7 (0x80) |
---|
| 1669 | |
---|
| 1670 | /* Bit definitions and macros for MCF_GPIO_SETTD */ |
---|
| 1671 | #define MCF_GPIO_SETTD_SETTD0 (0x01) |
---|
| 1672 | #define MCF_GPIO_SETTD_SETTD1 (0x02) |
---|
| 1673 | #define MCF_GPIO_SETTD_SETTD2 (0x04) |
---|
| 1674 | #define MCF_GPIO_SETTD_SETTD3 (0x08) |
---|
| 1675 | #define MCF_GPIO_SETTD_SETTD4 (0x10) |
---|
| 1676 | #define MCF_GPIO_SETTD_SETTD5 (0x20) |
---|
| 1677 | #define MCF_GPIO_SETTD_SETTD6 (0x40) |
---|
| 1678 | #define MCF_GPIO_SETTD_SETTD7 (0x80) |
---|
| 1679 | |
---|
| 1680 | /* Bit definitions and macros for MCF_GPIO_SETUA */ |
---|
| 1681 | #define MCF_GPIO_SETUA_SETUA0 (0x01) |
---|
| 1682 | #define MCF_GPIO_SETUA_SETUA1 (0x02) |
---|
| 1683 | #define MCF_GPIO_SETUA_SETUA2 (0x04) |
---|
| 1684 | #define MCF_GPIO_SETUA_SETUA3 (0x08) |
---|
| 1685 | #define MCF_GPIO_SETUA_SETUA4 (0x10) |
---|
| 1686 | #define MCF_GPIO_SETUA_SETUA5 (0x20) |
---|
| 1687 | #define MCF_GPIO_SETUA_SETUA6 (0x40) |
---|
| 1688 | #define MCF_GPIO_SETUA_SETUA7 (0x80) |
---|
| 1689 | |
---|
| 1690 | /* Bit definitions and macros for MCF_GPIO_SETUB */ |
---|
| 1691 | #define MCF_GPIO_SETUB_SETUB0 (0x01) |
---|
| 1692 | #define MCF_GPIO_SETUB_SETUB1 (0x02) |
---|
| 1693 | #define MCF_GPIO_SETUB_SETUB2 (0x04) |
---|
| 1694 | #define MCF_GPIO_SETUB_SETUB3 (0x08) |
---|
| 1695 | #define MCF_GPIO_SETUB_SETUB4 (0x10) |
---|
| 1696 | #define MCF_GPIO_SETUB_SETUB5 (0x20) |
---|
| 1697 | #define MCF_GPIO_SETUB_SETUB6 (0x40) |
---|
| 1698 | #define MCF_GPIO_SETUB_SETUB7 (0x80) |
---|
| 1699 | |
---|
| 1700 | /* Bit definitions and macros for MCF_GPIO_SETUC */ |
---|
| 1701 | #define MCF_GPIO_SETUC_SETUC0 (0x01) |
---|
| 1702 | #define MCF_GPIO_SETUC_SETUC1 (0x02) |
---|
| 1703 | #define MCF_GPIO_SETUC_SETUC2 (0x04) |
---|
| 1704 | #define MCF_GPIO_SETUC_SETUC3 (0x08) |
---|
| 1705 | #define MCF_GPIO_SETUC_SETUC4 (0x10) |
---|
| 1706 | #define MCF_GPIO_SETUC_SETUC5 (0x20) |
---|
| 1707 | #define MCF_GPIO_SETUC_SETUC6 (0x40) |
---|
| 1708 | #define MCF_GPIO_SETUC_SETUC7 (0x80) |
---|
| 1709 | |
---|
| 1710 | /* Bit definitions and macros for MCF_GPIO_SETDD */ |
---|
| 1711 | #define MCF_GPIO_SETDD_SETDD0 (0x01) |
---|
| 1712 | #define MCF_GPIO_SETDD_SETDD1 (0x02) |
---|
| 1713 | #define MCF_GPIO_SETDD_SETDD2 (0x04) |
---|
| 1714 | #define MCF_GPIO_SETDD_SETDD3 (0x08) |
---|
| 1715 | #define MCF_GPIO_SETDD_SETDD4 (0x10) |
---|
| 1716 | #define MCF_GPIO_SETDD_SETDD5 (0x20) |
---|
| 1717 | #define MCF_GPIO_SETDD_SETDD6 (0x40) |
---|
| 1718 | #define MCF_GPIO_SETDD_SETDD7 (0x80) |
---|
| 1719 | |
---|
| 1720 | /* Bit definitions and macros for MCF_GPIO_SETLD */ |
---|
| 1721 | #define MCF_GPIO_SETLD_SETLD0 (0x01) |
---|
| 1722 | #define MCF_GPIO_SETLD_SETLD1 (0x02) |
---|
| 1723 | #define MCF_GPIO_SETLD_SETLD2 (0x04) |
---|
| 1724 | #define MCF_GPIO_SETLD_SETLD3 (0x08) |
---|
| 1725 | #define MCF_GPIO_SETLD_SETLD4 (0x10) |
---|
| 1726 | #define MCF_GPIO_SETLD_SETLD5 (0x20) |
---|
| 1727 | #define MCF_GPIO_SETLD_SETLD6 (0x40) |
---|
| 1728 | #define MCF_GPIO_SETLD_SETLD7 (0x80) |
---|
| 1729 | |
---|
| 1730 | /* Bit definitions and macros for MCF_GPIO_SETGP */ |
---|
| 1731 | #define MCF_GPIO_SETGP_SETGP0 (0x01) |
---|
| 1732 | #define MCF_GPIO_SETGP_SETGP1 (0x02) |
---|
| 1733 | #define MCF_GPIO_SETGP_SETGP2 (0x04) |
---|
| 1734 | #define MCF_GPIO_SETGP_SETGP3 (0x08) |
---|
| 1735 | #define MCF_GPIO_SETGP_SETGP4 (0x10) |
---|
| 1736 | #define MCF_GPIO_SETGP_SETGP5 (0x20) |
---|
| 1737 | #define MCF_GPIO_SETGP_SETGP6 (0x40) |
---|
| 1738 | #define MCF_GPIO_SETGP_SETGP7 (0x80) |
---|
| 1739 | |
---|
| 1740 | /* Bit definitions and macros for MCF_GPIO_CLRNQ */ |
---|
| 1741 | #define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) |
---|
| 1742 | #define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) |
---|
| 1743 | #define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) |
---|
| 1744 | #define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) |
---|
| 1745 | #define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) |
---|
| 1746 | #define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) |
---|
| 1747 | #define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) |
---|
| 1748 | #define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) |
---|
| 1749 | |
---|
| 1750 | /* Bit definitions and macros for MCF_GPIO_CLRAN */ |
---|
| 1751 | #define MCF_GPIO_CLRAN_CLRAN0 (0x01) |
---|
| 1752 | #define MCF_GPIO_CLRAN_CLRAN1 (0x02) |
---|
| 1753 | #define MCF_GPIO_CLRAN_CLRAN2 (0x04) |
---|
| 1754 | #define MCF_GPIO_CLRAN_CLRAN3 (0x08) |
---|
| 1755 | #define MCF_GPIO_CLRAN_CLRAN4 (0x10) |
---|
| 1756 | #define MCF_GPIO_CLRAN_CLRAN5 (0x20) |
---|
| 1757 | #define MCF_GPIO_CLRAN_CLRAN6 (0x40) |
---|
| 1758 | #define MCF_GPIO_CLRAN_CLRAN7 (0x80) |
---|
| 1759 | |
---|
| 1760 | /* Bit definitions and macros for MCF_GPIO_CLRAS */ |
---|
| 1761 | #define MCF_GPIO_CLRAS_CLRAS0 (0x01) |
---|
| 1762 | #define MCF_GPIO_CLRAS_CLRAS1 (0x02) |
---|
| 1763 | #define MCF_GPIO_CLRAS_CLRAS2 (0x04) |
---|
| 1764 | #define MCF_GPIO_CLRAS_CLRAS3 (0x08) |
---|
| 1765 | #define MCF_GPIO_CLRAS_CLRAS4 (0x10) |
---|
| 1766 | #define MCF_GPIO_CLRAS_CLRAS5 (0x20) |
---|
| 1767 | #define MCF_GPIO_CLRAS_CLRAS6 (0x40) |
---|
| 1768 | #define MCF_GPIO_CLRAS_CLRAS7 (0x80) |
---|
| 1769 | |
---|
| 1770 | /* Bit definitions and macros for MCF_GPIO_CLRQS */ |
---|
| 1771 | #define MCF_GPIO_CLRQS_CLRQS0 (0x01) |
---|
| 1772 | #define MCF_GPIO_CLRQS_CLRQS1 (0x02) |
---|
| 1773 | #define MCF_GPIO_CLRQS_CLRQS2 (0x04) |
---|
| 1774 | #define MCF_GPIO_CLRQS_CLRQS3 (0x08) |
---|
| 1775 | #define MCF_GPIO_CLRQS_CLRQS4 (0x10) |
---|
| 1776 | #define MCF_GPIO_CLRQS_CLRQS5 (0x20) |
---|
| 1777 | #define MCF_GPIO_CLRQS_CLRQS6 (0x40) |
---|
| 1778 | #define MCF_GPIO_CLRQS_CLRQS7 (0x80) |
---|
| 1779 | |
---|
| 1780 | /* Bit definitions and macros for MCF_GPIO_CLRTA */ |
---|
| 1781 | #define MCF_GPIO_CLRTA_CLRTA0 (0x01) |
---|
| 1782 | #define MCF_GPIO_CLRTA_CLRTA1 (0x02) |
---|
| 1783 | #define MCF_GPIO_CLRTA_CLRTA2 (0x04) |
---|
| 1784 | #define MCF_GPIO_CLRTA_CLRTA3 (0x08) |
---|
| 1785 | #define MCF_GPIO_CLRTA_CLRTA4 (0x10) |
---|
| 1786 | #define MCF_GPIO_CLRTA_CLRTA5 (0x20) |
---|
| 1787 | #define MCF_GPIO_CLRTA_CLRTA6 (0x40) |
---|
| 1788 | #define MCF_GPIO_CLRTA_CLRTA7 (0x80) |
---|
| 1789 | |
---|
| 1790 | /* Bit definitions and macros for MCF_GPIO_CLRTC */ |
---|
| 1791 | #define MCF_GPIO_CLRTC_CLRTC0 (0x01) |
---|
| 1792 | #define MCF_GPIO_CLRTC_CLRTC1 (0x02) |
---|
| 1793 | #define MCF_GPIO_CLRTC_CLRTC2 (0x04) |
---|
| 1794 | #define MCF_GPIO_CLRTC_CLRTC3 (0x08) |
---|
| 1795 | #define MCF_GPIO_CLRTC_CLRTC4 (0x10) |
---|
| 1796 | #define MCF_GPIO_CLRTC_CLRTC5 (0x20) |
---|
| 1797 | #define MCF_GPIO_CLRTC_CLRTC6 (0x40) |
---|
| 1798 | #define MCF_GPIO_CLRTC_CLRTC7 (0x80) |
---|
| 1799 | |
---|
| 1800 | /* Bit definitions and macros for MCF_GPIO_CLRTD */ |
---|
| 1801 | #define MCF_GPIO_CLRTD_CLRTD0 (0x01) |
---|
| 1802 | #define MCF_GPIO_CLRTD_CLRTD1 (0x02) |
---|
| 1803 | #define MCF_GPIO_CLRTD_CLRTD2 (0x04) |
---|
| 1804 | #define MCF_GPIO_CLRTD_CLRTD3 (0x08) |
---|
| 1805 | #define MCF_GPIO_CLRTD_CLRTD4 (0x10) |
---|
| 1806 | #define MCF_GPIO_CLRTD_CLRTD5 (0x20) |
---|
| 1807 | #define MCF_GPIO_CLRTD_CLRTD6 (0x40) |
---|
| 1808 | #define MCF_GPIO_CLRTD_CLRTD7 (0x80) |
---|
| 1809 | |
---|
| 1810 | /* Bit definitions and macros for MCF_GPIO_CLRUA */ |
---|
| 1811 | #define MCF_GPIO_CLRUA_CLRUA0 (0x01) |
---|
| 1812 | #define MCF_GPIO_CLRUA_CLRUA1 (0x02) |
---|
| 1813 | #define MCF_GPIO_CLRUA_CLRUA2 (0x04) |
---|
| 1814 | #define MCF_GPIO_CLRUA_CLRUA3 (0x08) |
---|
| 1815 | #define MCF_GPIO_CLRUA_CLRUA4 (0x10) |
---|
| 1816 | #define MCF_GPIO_CLRUA_CLRUA5 (0x20) |
---|
| 1817 | #define MCF_GPIO_CLRUA_CLRUA6 (0x40) |
---|
| 1818 | #define MCF_GPIO_CLRUA_CLRUA7 (0x80) |
---|
| 1819 | |
---|
| 1820 | /* Bit definitions and macros for MCF_GPIO_CLRUB */ |
---|
| 1821 | #define MCF_GPIO_CLRUB_CLRUB0 (0x01) |
---|
| 1822 | #define MCF_GPIO_CLRUB_CLRUB1 (0x02) |
---|
| 1823 | #define MCF_GPIO_CLRUB_CLRUB2 (0x04) |
---|
| 1824 | #define MCF_GPIO_CLRUB_CLRUB3 (0x08) |
---|
| 1825 | #define MCF_GPIO_CLRUB_CLRUB4 (0x10) |
---|
| 1826 | #define MCF_GPIO_CLRUB_CLRUB5 (0x20) |
---|
| 1827 | #define MCF_GPIO_CLRUB_CLRUB6 (0x40) |
---|
| 1828 | #define MCF_GPIO_CLRUB_CLRUB7 (0x80) |
---|
| 1829 | |
---|
| 1830 | /* Bit definitions and macros for MCF_GPIO_CLRUC */ |
---|
| 1831 | #define MCF_GPIO_CLRUC_CLRUC0 (0x01) |
---|
| 1832 | #define MCF_GPIO_CLRUC_CLRUC1 (0x02) |
---|
| 1833 | #define MCF_GPIO_CLRUC_CLRUC2 (0x04) |
---|
| 1834 | #define MCF_GPIO_CLRUC_CLRUC3 (0x08) |
---|
| 1835 | #define MCF_GPIO_CLRUC_CLRUC4 (0x10) |
---|
| 1836 | #define MCF_GPIO_CLRUC_CLRUC5 (0x20) |
---|
| 1837 | #define MCF_GPIO_CLRUC_CLRUC6 (0x40) |
---|
| 1838 | #define MCF_GPIO_CLRUC_CLRUC7 (0x80) |
---|
| 1839 | |
---|
| 1840 | /* Bit definitions and macros for MCF_GPIO_CLRDD */ |
---|
| 1841 | #define MCF_GPIO_CLRDD_CLRDD0 (0x01) |
---|
| 1842 | #define MCF_GPIO_CLRDD_CLRDD1 (0x02) |
---|
| 1843 | #define MCF_GPIO_CLRDD_CLRDD2 (0x04) |
---|
| 1844 | #define MCF_GPIO_CLRDD_CLRDD3 (0x08) |
---|
| 1845 | #define MCF_GPIO_CLRDD_CLRDD4 (0x10) |
---|
| 1846 | #define MCF_GPIO_CLRDD_CLRDD5 (0x20) |
---|
| 1847 | #define MCF_GPIO_CLRDD_CLRDD6 (0x40) |
---|
| 1848 | #define MCF_GPIO_CLRDD_CLRDD7 (0x80) |
---|
| 1849 | |
---|
| 1850 | /* Bit definitions and macros for MCF_GPIO_CLRLD */ |
---|
| 1851 | #define MCF_GPIO_CLRLD_CLRLD0 (0x01) |
---|
| 1852 | #define MCF_GPIO_CLRLD_CLRLD1 (0x02) |
---|
| 1853 | #define MCF_GPIO_CLRLD_CLRLD2 (0x04) |
---|
| 1854 | #define MCF_GPIO_CLRLD_CLRLD3 (0x08) |
---|
| 1855 | #define MCF_GPIO_CLRLD_CLRLD4 (0x10) |
---|
| 1856 | #define MCF_GPIO_CLRLD_CLRLD5 (0x20) |
---|
| 1857 | #define MCF_GPIO_CLRLD_CLRLD6 (0x40) |
---|
| 1858 | #define MCF_GPIO_CLRLD_CLRLD7 (0x80) |
---|
| 1859 | |
---|
| 1860 | /* Bit definitions and macros for MCF_GPIO_CLRGP */ |
---|
| 1861 | #define MCF_GPIO_CLRGP_CLRGP0 (0x01) |
---|
| 1862 | #define MCF_GPIO_CLRGP_CLRGP1 (0x02) |
---|
| 1863 | #define MCF_GPIO_CLRGP_CLRGP2 (0x04) |
---|
| 1864 | #define MCF_GPIO_CLRGP_CLRGP3 (0x08) |
---|
| 1865 | #define MCF_GPIO_CLRGP_CLRGP4 (0x10) |
---|
| 1866 | #define MCF_GPIO_CLRGP_CLRGP5 (0x20) |
---|
| 1867 | #define MCF_GPIO_CLRGP_CLRGP6 (0x40) |
---|
| 1868 | #define MCF_GPIO_CLRGP_CLRGP7 (0x80) |
---|
| 1869 | |
---|
| 1870 | /* Bit definitions and macros for MCF_GPIO_PTIPAR */ |
---|
| 1871 | #define MCF_GPIO_PTIPAR_PTIPAR0 (0x01) |
---|
| 1872 | #define MCF_GPIO_PTIPAR_PTIPAR1 (0x02) |
---|
| 1873 | #define MCF_GPIO_PTIPAR_PTIPAR2 (0x04) |
---|
| 1874 | #define MCF_GPIO_PTIPAR_PTIPAR3 (0x08) |
---|
| 1875 | #define MCF_GPIO_PTIPAR_PTIPAR4 (0x10) |
---|
| 1876 | #define MCF_GPIO_PTIPAR_PTIPAR5 (0x20) |
---|
| 1877 | #define MCF_GPIO_PTIPAR_PTIPAR6 (0x40) |
---|
| 1878 | #define MCF_GPIO_PTIPAR_PTIPAR7 (0x80) |
---|
| 1879 | |
---|
| 1880 | /* Bit definitions and macros for MCF_GPIO_PTJPAR */ |
---|
| 1881 | #define MCF_GPIO_PTJPAR_PTJPAR0 (0x01) |
---|
| 1882 | #define MCF_GPIO_PTJPAR_PTJPAR1 (0x02) |
---|
| 1883 | #define MCF_GPIO_PTJPAR_PTJPAR2 (0x04) |
---|
| 1884 | #define MCF_GPIO_PTJPAR_PTJPAR3 (0x08) |
---|
| 1885 | #define MCF_GPIO_PTJPAR_PTJPAR4 (0x10) |
---|
| 1886 | #define MCF_GPIO_PTJPAR_PTJPAR5 (0x20) |
---|
| 1887 | #define MCF_GPIO_PTJPAR_PTJPAR6 (0x40) |
---|
| 1888 | #define MCF_GPIO_PTJPAR_PTJPAR7 (0x80) |
---|
| 1889 | |
---|
| 1890 | /* Bit definitions and macros for MCF_GPIO_PNQPAR */ |
---|
| 1891 | #define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) |
---|
| 1892 | #define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) |
---|
| 1893 | #define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) |
---|
| 1894 | #define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) |
---|
| 1895 | #define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) |
---|
| 1896 | #define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) |
---|
| 1897 | #define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) |
---|
| 1898 | #define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) |
---|
| 1899 | #define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) |
---|
| 1900 | #define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) |
---|
| 1901 | #define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) |
---|
| 1902 | #define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) |
---|
| 1903 | #define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) |
---|
| 1904 | #define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) |
---|
| 1905 | #define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) |
---|
| 1906 | #define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) |
---|
| 1907 | #define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) |
---|
| 1908 | #define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) |
---|
| 1909 | #define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) |
---|
| 1910 | #define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) |
---|
| 1911 | |
---|
| 1912 | /* Bit definitions and macros for MCF_GPIO_PANPAR */ |
---|
| 1913 | #define MCF_GPIO_PANPAR_PANPAR0 (0x01) |
---|
| 1914 | #define MCF_GPIO_PANPAR_PANPAR1 (0x02) |
---|
| 1915 | #define MCF_GPIO_PANPAR_PANPAR2 (0x04) |
---|
| 1916 | #define MCF_GPIO_PANPAR_PANPAR3 (0x08) |
---|
| 1917 | #define MCF_GPIO_PANPAR_PANPAR4 (0x10) |
---|
| 1918 | #define MCF_GPIO_PANPAR_PANPAR5 (0x20) |
---|
| 1919 | #define MCF_GPIO_PANPAR_PANPAR6 (0x40) |
---|
| 1920 | #define MCF_GPIO_PANPAR_PANPAR7 (0x80) |
---|
| 1921 | #define MCF_GPIO_PANPAR_AN0_GPIO (0x00) |
---|
| 1922 | #define MCF_GPIO_PANPAR_AN1_GPIO (0x00) |
---|
| 1923 | #define MCF_GPIO_PANPAR_AN2_GPIO (0x00) |
---|
| 1924 | #define MCF_GPIO_PANPAR_AN3_GPIO (0x00) |
---|
| 1925 | #define MCF_GPIO_PANPAR_AN4_GPIO (0x00) |
---|
| 1926 | #define MCF_GPIO_PANPAR_AN5_GPIO (0x00) |
---|
| 1927 | #define MCF_GPIO_PANPAR_AN6_GPIO (0x00) |
---|
| 1928 | #define MCF_GPIO_PANPAR_AN7_GPIO (0x00) |
---|
| 1929 | #define MCF_GPIO_PANPAR_AN0_AN0 (0x01) |
---|
| 1930 | #define MCF_GPIO_PANPAR_AN1_AN1 (0x02) |
---|
| 1931 | #define MCF_GPIO_PANPAR_AN2_AN2 (0x04) |
---|
| 1932 | #define MCF_GPIO_PANPAR_AN3_AN3 (0x08) |
---|
| 1933 | #define MCF_GPIO_PANPAR_AN4_AN4 (0x10) |
---|
| 1934 | #define MCF_GPIO_PANPAR_AN5_AN5 (0x20) |
---|
| 1935 | #define MCF_GPIO_PANPAR_AN6_AN6 (0x40) |
---|
| 1936 | #define MCF_GPIO_PANPAR_AN7_AN7 (0x80) |
---|
| 1937 | |
---|
| 1938 | /* Bit definitions and macros for MCF_GPIO_PASPAR */ |
---|
| 1939 | #define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) |
---|
| 1940 | #define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) |
---|
| 1941 | #define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) |
---|
| 1942 | #define MCF_GPIO_PASPAR_SCL_GPIO (0x00) |
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| 1943 | #define MCF_GPIO_PASPAR_SDA_GPIO (0x00) |
---|
| 1944 | #define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) |
---|
| 1945 | #define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) |
---|
| 1946 | #define MCF_GPIO_PASPAR_SCL_SCL (0x01) |
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| 1947 | #define MCF_GPIO_PASPAR_SDA_SDA (0x04) |
---|
| 1948 | #define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) |
---|
| 1949 | #define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) |
---|
| 1950 | #define MCF_GPIO_PASPAR_SCL_CANTX (0x02) |
---|
| 1951 | #define MCF_GPIO_PASPAR_SDA_CANRX (0x08) |
---|
| 1952 | #define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) |
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| 1953 | #define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) |
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| 1954 | #define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) |
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| 1955 | #define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) |
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| 1956 | |
---|
| 1957 | /* Bit definitions and macros for MCF_GPIO_PQSPAR */ |
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| 1958 | #define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) |
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| 1959 | #define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) |
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| 1960 | #define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) |
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| 1961 | #define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) |
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| 1962 | #define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) |
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| 1963 | #define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) |
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| 1964 | #define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) |
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| 1965 | #define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) |
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| 1966 | #define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) |
---|
| 1967 | #define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) |
---|
| 1968 | #define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) |
---|
| 1969 | #define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) |
---|
| 1970 | #define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) |
---|
| 1971 | #define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) |
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| 1972 | #define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) |
---|
| 1973 | #define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) |
---|
| 1974 | #define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) |
---|
| 1975 | #define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) |
---|
| 1976 | #define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) |
---|
| 1977 | #define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) |
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| 1978 | #define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) |
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| 1979 | #define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) |
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| 1980 | #define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) |
---|
| 1981 | #define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) |
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| 1982 | #define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) |
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| 1983 | #define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) |
---|
| 1984 | #define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) |
---|
| 1985 | #define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) |
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| 1986 | #define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) |
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| 1987 | #define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) |
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| 1988 | #define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) |
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| 1989 | |
---|
| 1990 | /* Bit definitions and macros for MCF_GPIO_PTAPAR */ |
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| 1991 | #define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) |
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| 1992 | #define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) |
---|
| 1993 | #define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) |
---|
| 1994 | #define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) |
---|
| 1995 | #define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) |
---|
| 1996 | #define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) |
---|
| 1997 | #define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) |
---|
| 1998 | #define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) |
---|
| 1999 | #define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) |
---|
| 2000 | #define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) |
---|
| 2001 | #define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) |
---|
| 2002 | #define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) |
---|
| 2003 | #define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) |
---|
| 2004 | #define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) |
---|
| 2005 | #define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) |
---|
| 2006 | #define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) |
---|
| 2007 | |
---|
| 2008 | /* Bit definitions and macros for MCF_GPIO_PTCPAR */ |
---|
| 2009 | #define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) |
---|
| 2010 | #define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) |
---|
| 2011 | #define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) |
---|
| 2012 | #define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) |
---|
| 2013 | #define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) |
---|
| 2014 | #define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) |
---|
| 2015 | #define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) |
---|
| 2016 | #define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) |
---|
| 2017 | #define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) |
---|
| 2018 | #define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) |
---|
| 2019 | #define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) |
---|
| 2020 | #define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) |
---|
| 2021 | #define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) |
---|
| 2022 | #define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) |
---|
| 2023 | #define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) |
---|
| 2024 | #define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) |
---|
| 2025 | #define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) |
---|
| 2026 | #define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) |
---|
| 2027 | #define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) |
---|
| 2028 | #define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) |
---|
| 2029 | |
---|
| 2030 | /* Bit definitions and macros for MCF_GPIO_PTDPAR */ |
---|
| 2031 | #define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) |
---|
| 2032 | #define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) |
---|
| 2033 | #define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) |
---|
| 2034 | #define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) |
---|
| 2035 | #define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) |
---|
| 2036 | #define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) |
---|
| 2037 | #define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) |
---|
| 2038 | #define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) |
---|
| 2039 | #define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) |
---|
| 2040 | #define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) |
---|
| 2041 | #define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) |
---|
| 2042 | #define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) |
---|
| 2043 | |
---|
| 2044 | /* Bit definitions and macros for MCF_GPIO_PTEPAR */ |
---|
| 2045 | #define MCF_GPIO_PTEPAR_PTEPAR0 (0x01) |
---|
| 2046 | #define MCF_GPIO_PTEPAR_PTEPAR1 (0x02) |
---|
| 2047 | #define MCF_GPIO_PTEPAR_PTEPAR2 (0x04) |
---|
| 2048 | #define MCF_GPIO_PTEPAR_PTEPAR3 (0x08) |
---|
| 2049 | #define MCF_GPIO_PTEPAR_PTEPAR4 (0x10) |
---|
| 2050 | #define MCF_GPIO_PTEPAR_PTEPAR5 (0x20) |
---|
| 2051 | #define MCF_GPIO_PTEPAR_PTEPAR6 (0x40) |
---|
| 2052 | #define MCF_GPIO_PTEPAR_PTEPAR7 (0x80) |
---|
| 2053 | |
---|
| 2054 | /* Bit definitions and macros for MCF_GPIO_PTFPAR */ |
---|
| 2055 | #define MCF_GPIO_PTFPAR_PTFPAR0 (0x01) |
---|
| 2056 | #define MCF_GPIO_PTFPAR_PTFPAR1 (0x02) |
---|
| 2057 | #define MCF_GPIO_PTFPAR_PTFPAR2 (0x04) |
---|
| 2058 | #define MCF_GPIO_PTFPAR_PTFPAR3 (0x08) |
---|
| 2059 | #define MCF_GPIO_PTFPAR_PTFPAR4 (0x10) |
---|
| 2060 | #define MCF_GPIO_PTFPAR_PTFPAR5 (0x20) |
---|
| 2061 | #define MCF_GPIO_PTFPAR_PTFPAR6 (0x40) |
---|
| 2062 | #define MCF_GPIO_PTFPAR_PTFPAR7 (0x80) |
---|
| 2063 | |
---|
| 2064 | /* Bit definitions and macros for MCF_GPIO_PTGPAR */ |
---|
| 2065 | #define MCF_GPIO_PTGPAR_PTGPAR0 (0x01) |
---|
| 2066 | #define MCF_GPIO_PTGPAR_PTGPAR1 (0x02) |
---|
| 2067 | #define MCF_GPIO_PTGPAR_PTGPAR2 (0x04) |
---|
| 2068 | #define MCF_GPIO_PTGPAR_PTGPAR3 (0x08) |
---|
| 2069 | #define MCF_GPIO_PTGPAR_PTGPAR4 (0x10) |
---|
| 2070 | #define MCF_GPIO_PTGPAR_PTGPAR5 (0x20) |
---|
| 2071 | #define MCF_GPIO_PTGPAR_PTGPAR6 (0x40) |
---|
| 2072 | #define MCF_GPIO_PTGPAR_PTGPAR7 (0x80) |
---|
| 2073 | |
---|
| 2074 | /* Bit definitions and macros for MCF_GPIO_PTHPAR */ |
---|
| 2075 | #define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x0003)<<0) |
---|
| 2076 | #define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x0003)<<2) |
---|
| 2077 | #define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x0003)<<4) |
---|
| 2078 | #define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x0003)<<6) |
---|
| 2079 | #define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x0003)<<8) |
---|
| 2080 | #define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x0003)<<10) |
---|
| 2081 | #define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x0003)<<12) |
---|
| 2082 | |
---|
| 2083 | |
---|
| 2084 | /* Bit definitions and macros for MCF_GPIO_PUAPAR */ |
---|
| 2085 | #define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) |
---|
| 2086 | #define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) |
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| 2087 | #define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) |
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| 2088 | #define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) |
---|
| 2089 | #define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) |
---|
| 2090 | #define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) |
---|
| 2091 | #define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) |
---|
| 2092 | #define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) |
---|
| 2093 | #define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) |
---|
| 2094 | #define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) |
---|
| 2095 | #define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) |
---|
| 2096 | #define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) |
---|
| 2097 | #define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) |
---|
| 2098 | #define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) |
---|
| 2099 | |
---|
| 2100 | /* Bit definitions and macros for MCF_GPIO_PUBPAR */ |
---|
| 2101 | #define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) |
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| 2102 | #define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) |
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| 2103 | #define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) |
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| 2104 | #define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) |
---|
| 2105 | #define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) |
---|
| 2106 | #define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) |
---|
| 2107 | #define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) |
---|
| 2108 | #define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) |
---|
| 2109 | #define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) |
---|
| 2110 | #define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) |
---|
| 2111 | #define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) |
---|
| 2112 | #define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) |
---|
| 2113 | #define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) |
---|
| 2114 | #define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) |
---|
| 2115 | #define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) |
---|
| 2116 | #define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) |
---|
| 2117 | |
---|
| 2118 | /* Bit definitions and macros for MCF_GPIO_PUCPAR */ |
---|
| 2119 | #define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x03)<<0) |
---|
| 2120 | #define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x03)<<2) |
---|
| 2121 | #define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x03)<<4) |
---|
| 2122 | #define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x03)<<6) |
---|
| 2123 | #define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) |
---|
| 2124 | #define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) |
---|
| 2125 | #define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) |
---|
| 2126 | #define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) |
---|
| 2127 | #define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) |
---|
| 2128 | #define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) |
---|
| 2129 | #define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) |
---|
| 2130 | #define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) |
---|
| 2131 | |
---|
| 2132 | /* Bit definitions and macros for MCF_GPIO_PDDPAR */ |
---|
| 2133 | #define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) |
---|
| 2134 | #define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) |
---|
| 2135 | #define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) |
---|
| 2136 | #define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) |
---|
| 2137 | #define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) |
---|
| 2138 | #define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) |
---|
| 2139 | #define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) |
---|
| 2140 | #define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) |
---|
| 2141 | #define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) |
---|
| 2142 | #define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) |
---|
| 2143 | #define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) |
---|
| 2144 | #define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) |
---|
| 2145 | #define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) |
---|
| 2146 | #define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) |
---|
| 2147 | #define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) |
---|
| 2148 | #define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) |
---|
| 2149 | #define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) |
---|
| 2150 | #define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) |
---|
| 2151 | #define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) |
---|
| 2152 | #define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) |
---|
| 2153 | #define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) |
---|
| 2154 | #define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) |
---|
| 2155 | #define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) |
---|
| 2156 | #define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) |
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| 2157 | |
---|
| 2158 | /* Bit definitions and macros for MCF_GPIO_PLDPAR */ |
---|
| 2159 | #define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) |
---|
| 2160 | #define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) |
---|
| 2161 | #define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) |
---|
| 2162 | #define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) |
---|
| 2163 | #define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) |
---|
| 2164 | #define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) |
---|
| 2165 | #define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) |
---|
| 2166 | #define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) |
---|
| 2167 | #define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) |
---|
| 2168 | #define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) |
---|
| 2169 | #define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) |
---|
| 2170 | #define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) |
---|
| 2171 | #define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) |
---|
| 2172 | #define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) |
---|
| 2173 | #define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) |
---|
| 2174 | #define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) |
---|
| 2175 | #define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) |
---|
| 2176 | #define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) |
---|
| 2177 | #define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) |
---|
| 2178 | #define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) |
---|
| 2179 | #define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) |
---|
| 2180 | |
---|
| 2181 | /* Bit definitions and macros for MCF_GPIO_PGPPAR */ |
---|
| 2182 | #define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) |
---|
| 2183 | #define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) |
---|
| 2184 | #define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) |
---|
| 2185 | #define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) |
---|
| 2186 | #define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) |
---|
| 2187 | #define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) |
---|
| 2188 | #define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) |
---|
| 2189 | #define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) |
---|
| 2190 | #define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) |
---|
| 2191 | #define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) |
---|
| 2192 | #define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) |
---|
| 2193 | #define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) |
---|
| 2194 | #define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) |
---|
| 2195 | #define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) |
---|
| 2196 | #define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) |
---|
| 2197 | #define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) |
---|
| 2198 | #define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) |
---|
| 2199 | #define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) |
---|
| 2200 | #define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) |
---|
| 2201 | #define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) |
---|
| 2202 | #define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) |
---|
| 2203 | #define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) |
---|
| 2204 | #define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) |
---|
| 2205 | #define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) |
---|
| 2206 | |
---|
| 2207 | /* Bit definitions and macros for MCF_GPIO_PWOR */ |
---|
| 2208 | #define MCF_GPIO_PWOR_PWOR0 (0x0001) |
---|
| 2209 | #define MCF_GPIO_PWOR_PWOR1 (0x0002) |
---|
| 2210 | #define MCF_GPIO_PWOR_PWOR2 (0x0004) |
---|
| 2211 | #define MCF_GPIO_PWOR_PWOR3 (0x0008) |
---|
| 2212 | #define MCF_GPIO_PWOR_PWOR4 (0x0010) |
---|
| 2213 | #define MCF_GPIO_PWOR_PWOR5 (0x0020) |
---|
| 2214 | #define MCF_GPIO_PWOR_PWOR6 (0x0040) |
---|
| 2215 | #define MCF_GPIO_PWOR_PWOR7 (0x0080) |
---|
| 2216 | #define MCF_GPIO_PWOR_PWOR8 (0x0100) |
---|
| 2217 | #define MCF_GPIO_PWOR_PWOR9 (0x0200) |
---|
| 2218 | #define MCF_GPIO_PWOR_PWOR10 (0x0400) |
---|
| 2219 | #define MCF_GPIO_PWOR_PWOR11 (0x0800) |
---|
| 2220 | #define MCF_GPIO_PWOR_PWOR12 (0x1000) |
---|
| 2221 | #define MCF_GPIO_PWOR_PWOR13 (0x2000) |
---|
| 2222 | #define MCF_GPIO_PWOR_PWOR14 (0x4000) |
---|
| 2223 | #define MCF_GPIO_PWOR_PWOR15 (0x8000) |
---|
| 2224 | |
---|
| 2225 | /* Bit definitions and macros for MCF_GPIO_PDSRH */ |
---|
| 2226 | #define MCF_GPIO_PDSRH_PDSR32 (0x0001) |
---|
| 2227 | #define MCF_GPIO_PDSRH_PDSR33 (0x0002) |
---|
| 2228 | #define MCF_GPIO_PDSRH_PDSR34 (0x0004) |
---|
| 2229 | #define MCF_GPIO_PDSRH_PDSR35 (0x0008) |
---|
| 2230 | #define MCF_GPIO_PDSRH_PDSR36 (0x0010) |
---|
| 2231 | #define MCF_GPIO_PDSRH_PDSR37 (0x0020) |
---|
| 2232 | #define MCF_GPIO_PDSRH_PDSR38 (0x0040) |
---|
| 2233 | #define MCF_GPIO_PDSRH_PDSR39 (0x0080) |
---|
| 2234 | #define MCF_GPIO_PDSRH_PDSR40 (0x0100) |
---|
| 2235 | #define MCF_GPIO_PDSRH_PDSR41 (0x0200) |
---|
| 2236 | #define MCF_GPIO_PDSRH_PDSR42 (0x0400) |
---|
| 2237 | #define MCF_GPIO_PDSRH_PDSR43 (0x0800) |
---|
| 2238 | #define MCF_GPIO_PDSRH_PDSR44 (0x1000) |
---|
| 2239 | #define MCF_GPIO_PDSRH_PDSR45 (0x2000) |
---|
| 2240 | #define MCF_GPIO_PDSRH_PDSR46 (0x4000) |
---|
| 2241 | #define MCF_GPIO_PDSRH_PDSR47 (0x8000) |
---|
| 2242 | |
---|
| 2243 | /* Bit definitions and macros for MCF_GPIO_PDSRL */ |
---|
| 2244 | #define MCF_GPIO_PDSRL_PDSR0 (0x00000001) |
---|
| 2245 | #define MCF_GPIO_PDSRL_PDSR1 (0x00000002) |
---|
| 2246 | #define MCF_GPIO_PDSRL_PDSR2 (0x00000004) |
---|
| 2247 | #define MCF_GPIO_PDSRL_PDSR3 (0x00000008) |
---|
| 2248 | #define MCF_GPIO_PDSRL_PDSR4 (0x00000010) |
---|
| 2249 | #define MCF_GPIO_PDSRL_PDSR5 (0x00000020) |
---|
| 2250 | #define MCF_GPIO_PDSRL_PDSR6 (0x00000040) |
---|
| 2251 | #define MCF_GPIO_PDSRL_PDSR7 (0x00000080) |
---|
| 2252 | #define MCF_GPIO_PDSRL_PDSR8 (0x00000100) |
---|
| 2253 | #define MCF_GPIO_PDSRL_PDSR9 (0x00000200) |
---|
| 2254 | #define MCF_GPIO_PDSRL_PDSR10 (0x00000400) |
---|
| 2255 | #define MCF_GPIO_PDSRL_PDSR11 (0x00000800) |
---|
| 2256 | #define MCF_GPIO_PDSRL_PDSR12 (0x00001000) |
---|
| 2257 | #define MCF_GPIO_PDSRL_PDSR13 (0x00002000) |
---|
| 2258 | #define MCF_GPIO_PDSRL_PDSR14 (0x00004000) |
---|
| 2259 | #define MCF_GPIO_PDSRL_PDSR15 (0x00008000) |
---|
| 2260 | #define MCF_GPIO_PDSRL_PDSR16 (0x00010000) |
---|
| 2261 | #define MCF_GPIO_PDSRL_PDSR17 (0x00020000) |
---|
| 2262 | #define MCF_GPIO_PDSRL_PDSR18 (0x00040000) |
---|
| 2263 | #define MCF_GPIO_PDSRL_PDSR19 (0x00080000) |
---|
| 2264 | #define MCF_GPIO_PDSRL_PDSR20 (0x00100000) |
---|
| 2265 | #define MCF_GPIO_PDSRL_PDSR21 (0x00200000) |
---|
| 2266 | #define MCF_GPIO_PDSRL_PDSR22 (0x00400000) |
---|
| 2267 | #define MCF_GPIO_PDSRL_PDSR23 (0x00800000) |
---|
| 2268 | #define MCF_GPIO_PDSRL_PDSR24 (0x01000000) |
---|
| 2269 | #define MCF_GPIO_PDSRL_PDSR25 (0x02000000) |
---|
| 2270 | #define MCF_GPIO_PDSRL_PDSR26 (0x04000000) |
---|
| 2271 | #define MCF_GPIO_PDSRL_PDSR27 (0x08000000) |
---|
| 2272 | #define MCF_GPIO_PDSRL_PDSR28 (0x10000000) |
---|
| 2273 | #define MCF_GPIO_PDSRL_PDSR29 (0x20000000) |
---|
| 2274 | #define MCF_GPIO_PDSRL_PDSR30 (0x40000000) |
---|
| 2275 | #define MCF_GPIO_PDSRL_PDSR31 (0x80000000) |
---|
| 2276 | |
---|
| 2277 | /********************************************************************* |
---|
| 2278 | * |
---|
| 2279 | * ColdFire Integration Module (CIM) |
---|
| 2280 | * |
---|
| 2281 | *********************************************************************/ |
---|
| 2282 | |
---|
| 2283 | /* Register read/write macros */ |
---|
| 2284 | #define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) |
---|
| 2285 | #define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) |
---|
| 2286 | #define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) |
---|
| 2287 | #define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) |
---|
| 2288 | #define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) |
---|
| 2289 | #define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) |
---|
| 2290 | |
---|
| 2291 | /* Bit definitions and macros for MCF_CIM_RCR */ |
---|
| 2292 | #define MCF_CIM_RCR_LVDE (0x01) |
---|
| 2293 | #define MCF_CIM_RCR_LVDRE (0x04) |
---|
| 2294 | #define MCF_CIM_RCR_LVDIE (0x08) |
---|
| 2295 | #define MCF_CIM_RCR_LVDF (0x10) |
---|
| 2296 | #define MCF_CIM_RCR_FRCRSTOUT (0x40) |
---|
| 2297 | #define MCF_CIM_RCR_SOFTRST (0x80) |
---|
| 2298 | |
---|
| 2299 | /* Bit definitions and macros for MCF_CIM_RSR */ |
---|
| 2300 | #define MCF_CIM_RSR_LOL (0x01) |
---|
| 2301 | #define MCF_CIM_RSR_LOC (0x02) |
---|
| 2302 | #define MCF_CIM_RSR_EXT (0x04) |
---|
| 2303 | #define MCF_CIM_RSR_POR (0x08) |
---|
| 2304 | #define MCF_CIM_RSR_WDR (0x10) |
---|
| 2305 | #define MCF_CIM_RSR_SOFT (0x20) |
---|
| 2306 | #define MCF_CIM_RSR_LVD (0x40) |
---|
| 2307 | |
---|
| 2308 | /* Bit definitions and macros for MCF_CIM_CCR */ |
---|
| 2309 | #define MCF_CIM_CCR_LOAD (0x8000) |
---|
| 2310 | #define MCF_CIM_CCR_EZPORT (0x05) |
---|
| 2311 | #define MCF_CIM_CCR_SCHIP (0x06) |
---|
| 2312 | #define MCF_CIM_CCR_MODE(x) (((x)&0x7)<<8) |
---|
| 2313 | |
---|
| 2314 | /* Bit definitions and macros for MCF_CIM_LPCR */ |
---|
| 2315 | #define MCF_CIM_LPCR_LVDSE (0x02) |
---|
| 2316 | #define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) |
---|
| 2317 | #define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) |
---|
| 2318 | #define MCF_CIM_LPCR_LPMD_STOP (0xC0) |
---|
| 2319 | #define MCF_CIM_LPCR_LPMD_WAIT (0x80) |
---|
| 2320 | #define MCF_CIM_LPCR_LPMD_DOZE (0x40) |
---|
| 2321 | #define MCF_CIM_LPCR_LPMD_RUN (0x00) |
---|
| 2322 | |
---|
| 2323 | /* Bit definitions and macros for MCF_CIM_RCON */ |
---|
| 2324 | #define MCF_CIM_RCON_RLOAD (0x0020) |
---|
| 2325 | |
---|
| 2326 | /********************************************************************* |
---|
| 2327 | * |
---|
| 2328 | * Clock Module (CLOCK) |
---|
| 2329 | * |
---|
| 2330 | *********************************************************************/ |
---|
| 2331 | |
---|
| 2332 | /* Register read/write macros */ |
---|
| 2333 | #define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) |
---|
| 2334 | #define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) |
---|
| 2335 | #define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) |
---|
| 2336 | #define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) |
---|
| 2337 | #define MCF_CLOCK_CCLR (*(vuint8 *)(&__IPSBAR[0x120009])) |
---|
| 2338 | #define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) |
---|
| 2339 | #define MCF_CLOCK_RTCCR (*(vuint8*)(&__IPSBAR[0x120012])) |
---|
| 2340 | |
---|
| 2341 | /* Bit definitions and macros for MCF_CLOCK_SYNCR */ |
---|
| 2342 | #define MCF_CLOCK_SYNCR_PLLEN (0x0001) |
---|
| 2343 | #define MCF_CLOCK_SYNCR_PLLMODE (0x0002) |
---|
| 2344 | #define MCF_CLOCK_SYNCR_CLKSRC (0x0004) |
---|
| 2345 | #define MCF_CLOCK_SYNCR_FWKUP (0x0020) |
---|
| 2346 | #define MCF_CLOCK_SYNCR_DISCLK (0x0040) |
---|
| 2347 | #define MCF_CLOCK_SYNCR_LOCEN (0x0080) |
---|
| 2348 | #define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) |
---|
| 2349 | #define MCF_CLOCK_SYNCR_LOCRE (0x0800) |
---|
| 2350 | #define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) |
---|
| 2351 | #define MCF_CLOCK_SYNCR_LOLRE (0x8000) |
---|
| 2352 | |
---|
| 2353 | /* Bit definitions and macros for MCF_CLOCK_SYNSR */ |
---|
| 2354 | #define MCF_CLOCK_SYNSR_LOCS (0x04) |
---|
| 2355 | #define MCF_CLOCK_SYNSR_LOCK (0x08) |
---|
| 2356 | #define MCF_CLOCK_SYNSR_LOCKS (0x10) |
---|
| 2357 | #define MCF_CLOCK_SYNSR_CRYOSC (0x20) |
---|
| 2358 | #define MCF_CLOCK_SYNSR_OCOSC (0x40) |
---|
| 2359 | #define MCF_CLOCK_SYNSR_EXTOSC (0x80) |
---|
| 2360 | |
---|
| 2361 | /* Bit definitions and macros for MCF_CLOCK_LPCR */ |
---|
| 2362 | #define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) |
---|
| 2363 | |
---|
| 2364 | /* Bit definitions and macros for MCF_CLOCK_CCHR */ |
---|
| 2365 | #define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) |
---|
| 2366 | |
---|
| 2367 | /* Bit definitions and macros for MCF_CLOCK_CCHR */ |
---|
| 2368 | #define MCF_CLOCK_CCLR_PRIM_OSC (0x00) |
---|
| 2369 | #define MCF_CLOCK_CCLR_REL_OSC (0x01) |
---|
| 2370 | #define MCF_CLOCK_CCLR_SEC_OSC (0x02) |
---|
| 2371 | #define MCF_CLOCK_CCLR_SEC1_OSC (0x03) |
---|
| 2372 | |
---|
| 2373 | /* Bit definitions and macros for MCF_CLOCK_RTCDR */ |
---|
| 2374 | #define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 2375 | |
---|
| 2376 | /* Bit definitions and macros for MCF_CLOCK_RTCCR */ |
---|
| 2377 | #define MCF_CLOCK_RTCCR_RTCSEL 0x01U |
---|
| 2378 | #define MCF_CLOCK_RTCCR_LPEN 0x02U |
---|
| 2379 | #define MCF_CLOCK_RTCCR_REFS 0x04U |
---|
| 2380 | #define MCF_CLOCK_RTCCR_KHZEN 0x08U |
---|
| 2381 | #define MCF_CLOCK_RTCCR_OSCEN 0x10U |
---|
| 2382 | #define MCF_CLOCK_RTCCR_EXTALEN 0x40U |
---|
| 2383 | |
---|
| 2384 | /********************************************************************* |
---|
| 2385 | * |
---|
| 2386 | * Edge Port Module (EPORT) |
---|
| 2387 | * |
---|
| 2388 | *********************************************************************/ |
---|
| 2389 | |
---|
| 2390 | /* Register read/write macros */ |
---|
| 2391 | #define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) |
---|
| 2392 | #define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) |
---|
| 2393 | #define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) |
---|
| 2394 | #define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) |
---|
| 2395 | #define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) |
---|
| 2396 | #define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) |
---|
| 2397 | |
---|
| 2398 | /* Bit definitions and macros for MCF_EPORT_EPPAR */ |
---|
| 2399 | #define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) |
---|
| 2400 | #define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) |
---|
| 2401 | #define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) |
---|
| 2402 | #define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) |
---|
| 2403 | #define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) |
---|
| 2404 | #define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) |
---|
| 2405 | #define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) |
---|
| 2406 | #define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) |
---|
| 2407 | #define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) |
---|
| 2408 | #define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) |
---|
| 2409 | #define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) |
---|
| 2410 | #define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) |
---|
| 2411 | #define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) |
---|
| 2412 | #define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) |
---|
| 2413 | #define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) |
---|
| 2414 | #define MCF_EPORT_EPPAR_LEVEL (0) |
---|
| 2415 | #define MCF_EPORT_EPPAR_RISING (1) |
---|
| 2416 | #define MCF_EPORT_EPPAR_FALLING (2) |
---|
| 2417 | #define MCF_EPORT_EPPAR_BOTH (3) |
---|
| 2418 | #define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) |
---|
| 2419 | #define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) |
---|
| 2420 | #define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) |
---|
| 2421 | #define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) |
---|
| 2422 | #define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) |
---|
| 2423 | #define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) |
---|
| 2424 | #define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) |
---|
| 2425 | #define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) |
---|
| 2426 | #define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) |
---|
| 2427 | #define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) |
---|
| 2428 | #define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) |
---|
| 2429 | #define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) |
---|
| 2430 | #define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) |
---|
| 2431 | #define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) |
---|
| 2432 | #define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) |
---|
| 2433 | #define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) |
---|
| 2434 | #define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) |
---|
| 2435 | #define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) |
---|
| 2436 | #define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) |
---|
| 2437 | #define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) |
---|
| 2438 | #define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) |
---|
| 2439 | #define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) |
---|
| 2440 | #define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) |
---|
| 2441 | #define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) |
---|
| 2442 | #define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) |
---|
| 2443 | #define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) |
---|
| 2444 | #define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) |
---|
| 2445 | #define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) |
---|
| 2446 | #define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) |
---|
| 2447 | #define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) |
---|
| 2448 | #define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) |
---|
| 2449 | #define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) |
---|
| 2450 | #define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) |
---|
| 2451 | #define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) |
---|
| 2452 | #define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) |
---|
| 2453 | #define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) |
---|
| 2454 | #define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) |
---|
| 2455 | #define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) |
---|
| 2456 | #define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) |
---|
| 2457 | #define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) |
---|
| 2458 | #define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) |
---|
| 2459 | #define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) |
---|
| 2460 | #define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) |
---|
| 2461 | #define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) |
---|
| 2462 | #define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) |
---|
| 2463 | #define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) |
---|
| 2464 | #define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) |
---|
| 2465 | #define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) |
---|
| 2466 | #define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) |
---|
| 2467 | #define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) |
---|
| 2468 | #define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) |
---|
| 2469 | #define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) |
---|
| 2470 | #define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) |
---|
| 2471 | #define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) |
---|
| 2472 | #define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) |
---|
| 2473 | #define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) |
---|
| 2474 | #define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) |
---|
| 2475 | #define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) |
---|
| 2476 | #define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) |
---|
| 2477 | #define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) |
---|
| 2478 | |
---|
| 2479 | /* Bit definitions and macros for MCF_EPORT_EPDDR */ |
---|
| 2480 | #define MCF_EPORT_EPDDR_EPDD1 (0x02) |
---|
| 2481 | #define MCF_EPORT_EPDDR_EPDD2 (0x04) |
---|
| 2482 | #define MCF_EPORT_EPDDR_EPDD3 (0x08) |
---|
| 2483 | #define MCF_EPORT_EPDDR_EPDD4 (0x10) |
---|
| 2484 | #define MCF_EPORT_EPDDR_EPDD5 (0x20) |
---|
| 2485 | #define MCF_EPORT_EPDDR_EPDD6 (0x40) |
---|
| 2486 | #define MCF_EPORT_EPDDR_EPDD7 (0x80) |
---|
| 2487 | #define MCF_EPORT_EPDDR_EPDD8 (0x01) |
---|
| 2488 | #define MCF_EPORT_EPDDR_EPDD9 (0x02) |
---|
| 2489 | #define MCF_EPORT_EPDDR_EPDD10 (0x04) |
---|
| 2490 | #define MCF_EPORT_EPDDR_EPDD11 (0x08) |
---|
| 2491 | #define MCF_EPORT_EPDDR_EPDD12 (0x10) |
---|
| 2492 | #define MCF_EPORT_EPDDR_EPDD13 (0x20) |
---|
| 2493 | #define MCF_EPORT_EPDDR_EPDD14 (0x40) |
---|
| 2494 | #define MCF_EPORT_EPDDR_EPDD15 (0x80) |
---|
| 2495 | |
---|
| 2496 | /* Bit definitions and macros for MCF_EPORT_EPIER */ |
---|
| 2497 | #define MCF_EPORT_EPIER_EPIE1 (0x02) |
---|
| 2498 | #define MCF_EPORT_EPIER_EPIE2 (0x04) |
---|
| 2499 | #define MCF_EPORT_EPIER_EPIE3 (0x08) |
---|
| 2500 | #define MCF_EPORT_EPIER_EPIE4 (0x10) |
---|
| 2501 | #define MCF_EPORT_EPIER_EPIE5 (0x20) |
---|
| 2502 | #define MCF_EPORT_EPIER_EPIE6 (0x40) |
---|
| 2503 | #define MCF_EPORT_EPIER_EPIE7 (0x80) |
---|
| 2504 | #define MCF_EPORT_EPIER_EPIE8 (0x01) |
---|
| 2505 | #define MCF_EPORT_EPIER_EPIE9 (0x02) |
---|
| 2506 | #define MCF_EPORT_EPIER_EPIE10 (0x04) |
---|
| 2507 | #define MCF_EPORT_EPIER_EPIE11 (0x08) |
---|
| 2508 | #define MCF_EPORT_EPIER_EPIE12 (0x10) |
---|
| 2509 | #define MCF_EPORT_EPIER_EPIE13 (0x20) |
---|
| 2510 | #define MCF_EPORT_EPIER_EPIE14 (0x40) |
---|
| 2511 | #define MCF_EPORT_EPIER_EPIE15 (0x80) |
---|
| 2512 | |
---|
| 2513 | /* Bit definitions and macros for MCF_EPORT_EPDR */ |
---|
| 2514 | #define MCF_EPORT_EPDR_EPD1 (0x02) |
---|
| 2515 | #define MCF_EPORT_EPDR_EPD2 (0x04) |
---|
| 2516 | #define MCF_EPORT_EPDR_EPD3 (0x08) |
---|
| 2517 | #define MCF_EPORT_EPDR_EPD4 (0x10) |
---|
| 2518 | #define MCF_EPORT_EPDR_EPD5 (0x20) |
---|
| 2519 | #define MCF_EPORT_EPDR_EPD6 (0x40) |
---|
| 2520 | #define MCF_EPORT_EPDR_EPD7 (0x80) |
---|
| 2521 | #define MCF_EPORT_EPDR_EPD8 (0x01) |
---|
| 2522 | #define MCF_EPORT_EPDR_EPD9 (0x02) |
---|
| 2523 | #define MCF_EPORT_EPDR_EPD10 (0x04) |
---|
| 2524 | #define MCF_EPORT_EPDR_EPD11 (0x08) |
---|
| 2525 | #define MCF_EPORT_EPDR_EPD12 (0x10) |
---|
| 2526 | #define MCF_EPORT_EPDR_EPD13 (0x20) |
---|
| 2527 | #define MCF_EPORT_EPDR_EPD14 (0x40) |
---|
| 2528 | #define MCF_EPORT_EPDR_EPD15 (0x80) |
---|
| 2529 | |
---|
| 2530 | /* Bit definitions and macros for MCF_EPORT_EPPDR */ |
---|
| 2531 | #define MCF_EPORT_EPPDR_EPPD1 (0x02) |
---|
| 2532 | #define MCF_EPORT_EPPDR_EPPD2 (0x04) |
---|
| 2533 | #define MCF_EPORT_EPPDR_EPPD3 (0x08) |
---|
| 2534 | #define MCF_EPORT_EPPDR_EPPD4 (0x10) |
---|
| 2535 | #define MCF_EPORT_EPPDR_EPPD5 (0x20) |
---|
| 2536 | #define MCF_EPORT_EPPDR_EPPD6 (0x40) |
---|
| 2537 | #define MCF_EPORT_EPPDR_EPPD7 (0x80) |
---|
| 2538 | #define MCF_EPORT_EPPDR_EPPD8 (0x01) |
---|
| 2539 | #define MCF_EPORT_EPPDR_EPPD9 (0x02) |
---|
| 2540 | #define MCF_EPORT_EPPDR_EPPD10 (0x04) |
---|
| 2541 | #define MCF_EPORT_EPPDR_EPPD11 (0x08) |
---|
| 2542 | #define MCF_EPORT_EPPDR_EPPD12 (0x10) |
---|
| 2543 | #define MCF_EPORT_EPPDR_EPPD13 (0x20) |
---|
| 2544 | #define MCF_EPORT_EPPDR_EPPD14 (0x40) |
---|
| 2545 | #define MCF_EPORT_EPPDR_EPPD15 (0x80) |
---|
| 2546 | |
---|
| 2547 | /* Bit definitions and macros for MCF_EPORT_EPFR */ |
---|
| 2548 | #define MCF_EPORT_EPFR_EPF1 (0x02) |
---|
| 2549 | #define MCF_EPORT_EPFR_EPF2 (0x04) |
---|
| 2550 | #define MCF_EPORT_EPFR_EPF3 (0x08) |
---|
| 2551 | #define MCF_EPORT_EPFR_EPF4 (0x10) |
---|
| 2552 | #define MCF_EPORT_EPFR_EPF5 (0x20) |
---|
| 2553 | #define MCF_EPORT_EPFR_EPF6 (0x40) |
---|
| 2554 | #define MCF_EPORT_EPFR_EPF7 (0x80) |
---|
| 2555 | #define MCF_EPORT_EPFR_EPF8 (0x01) |
---|
| 2556 | #define MCF_EPORT_EPFR_EPF9 (0x02) |
---|
| 2557 | #define MCF_EPORT_EPFR_EPF10 (0x04) |
---|
| 2558 | #define MCF_EPORT_EPFR_EPF11 (0x08) |
---|
| 2559 | #define MCF_EPORT_EPFR_EPF12 (0x10) |
---|
| 2560 | #define MCF_EPORT_EPFR_EPF13 (0x20) |
---|
| 2561 | #define MCF_EPORT_EPFR_EPF14 (0x40) |
---|
| 2562 | #define MCF_EPORT_EPFR_EPF15 (0x80) |
---|
| 2563 | |
---|
| 2564 | |
---|
| 2565 | /********************************************************************* |
---|
| 2566 | * |
---|
| 2567 | * Backup Watchdog Timer Module (BWT) |
---|
| 2568 | * |
---|
| 2569 | *********************************************************************/ |
---|
| 2570 | |
---|
| 2571 | #define MCF_BWT_WCR (*(vuint16*)(&__IPSBAR[0x140000])) |
---|
| 2572 | #define MCF_BWT_WMR (*(vuint16*)(&__IPSBAR[0x140002])) |
---|
| 2573 | #define MCF_BWT_WCNTR (*(vuint16*)(&__IPSBAR[0x140004])) |
---|
| 2574 | #define MCF_BWT_WSR (*(vuint16*)(&__IPSBAR[0x140006])) |
---|
| 2575 | |
---|
| 2576 | /* Bit definitions and macros for MCF_BWT_WCR */ |
---|
| 2577 | #define MCF_BWT_WCR_EN 0x01 |
---|
| 2578 | #define MCF_BWT_WCR_DOZE 0x04 |
---|
| 2579 | #define MCF_BWT_WCR_WAIT 0x08 |
---|
| 2580 | #define MCF_BWT_WCR_STOP 0x10 |
---|
| 2581 | |
---|
| 2582 | #define MCF_BWT_WSR_SEQ1 0x5555 |
---|
| 2583 | #define MCF_BWT_WSR_SEQ2 0xAAAA |
---|
| 2584 | |
---|
| 2585 | //MPR: TODO this Modules is new in mcf52258 vs. mcf52235 and some macros must be written first |
---|
| 2586 | |
---|
| 2587 | /********************************************************************* |
---|
| 2588 | * |
---|
| 2589 | * Programmable Interrupt Timer Modules (PIT) |
---|
| 2590 | * |
---|
| 2591 | *********************************************************************/ |
---|
| 2592 | |
---|
| 2593 | /* Register read/write macros */ |
---|
| 2594 | #define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) |
---|
| 2595 | #define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) |
---|
| 2596 | #define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) |
---|
| 2597 | #define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) |
---|
| 2598 | #define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) |
---|
| 2599 | #define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) |
---|
| 2600 | #define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) |
---|
| 2601 | #define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) |
---|
| 2602 | #define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) |
---|
| 2603 | |
---|
| 2604 | /* Bit definitions and macros for MCF_PIT_PCSR */ |
---|
| 2605 | #define MCF_PIT_PCSR_EN (0x0001) |
---|
| 2606 | #define MCF_PIT_PCSR_RLD (0x0002) |
---|
| 2607 | #define MCF_PIT_PCSR_PIF (0x0004) |
---|
| 2608 | #define MCF_PIT_PCSR_PIE (0x0008) |
---|
| 2609 | #define MCF_PIT_PCSR_OVW (0x0010) |
---|
| 2610 | #define MCF_PIT_PCSR_HALTED (0x0020) |
---|
| 2611 | #define MCF_PIT_PCSR_DOZE (0x0040) |
---|
| 2612 | #define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) |
---|
| 2613 | |
---|
| 2614 | /* Bit definitions and macros for MCF_PIT_PMR */ |
---|
| 2615 | #define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) |
---|
| 2616 | |
---|
| 2617 | /* Bit definitions and macros for MCF_PIT_PCNTR */ |
---|
| 2618 | #define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) |
---|
| 2619 | |
---|
| 2620 | /********************************************************************* |
---|
| 2621 | * |
---|
| 2622 | * Analog-to-Digital Converter (ADC) |
---|
| 2623 | * |
---|
| 2624 | *********************************************************************/ |
---|
| 2625 | |
---|
| 2626 | /* Register read/write macros */ |
---|
| 2627 | #define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) |
---|
| 2628 | #define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) |
---|
| 2629 | #define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) |
---|
| 2630 | #define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) |
---|
| 2631 | #define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) |
---|
| 2632 | #define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) |
---|
| 2633 | #define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) |
---|
| 2634 | #define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) |
---|
| 2635 | #define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) |
---|
| 2636 | #define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) |
---|
| 2637 | #define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) |
---|
| 2638 | #define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) |
---|
| 2639 | #define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) |
---|
| 2640 | #define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) |
---|
| 2641 | #define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) |
---|
| 2642 | #define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) |
---|
| 2643 | #define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) |
---|
| 2644 | #define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) |
---|
| 2645 | #define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) |
---|
| 2646 | #define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) |
---|
| 2647 | #define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) |
---|
| 2648 | #define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) |
---|
| 2649 | #define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) |
---|
| 2650 | #define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) |
---|
| 2651 | #define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) |
---|
| 2652 | #define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) |
---|
| 2653 | #define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) |
---|
| 2654 | #define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) |
---|
| 2655 | #define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) |
---|
| 2656 | #define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) |
---|
| 2657 | #define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) |
---|
| 2658 | #define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) |
---|
| 2659 | #define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) |
---|
| 2660 | #define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) |
---|
| 2661 | #define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) |
---|
| 2662 | #define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) |
---|
| 2663 | #define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) |
---|
| 2664 | #define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) |
---|
| 2665 | #define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) |
---|
| 2666 | #define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) |
---|
| 2667 | #define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) |
---|
| 2668 | #define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) |
---|
| 2669 | #define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) |
---|
| 2670 | #define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) |
---|
| 2671 | #define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) |
---|
| 2672 | #define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) |
---|
| 2673 | #define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) |
---|
| 2674 | |
---|
| 2675 | /* Bit definitions and macros for MCF_ADC_CTRL1 */ |
---|
| 2676 | #define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) |
---|
| 2677 | #define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) |
---|
| 2678 | #define MCF_ADC_CTRL1_HLMTIE (0x0100) |
---|
| 2679 | #define MCF_ADC_CTRL1_LLMTIE (0x0200) |
---|
| 2680 | #define MCF_ADC_CTRL1_ZCIE (0x0400) |
---|
| 2681 | #define MCF_ADC_CTRL1_EOSIE0 (0x0800) |
---|
| 2682 | #define MCF_ADC_CTRL1_SYNC0 (0x1000) |
---|
| 2683 | #define MCF_ADC_CTRL1_START0 (0x2000) |
---|
| 2684 | #define MCF_ADC_CTRL1_STOP0 (0x4000) |
---|
| 2685 | |
---|
| 2686 | /* Bit definitions and macros for MCF_ADC_CTRL2 */ |
---|
| 2687 | #define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) |
---|
| 2688 | #define MCF_ADC_CTRL2_SIMULT (0x0020) |
---|
| 2689 | #define MCF_ADC_CTRL2_EOSIE1 (0x0800) |
---|
| 2690 | #define MCF_ADC_CTRL2_SYNC1 (0x1000) |
---|
| 2691 | #define MCF_ADC_CTRL2_START1 (0x2000) |
---|
| 2692 | #define MCF_ADC_CTRL2_STOP1 (0x4000) |
---|
| 2693 | |
---|
| 2694 | /* Bit definitions and macros for MCF_ADC_ADZCC */ |
---|
| 2695 | #define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) |
---|
| 2696 | #define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) |
---|
| 2697 | #define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) |
---|
| 2698 | #define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) |
---|
| 2699 | #define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) |
---|
| 2700 | #define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) |
---|
| 2701 | #define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) |
---|
| 2702 | #define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) |
---|
| 2703 | |
---|
| 2704 | /* Bit definitions and macros for MCF_ADC_ADLST1 */ |
---|
| 2705 | #define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) |
---|
| 2706 | #define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) |
---|
| 2707 | #define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) |
---|
| 2708 | #define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) |
---|
| 2709 | |
---|
| 2710 | /* Bit definitions and macros for MCF_ADC_ADLST2 */ |
---|
| 2711 | #define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) |
---|
| 2712 | #define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) |
---|
| 2713 | #define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) |
---|
| 2714 | #define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) |
---|
| 2715 | |
---|
| 2716 | /* Bit definitions and macros for MCF_ADC_ADSDIS */ |
---|
| 2717 | #define MCF_ADC_ADSDIS_DS0 (0x0001) |
---|
| 2718 | #define MCF_ADC_ADSDIS_DS1 (0x0002) |
---|
| 2719 | #define MCF_ADC_ADSDIS_DS2 (0x0004) |
---|
| 2720 | #define MCF_ADC_ADSDIS_DS3 (0x0008) |
---|
| 2721 | #define MCF_ADC_ADSDIS_DS4 (0x0010) |
---|
| 2722 | #define MCF_ADC_ADSDIS_DS5 (0x0020) |
---|
| 2723 | #define MCF_ADC_ADSDIS_DS6 (0x0040) |
---|
| 2724 | #define MCF_ADC_ADSDIS_DS7 (0x0080) |
---|
| 2725 | |
---|
| 2726 | /* Bit definitions and macros for MCF_ADC_ADSTAT */ |
---|
| 2727 | #define MCF_ADC_ADSTAT_RDY0 (0x0001) |
---|
| 2728 | #define MCF_ADC_ADSTAT_RDY1 (0x0002) |
---|
| 2729 | #define MCF_ADC_ADSTAT_RDY2 (0x0004) |
---|
| 2730 | #define MCF_ADC_ADSTAT_RDY3 (0x0008) |
---|
| 2731 | #define MCF_ADC_ADSTAT_RDY4 (0x0010) |
---|
| 2732 | #define MCF_ADC_ADSTAT_RDY5 (0x0020) |
---|
| 2733 | #define MCF_ADC_ADSTAT_RDY6 (0x0040) |
---|
| 2734 | #define MCF_ADC_ADSTAT_RDY7 (0x0080) |
---|
| 2735 | #define MCF_ADC_ADSTAT_HLMT (0x0100) |
---|
| 2736 | #define MCF_ADC_ADSTAT_LLMTI (0x0200) |
---|
| 2737 | #define MCF_ADC_ADSTAT_ZCI (0x0400) |
---|
| 2738 | #define MCF_ADC_ADSTAT_EOSI (0x0800) |
---|
| 2739 | #define MCF_ADC_ADSTAT_CIP (0x8000) |
---|
| 2740 | |
---|
| 2741 | /* Bit definitions and macros for MCF_ADC_ADLSTAT */ |
---|
| 2742 | #define MCF_ADC_ADLSTAT_LLS0 (0x0001) |
---|
| 2743 | #define MCF_ADC_ADLSTAT_LLS1 (0x0002) |
---|
| 2744 | #define MCF_ADC_ADLSTAT_LLS2 (0x0004) |
---|
| 2745 | #define MCF_ADC_ADLSTAT_LLS3 (0x0008) |
---|
| 2746 | #define MCF_ADC_ADLSTAT_LLS4 (0x0010) |
---|
| 2747 | #define MCF_ADC_ADLSTAT_LLS5 (0x0020) |
---|
| 2748 | #define MCF_ADC_ADLSTAT_LLS6 (0x0040) |
---|
| 2749 | #define MCF_ADC_ADLSTAT_LLS7 (0x0080) |
---|
| 2750 | #define MCF_ADC_ADLSTAT_HLS0 (0x0100) |
---|
| 2751 | #define MCF_ADC_ADLSTAT_HLS1 (0x0200) |
---|
| 2752 | #define MCF_ADC_ADLSTAT_HLS2 (0x0400) |
---|
| 2753 | #define MCF_ADC_ADLSTAT_HLS3 (0x0800) |
---|
| 2754 | #define MCF_ADC_ADLSTAT_HLS4 (0x1000) |
---|
| 2755 | #define MCF_ADC_ADLSTAT_HLS5 (0x2000) |
---|
| 2756 | #define MCF_ADC_ADLSTAT_HLS6 (0x4000) |
---|
| 2757 | #define MCF_ADC_ADLSTAT_HLS7 (0x8000) |
---|
| 2758 | |
---|
| 2759 | /* Bit definitions and macros for MCF_ADC_ADZCSTAT */ |
---|
| 2760 | #define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) |
---|
| 2761 | #define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) |
---|
| 2762 | #define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) |
---|
| 2763 | #define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) |
---|
| 2764 | #define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) |
---|
| 2765 | #define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) |
---|
| 2766 | #define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) |
---|
| 2767 | #define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) |
---|
| 2768 | |
---|
| 2769 | /* Bit definitions and macros for MCF_ADC_ADRSLT */ |
---|
| 2770 | #define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) |
---|
| 2771 | #define MCF_ADC_ADRSLT_SEXT (0x8000) |
---|
| 2772 | |
---|
| 2773 | /* Bit definitions and macros for MCF_ADC_ADLLMT */ |
---|
| 2774 | #define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) |
---|
| 2775 | |
---|
| 2776 | /* Bit definitions and macros for MCF_ADC_ADHLMT */ |
---|
| 2777 | #define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) |
---|
| 2778 | |
---|
| 2779 | /* Bit definitions and macros for MCF_ADC_ADOFS */ |
---|
| 2780 | #define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) |
---|
| 2781 | |
---|
| 2782 | /* Bit definitions and macros for MCF_ADC_POWER */ |
---|
| 2783 | #define MCF_ADC_POWER_PD0 (0x0001) |
---|
| 2784 | #define MCF_ADC_POWER_PD1 (0x0002) |
---|
| 2785 | #define MCF_ADC_POWER_PD2 (0x0004) |
---|
| 2786 | #define MCF_ADC_POWER_APD (0x0008) |
---|
| 2787 | #define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) |
---|
| 2788 | #define MCF_ADC_POWER_PSTS0 (0x0400) |
---|
| 2789 | #define MCF_ADC_POWER_PSTS1 (0x0800) |
---|
| 2790 | #define MCF_ADC_POWER_PSTS2 (0x1000) |
---|
| 2791 | #define MCF_ADC_POWER_ASTBY (0x8000) |
---|
| 2792 | |
---|
| 2793 | /* Bit definitions and macros for MCF_ADC_CAL */ |
---|
| 2794 | #define MCF_ADC_CAL_CAL0 (0x0001) |
---|
| 2795 | #define MCF_ADC_CAL_CRS0 (0x0002) |
---|
| 2796 | #define MCF_ADC_CAL_CAL1 (0x0004) |
---|
| 2797 | #define MCF_ADC_CAL_CRS1 (0x0008) |
---|
| 2798 | |
---|
| 2799 | /********************************************************************* |
---|
| 2800 | * |
---|
| 2801 | * General Purpose Timer (GPT) |
---|
| 2802 | * |
---|
| 2803 | *********************************************************************/ |
---|
| 2804 | |
---|
| 2805 | /* Register read/write macros */ |
---|
| 2806 | #define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) |
---|
| 2807 | #define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) |
---|
| 2808 | #define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) |
---|
| 2809 | #define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) |
---|
| 2810 | #define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) |
---|
| 2811 | #define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) |
---|
| 2812 | #define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) |
---|
| 2813 | #define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) |
---|
| 2814 | #define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) |
---|
| 2815 | #define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) |
---|
| 2816 | #define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) |
---|
| 2817 | #define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) |
---|
| 2818 | #define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) |
---|
| 2819 | #define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) |
---|
| 2820 | #define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) |
---|
| 2821 | #define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) |
---|
| 2822 | #define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) |
---|
| 2823 | #define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) |
---|
| 2824 | #define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) |
---|
| 2825 | #define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) |
---|
| 2826 | #define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) |
---|
| 2827 | #define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) |
---|
| 2828 | #define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) |
---|
| 2829 | |
---|
| 2830 | /* Bit definitions and macros for MCF_GPT_GPTIOS */ |
---|
| 2831 | #define MCF_GPT_GPTIOS_IOS0 (0x01) |
---|
| 2832 | #define MCF_GPT_GPTIOS_IOS1 (0x02) |
---|
| 2833 | #define MCF_GPT_GPTIOS_IOS2 (0x04) |
---|
| 2834 | #define MCF_GPT_GPTIOS_IOS3 (0x08) |
---|
| 2835 | |
---|
| 2836 | /* Bit definitions and macros for MCF_GPT_GPTCFORC */ |
---|
| 2837 | #define MCF_GPT_GPTCFORC_FOC0 (0x01) |
---|
| 2838 | #define MCF_GPT_GPTCFORC_FOC1 (0x02) |
---|
| 2839 | #define MCF_GPT_GPTCFORC_FOC2 (0x04) |
---|
| 2840 | #define MCF_GPT_GPTCFORC_FOC3 (0x08) |
---|
| 2841 | |
---|
| 2842 | /* Bit definitions and macros for MCF_GPT_GPTOC3D */ |
---|
| 2843 | #define MCF_GPT_GPTOC3D_OC3D0 (0x01) |
---|
| 2844 | #define MCF_GPT_GPTOC3D_OC3D1 (0x02) |
---|
| 2845 | #define MCF_GPT_GPTOC3D_OC3D2 (0x04) |
---|
| 2846 | #define MCF_GPT_GPTOC3D_OC3D3 (0x08) |
---|
| 2847 | |
---|
| 2848 | /* Bit definitions and macros for MCF_GPT_GPTSCR1 */ |
---|
| 2849 | #define MCF_GPT_GPTSCR1_TFFCA (0x10) |
---|
| 2850 | #define MCF_GPT_GPTSCR1_GPTEN (0x80) |
---|
| 2851 | |
---|
| 2852 | /* Bit definitions and macros for MCF_GPT_GPTTOV */ |
---|
| 2853 | #define MCF_GPT_GPTTOV_TOV0 (0x01) |
---|
| 2854 | #define MCF_GPT_GPTTOV_TOV1 (0x02) |
---|
| 2855 | #define MCF_GPT_GPTTOV_TOV2 (0x04) |
---|
| 2856 | #define MCF_GPT_GPTTOV_TOV3 (0x08) |
---|
| 2857 | |
---|
| 2858 | /* Bit definitions and macros for MCF_GPT_GPTCTL1 */ |
---|
| 2859 | #define MCF_GPT_GPTCTL1_OL0 (0x01) |
---|
| 2860 | #define MCF_GPT_GPTCTL1_OM0 (0x02) |
---|
| 2861 | #define MCF_GPT_GPTCTL1_OL1 (0x04) |
---|
| 2862 | #define MCF_GPT_GPTCTL1_OM1 (0x08) |
---|
| 2863 | #define MCF_GPT_GPTCTL1_OL2 (0x10) |
---|
| 2864 | #define MCF_GPT_GPTCTL1_OM2 (0x20) |
---|
| 2865 | #define MCF_GPT_GPTCTL1_OL3 (0x40) |
---|
| 2866 | #define MCF_GPT_GPTCTL1_OM3 (0x80) |
---|
| 2867 | #define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) |
---|
| 2868 | #define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) |
---|
| 2869 | #define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) |
---|
| 2870 | #define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) |
---|
| 2871 | #define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) |
---|
| 2872 | #define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) |
---|
| 2873 | #define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) |
---|
| 2874 | #define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) |
---|
| 2875 | #define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) |
---|
| 2876 | #define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) |
---|
| 2877 | #define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) |
---|
| 2878 | #define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) |
---|
| 2879 | #define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) |
---|
| 2880 | #define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) |
---|
| 2881 | #define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) |
---|
| 2882 | #define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) |
---|
| 2883 | |
---|
| 2884 | /* Bit definitions and macros for MCF_GPT_GPTCTL2 */ |
---|
| 2885 | #define MCF_GPT_GPTCTL2_EDG0A (0x01) |
---|
| 2886 | #define MCF_GPT_GPTCTL2_EDG0B (0x02) |
---|
| 2887 | #define MCF_GPT_GPTCTL2_EDG1A (0x04) |
---|
| 2888 | #define MCF_GPT_GPTCTL2_EDG1B (0x08) |
---|
| 2889 | #define MCF_GPT_GPTCTL2_EDG2A (0x10) |
---|
| 2890 | #define MCF_GPT_GPTCTL2_EDG2B (0x20) |
---|
| 2891 | #define MCF_GPT_GPTCTL2_EDG3A (0x40) |
---|
| 2892 | #define MCF_GPT_GPTCTL2_EDG3B (0x80) |
---|
| 2893 | #define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) |
---|
| 2894 | #define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) |
---|
| 2895 | #define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) |
---|
| 2896 | #define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) |
---|
| 2897 | #define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) |
---|
| 2898 | #define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) |
---|
| 2899 | #define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) |
---|
| 2900 | #define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) |
---|
| 2901 | #define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) |
---|
| 2902 | #define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) |
---|
| 2903 | #define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) |
---|
| 2904 | #define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) |
---|
| 2905 | #define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) |
---|
| 2906 | #define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) |
---|
| 2907 | #define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) |
---|
| 2908 | #define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) |
---|
| 2909 | |
---|
| 2910 | /* Bit definitions and macros for MCF_GPT_GPTIE */ |
---|
| 2911 | #define MCF_GPT_GPTIE_CI0 (0x01) |
---|
| 2912 | #define MCF_GPT_GPTIE_CI1 (0x02) |
---|
| 2913 | #define MCF_GPT_GPTIE_CI2 (0x04) |
---|
| 2914 | #define MCF_GPT_GPTIE_CI3 (0x08) |
---|
| 2915 | |
---|
| 2916 | /* Bit definitions and macros for MCF_GPT_GPTSCR2 */ |
---|
| 2917 | #define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) |
---|
| 2918 | #define MCF_GPT_GPTSCR2_TCRE (0x08) |
---|
| 2919 | #define MCF_GPT_GPTSCR2_RDPT (0x10) |
---|
| 2920 | #define MCF_GPT_GPTSCR2_PUPT (0x20) |
---|
| 2921 | #define MCF_GPT_GPTSCR2_TOI (0x80) |
---|
| 2922 | #define MCF_GPT_GPTSCR2_PR_1 ((0x00)) |
---|
| 2923 | #define MCF_GPT_GPTSCR2_PR_2 ((0x01)) |
---|
| 2924 | #define MCF_GPT_GPTSCR2_PR_4 ((0x02)) |
---|
| 2925 | #define MCF_GPT_GPTSCR2_PR_8 ((0x03)) |
---|
| 2926 | #define MCF_GPT_GPTSCR2_PR_16 ((0x04)) |
---|
| 2927 | #define MCF_GPT_GPTSCR2_PR_32 ((0x05)) |
---|
| 2928 | #define MCF_GPT_GPTSCR2_PR_64 ((0x06)) |
---|
| 2929 | #define MCF_GPT_GPTSCR2_PR_128 ((0x07)) |
---|
| 2930 | |
---|
| 2931 | /* Bit definitions and macros for MCF_GPT_GPTFLG1 */ |
---|
| 2932 | #define MCF_GPT_GPTFLG1_CF0 (0x01) |
---|
| 2933 | #define MCF_GPT_GPTFLG1_CF1 (0x02) |
---|
| 2934 | #define MCF_GPT_GPTFLG1_CF2 (0x04) |
---|
| 2935 | #define MCF_GPT_GPTFLG1_CF3 (0x08) |
---|
| 2936 | |
---|
| 2937 | /* Bit definitions and macros for MCF_GPT_GPTFLG2 */ |
---|
| 2938 | #define MCF_GPT_GPTFLG2_CF0 (0x01) |
---|
| 2939 | #define MCF_GPT_GPTFLG2_CF1 (0x02) |
---|
| 2940 | #define MCF_GPT_GPTFLG2_CF2 (0x04) |
---|
| 2941 | #define MCF_GPT_GPTFLG2_CF3 (0x08) |
---|
| 2942 | #define MCF_GPT_GPTFLG2_TOF (0x80) |
---|
| 2943 | |
---|
| 2944 | /* Bit definitions and macros for MCF_GPT_GPTC */ |
---|
| 2945 | #define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) |
---|
| 2946 | |
---|
| 2947 | /* Bit definitions and macros for MCF_GPT_GPTPACTL */ |
---|
| 2948 | #define MCF_GPT_GPTPACTL_PAI (0x01) |
---|
| 2949 | #define MCF_GPT_GPTPACTL_PAOVI (0x02) |
---|
| 2950 | #define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) |
---|
| 2951 | #define MCF_GPT_GPTPACTL_PEDGE (0x10) |
---|
| 2952 | #define MCF_GPT_GPTPACTL_PAMOD (0x20) |
---|
| 2953 | #define MCF_GPT_GPTPACTL_PAE (0x40) |
---|
| 2954 | #define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) |
---|
| 2955 | #define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) |
---|
| 2956 | #define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) |
---|
| 2957 | #define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) |
---|
| 2958 | |
---|
| 2959 | /* Bit definitions and macros for MCF_GPT_GPTPAFLG */ |
---|
| 2960 | #define MCF_GPT_GPTPAFLG_PAIF (0x01) |
---|
| 2961 | #define MCF_GPT_GPTPAFLG_PAOVF (0x02) |
---|
| 2962 | |
---|
| 2963 | /* Bit definitions and macros for MCF_GPT_GPTPACNT */ |
---|
| 2964 | #define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) |
---|
| 2965 | |
---|
| 2966 | /* Bit definitions and macros for MCF_GPT_GPTPORT */ |
---|
| 2967 | #define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) |
---|
| 2968 | |
---|
| 2969 | /* Bit definitions and macros for MCF_GPT_GPTDDR */ |
---|
| 2970 | #define MCF_GPT_GPTDDR_DDRT0 (0x01) |
---|
| 2971 | #define MCF_GPT_GPTDDR_DDRT1 (0x02) |
---|
| 2972 | #define MCF_GPT_GPTDDR_DDRT2 (0x04) |
---|
| 2973 | #define MCF_GPT_GPTDDR_DDRT3 (0x08) |
---|
| 2974 | |
---|
| 2975 | /********************************************************************* |
---|
| 2976 | * |
---|
| 2977 | * Pulse Width Modulation (PWM) |
---|
| 2978 | * |
---|
| 2979 | *********************************************************************/ |
---|
| 2980 | |
---|
| 2981 | /* Register read/write macros */ |
---|
| 2982 | #define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) |
---|
| 2983 | #define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) |
---|
| 2984 | #define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) |
---|
| 2985 | #define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) |
---|
| 2986 | #define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) |
---|
| 2987 | #define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) |
---|
| 2988 | #define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) |
---|
| 2989 | #define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) |
---|
| 2990 | #define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) |
---|
| 2991 | #define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) |
---|
| 2992 | #define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) |
---|
| 2993 | #define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) |
---|
| 2994 | #define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) |
---|
| 2995 | #define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) |
---|
| 2996 | #define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) |
---|
| 2997 | #define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) |
---|
| 2998 | #define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) |
---|
| 2999 | #define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) |
---|
| 3000 | #define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) |
---|
| 3001 | #define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) |
---|
| 3002 | #define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) |
---|
| 3003 | #define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) |
---|
| 3004 | #define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) |
---|
| 3005 | #define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) |
---|
| 3006 | #define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) |
---|
| 3007 | #define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) |
---|
| 3008 | #define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) |
---|
| 3009 | #define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) |
---|
| 3010 | #define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) |
---|
| 3011 | #define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) |
---|
| 3012 | #define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) |
---|
| 3013 | #define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) |
---|
| 3014 | #define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) |
---|
| 3015 | #define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) |
---|
| 3016 | #define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) |
---|
| 3017 | #define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) |
---|
| 3018 | |
---|
| 3019 | /* Bit definitions and macros for MCF_PWM_PWME */ |
---|
| 3020 | #define MCF_PWM_PWME_PWME0 (0x01) |
---|
| 3021 | #define MCF_PWM_PWME_PWME1 (0x02) |
---|
| 3022 | #define MCF_PWM_PWME_PWME2 (0x04) |
---|
| 3023 | #define MCF_PWM_PWME_PWME3 (0x08) |
---|
| 3024 | |
---|
| 3025 | /* Bit definitions and macros for MCF_PWM_PWMPOL */ |
---|
| 3026 | #define MCF_PWM_PWMPOL_PPOL0 (0x01) |
---|
| 3027 | #define MCF_PWM_PWMPOL_PPOL1 (0x02) |
---|
| 3028 | #define MCF_PWM_PWMPOL_PPOL2 (0x04) |
---|
| 3029 | #define MCF_PWM_PWMPOL_PPOL3 (0x08) |
---|
| 3030 | |
---|
| 3031 | /* Bit definitions and macros for MCF_PWM_PWMCLK */ |
---|
| 3032 | #define MCF_PWM_PWMCLK_PCLK0 (0x01) |
---|
| 3033 | #define MCF_PWM_PWMCLK_PCLK1 (0x02) |
---|
| 3034 | #define MCF_PWM_PWMCLK_PCLK2 (0x04) |
---|
| 3035 | #define MCF_PWM_PWMCLK_PCLK3 (0x08) |
---|
| 3036 | |
---|
| 3037 | /* Bit definitions and macros for MCF_PWM_PWMPRCLK */ |
---|
| 3038 | #define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) |
---|
| 3039 | #define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) |
---|
| 3040 | |
---|
| 3041 | /* Bit definitions and macros for MCF_PWM_PWMCAE */ |
---|
| 3042 | #define MCF_PWM_PWMCAE_CAE0 (0x01) |
---|
| 3043 | #define MCF_PWM_PWMCAE_CAE1 (0x02) |
---|
| 3044 | #define MCF_PWM_PWMCAE_CAE2 (0x04) |
---|
| 3045 | #define MCF_PWM_PWMCAE_CAE3 (0x08) |
---|
| 3046 | |
---|
| 3047 | /* Bit definitions and macros for MCF_PWM_PWMCTL */ |
---|
| 3048 | #define MCF_PWM_PWMCTL_PFRZ (0x04) |
---|
| 3049 | #define MCF_PWM_PWMCTL_PSWAI (0x08) |
---|
| 3050 | #define MCF_PWM_PWMCTL_CON01 (0x10) |
---|
| 3051 | #define MCF_PWM_PWMCTL_CON23 (0x20) |
---|
| 3052 | |
---|
| 3053 | /* Bit definitions and macros for MCF_PWM_PWMSCLA */ |
---|
| 3054 | #define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) |
---|
| 3055 | |
---|
| 3056 | /* Bit definitions and macros for MCF_PWM_PWMSCLB */ |
---|
| 3057 | #define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) |
---|
| 3058 | |
---|
| 3059 | /* Bit definitions and macros for MCF_PWM_PWMCNT */ |
---|
| 3060 | #define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) |
---|
| 3061 | |
---|
| 3062 | /* Bit definitions and macros for MCF_PWM_PWMPER */ |
---|
| 3063 | #define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) |
---|
| 3064 | |
---|
| 3065 | /* Bit definitions and macros for MCF_PWM_PWMDTY */ |
---|
| 3066 | #define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) |
---|
| 3067 | |
---|
| 3068 | /* Bit definitions and macros for MCF_PWM_PWMSDN */ |
---|
| 3069 | #define MCF_PWM_PWMSDN_SDNEN (0x01) |
---|
| 3070 | #define MCF_PWM_PWMSDN_PWM7IL (0x02) |
---|
| 3071 | #define MCF_PWM_PWMSDN_PWM7IN (0x04) |
---|
| 3072 | #define MCF_PWM_PWMSDN_LVL (0x10) |
---|
| 3073 | #define MCF_PWM_PWMSDN_RESTART (0x20) |
---|
| 3074 | #define MCF_PWM_PWMSDN_IE (0x40) |
---|
| 3075 | #define MCF_PWM_PWMSDN_IF (0x80) |
---|
| 3076 | |
---|
| 3077 | /********************************************************************* |
---|
| 3078 | * |
---|
| 3079 | * FlexCAN Module (CAN) |
---|
| 3080 | * |
---|
| 3081 | *********************************************************************/ |
---|
| 3082 | |
---|
| 3083 | /* Register read/write macros */ |
---|
| 3084 | #define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) |
---|
| 3085 | #define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) |
---|
| 3086 | #define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) |
---|
| 3087 | #define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) |
---|
| 3088 | #define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) |
---|
| 3089 | #define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) |
---|
| 3090 | #define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) |
---|
| 3091 | #define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) |
---|
| 3092 | #define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) |
---|
| 3093 | #define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) |
---|
| 3094 | |
---|
| 3095 | /* Bit definitions and macros for MCF_CAN_CANMCR */ |
---|
| 3096 | #define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) |
---|
| 3097 | #define MCF_CAN_CANMCR_SUPV (0x00800000) |
---|
| 3098 | #define MCF_CAN_CANMCR_FRZACK (0x01000000) |
---|
| 3099 | #define MCF_CAN_CANMCR_SOFTRST (0x02000000) |
---|
| 3100 | #define MCF_CAN_CANMCR_HALT (0x10000000) |
---|
| 3101 | #define MCF_CAN_CANMCR_FRZ (0x40000000) |
---|
| 3102 | #define MCF_CAN_CANMCR_MDIS (0x80000000) |
---|
| 3103 | |
---|
| 3104 | /* Bit definitions and macros for MCF_CAN_CANCTRL */ |
---|
| 3105 | #define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) |
---|
| 3106 | #define MCF_CAN_CANCTRL_LOM (0x00000008) |
---|
| 3107 | #define MCF_CAN_CANCTRL_LBUF (0x00000010) |
---|
| 3108 | #define MCF_CAN_CANCTRL_TSYNC (0x00000020) |
---|
| 3109 | #define MCF_CAN_CANCTRL_BOFFREC (0x00000040) |
---|
| 3110 | #define MCF_CAN_CANCTRL_SAMP (0x00000080) |
---|
| 3111 | #define MCF_CAN_CANCTRL_LPB (0x00001000) |
---|
| 3112 | #define MCF_CAN_CANCTRL_CLKSRC (0x00002000) |
---|
| 3113 | #define MCF_CAN_CANCTRL_ERRMSK (0x00004000) |
---|
| 3114 | #define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) |
---|
| 3115 | #define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) |
---|
| 3116 | #define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) |
---|
| 3117 | #define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) |
---|
| 3118 | #define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) |
---|
| 3119 | |
---|
| 3120 | /* Bit definitions and macros for MCF_CAN_TIMER */ |
---|
| 3121 | #define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) |
---|
| 3122 | |
---|
| 3123 | /* Bit definitions and macros for MCF_CAN_RXGMASK */ |
---|
| 3124 | #define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) |
---|
| 3125 | |
---|
| 3126 | /* Bit definitions and macros for MCF_CAN_RX14MASK */ |
---|
| 3127 | #define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) |
---|
| 3128 | |
---|
| 3129 | /* Bit definitions and macros for MCF_CAN_RX15MASK */ |
---|
| 3130 | #define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) |
---|
| 3131 | |
---|
| 3132 | /* Bit definitions and macros for MCF_CAN_ERRCNT */ |
---|
| 3133 | #define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) |
---|
| 3134 | #define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) |
---|
| 3135 | |
---|
| 3136 | /* Bit definitions and macros for MCF_CAN_ERRSTAT */ |
---|
| 3137 | #define MCF_CAN_ERRSTAT_WAKINT (0x00000001) |
---|
| 3138 | #define MCF_CAN_ERRSTAT_ERRINT (0x00000002) |
---|
| 3139 | #define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) |
---|
| 3140 | #define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) |
---|
| 3141 | #define MCF_CAN_ERRSTAT_TXRX (0x00000040) |
---|
| 3142 | #define MCF_CAN_ERRSTAT_IDLE (0x00000080) |
---|
| 3143 | #define MCF_CAN_ERRSTAT_RXWRN (0x00000100) |
---|
| 3144 | #define MCF_CAN_ERRSTAT_TXWRN (0x00000200) |
---|
| 3145 | #define MCF_CAN_ERRSTAT_STFERR (0x00000400) |
---|
| 3146 | #define MCF_CAN_ERRSTAT_FRMERR (0x00000800) |
---|
| 3147 | #define MCF_CAN_ERRSTAT_CRCERR (0x00001000) |
---|
| 3148 | #define MCF_CAN_ERRSTAT_ACKERR (0x00002000) |
---|
| 3149 | #define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) |
---|
| 3150 | #define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) |
---|
| 3151 | #define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) |
---|
| 3152 | #define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) |
---|
| 3153 | |
---|
| 3154 | /* Bit definitions and macros for MCF_CAN_IMASK */ |
---|
| 3155 | #define MCF_CAN_IMASK_BUF(x) (1<<x) |
---|
| 3156 | |
---|
| 3157 | /* Bit definitions and macros for MCF_CAN_IFLAG */ |
---|
| 3158 | #define MCF_CAN_IFLAG_BUF(x) (1<<x) |
---|
| 3159 | |
---|
| 3160 | /********************************************************************* |
---|
| 3161 | * |
---|
| 3162 | * ColdFire Flash Module (CFM) |
---|
| 3163 | * |
---|
| 3164 | *********************************************************************/ |
---|
| 3165 | |
---|
| 3166 | /* Register read/write macros */ |
---|
| 3167 | #define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000])) |
---|
| 3168 | #define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002])) |
---|
| 3169 | #define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008])) |
---|
| 3170 | #define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010])) |
---|
| 3171 | #define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014])) |
---|
| 3172 | #define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018])) |
---|
| 3173 | #define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020])) |
---|
| 3174 | #define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024])) |
---|
| 3175 | |
---|
| 3176 | /* Bit definitions and macros for MCF_CFM_CFMMCR */ |
---|
| 3177 | #define MCF_CFM_CFMMCR_KEYACC (0x0020) |
---|
| 3178 | #define MCF_CFM_CFMMCR_CCIE (0x0040) |
---|
| 3179 | #define MCF_CFM_CFMMCR_CBEIE (0x0080) |
---|
| 3180 | #define MCF_CFM_CFMMCR_AEIE (0x0100) |
---|
| 3181 | #define MCF_CFM_CFMMCR_PVIE (0x0200) |
---|
| 3182 | #define MCF_CFM_CFMMCR_LOCK (0x0400) |
---|
| 3183 | |
---|
| 3184 | /* Bit definitions and macros for MCF_CFM_CFMCLKD */ |
---|
| 3185 | #define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0) |
---|
| 3186 | #define MCF_CFM_CFMCLKD_PRDIV8 (0x40) |
---|
| 3187 | #define MCF_CFM_CFMCLKD_DIVLD (0x80) |
---|
| 3188 | |
---|
| 3189 | /* Bit definitions and macros for MCF_CFM_CFMSEC */ |
---|
| 3190 | #define MCF_CFM_CFMSEC_SEC(x) (((x)&0x0000FFFF)<<0) |
---|
| 3191 | #define MCF_CFM_CFMSEC_SECSTAT (0x40000000) |
---|
| 3192 | #define MCF_CFM_CFMSEC_KEYEN (0x80000000) |
---|
| 3193 | |
---|
| 3194 | /* Bit definitions and macros for MCF_CFM_CFMUSTAT */ |
---|
| 3195 | #define MCF_CFM_CFMUSTAT_BLANK (0x04) |
---|
| 3196 | #define MCF_CFM_CFMUSTAT_ACCERR (0x10) |
---|
| 3197 | #define MCF_CFM_CFMUSTAT_PVIOL (0x20) |
---|
| 3198 | #define MCF_CFM_CFMUSTAT_CCIF (0x40) |
---|
| 3199 | #define MCF_CFM_CFMUSTAT_CBEIF (0x80) |
---|
| 3200 | |
---|
| 3201 | /* Bit definitions and macros for MCF_CFM_CFMCMD */ |
---|
| 3202 | #define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0) |
---|
| 3203 | #define MCF_CFM_CFMCMD_RDARY1 (0x05) |
---|
| 3204 | #define MCF_CFM_CFMCMD_PGM (0x20) |
---|
| 3205 | #define MCF_CFM_CFMCMD_PGERS (0x40) |
---|
| 3206 | #define MCF_CFM_CFMCMD_MASERS (0x41) |
---|
| 3207 | #define MCF_CFM_CFMCMD_PGERSVER (0x06) |
---|
| 3208 | |
---|
| 3209 | /********************************************************************* |
---|
| 3210 | * |
---|
| 3211 | * Interrupt Controller (INTC_IACK) |
---|
| 3212 | * |
---|
| 3213 | *********************************************************************/ |
---|
| 3214 | |
---|
| 3215 | /* Register read/write macros */ |
---|
| 3216 | #define MCF_INTC_IACK_GSWIACK (*(vuint8 *)(&__IPSBAR[0x000FE0])) |
---|
| 3217 | #define MCF_INTC_IACK_GL1IACK (*(vuint8 *)(&__IPSBAR[0x000FE4])) |
---|
| 3218 | #define MCF_INTC_IACK_GL2IACK (*(vuint8 *)(&__IPSBAR[0x000FE8])) |
---|
| 3219 | #define MCF_INTC_IACK_GL3IACK (*(vuint8 *)(&__IPSBAR[0x000FEC])) |
---|
| 3220 | #define MCF_INTC_IACK_GL4IACK (*(vuint8 *)(&__IPSBAR[0x000FF0])) |
---|
| 3221 | #define MCF_INTC_IACK_GL5IACK (*(vuint8 *)(&__IPSBAR[0x000FF4])) |
---|
| 3222 | #define MCF_INTC_IACK_GL6IACK (*(vuint8 *)(&__IPSBAR[0x000FF8])) |
---|
| 3223 | #define MCF_INTC_IACK_GL7IACK (*(vuint8 *)(&__IPSBAR[0x000FFC])) |
---|
| 3224 | #define MCF_INTC_IACK_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)])) |
---|
| 3225 | |
---|
| 3226 | /* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */ |
---|
| 3227 | #define MCF_INTC_IACK_GSWIACK_VECTOR(x) (((x)&0xFF)<<0) |
---|
| 3228 | |
---|
| 3229 | /* Bit definitions and macros for MCF_INTC_IACK_GLIACK */ |
---|
| 3230 | #define MCF_INTC_IACK_GLIACK_VECTOR(x) (((x)&0xFF)<<0) |
---|
| 3231 | |
---|
| 3232 | /********************************************************************* |
---|
| 3233 | * |
---|
| 3234 | * Fast Ethernet Controller (FEC) |
---|
| 3235 | * |
---|
| 3236 | *********************************************************************/ |
---|
| 3237 | |
---|
| 3238 | /* Register read/write macros */ |
---|
| 3239 | #define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x001004])) |
---|
| 3240 | #define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x001008])) |
---|
| 3241 | #define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x001010])) |
---|
| 3242 | #define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x001014])) |
---|
| 3243 | #define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x001024])) |
---|
| 3244 | #define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x001040])) |
---|
| 3245 | #define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x001044])) |
---|
| 3246 | #define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x001064])) |
---|
| 3247 | #define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x001084])) |
---|
| 3248 | #define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x0010C4])) |
---|
| 3249 | #define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x0010E4])) |
---|
| 3250 | #define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x0010E8])) |
---|
| 3251 | #define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x0010EC])) |
---|
| 3252 | #define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x001118])) |
---|
| 3253 | #define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x00111C])) |
---|
| 3254 | #define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x001120])) |
---|
| 3255 | #define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x001124])) |
---|
| 3256 | #define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x001144])) |
---|
| 3257 | #define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x00114C])) |
---|
| 3258 | #define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x001150])) |
---|
| 3259 | #define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x001180])) |
---|
| 3260 | #define MCF_FEC_ETDSR (*(vuint32*)(&__IPSBAR[0x001184])) |
---|
| 3261 | #define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x001188])) |
---|
| 3262 | #define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x001200])) |
---|
| 3263 | #define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x001204])) |
---|
| 3264 | #define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x001208])) |
---|
| 3265 | #define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x00120C])) |
---|
| 3266 | #define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001210])) |
---|
| 3267 | #define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001214])) |
---|
| 3268 | #define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001218])) |
---|
| 3269 | #define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x00121C])) |
---|
| 3270 | #define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x001220])) |
---|
| 3271 | #define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x001224])) |
---|
| 3272 | #define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x001228])) |
---|
| 3273 | #define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x00122C])) |
---|
| 3274 | #define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x001230])) |
---|
| 3275 | #define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x001234])) |
---|
| 3276 | #define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x001238])) |
---|
| 3277 | #define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x00123C])) |
---|
| 3278 | #define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x001240])) |
---|
| 3279 | #define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x001244])) |
---|
| 3280 | #define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x001248])) |
---|
| 3281 | #define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x00124C])) |
---|
| 3282 | #define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x001250])) |
---|
| 3283 | #define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x001254])) |
---|
| 3284 | #define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x001258])) |
---|
| 3285 | #define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x00125C])) |
---|
| 3286 | #define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x001260])) |
---|
| 3287 | #define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x001264])) |
---|
| 3288 | #define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x001268])) |
---|
| 3289 | #define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x00126C])) |
---|
| 3290 | #define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x001270])) |
---|
| 3291 | #define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x001274])) |
---|
| 3292 | #define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x001284])) |
---|
| 3293 | #define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x001288])) |
---|
| 3294 | #define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x00128C])) |
---|
| 3295 | #define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x001290])) |
---|
| 3296 | #define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x001294])) |
---|
| 3297 | #define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x001298])) |
---|
| 3298 | #define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x00129C])) |
---|
| 3299 | #define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x0012A0])) |
---|
| 3300 | #define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x0012A4])) |
---|
| 3301 | #define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x0012A8])) |
---|
| 3302 | #define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x0012AC])) |
---|
| 3303 | #define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x0012B0])) |
---|
| 3304 | #define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x0012B4])) |
---|
| 3305 | #define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(&__IPSBAR[0x0012B8])) |
---|
| 3306 | #define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x0012C0])) |
---|
| 3307 | #define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(&__IPSBAR[0x0012BC])) |
---|
| 3308 | #define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x0012C4])) |
---|
| 3309 | #define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x0012C8])) |
---|
| 3310 | #define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x0012CC])) |
---|
| 3311 | #define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x0012D0])) |
---|
| 3312 | #define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x0012D4])) |
---|
| 3313 | #define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x0012D8])) |
---|
| 3314 | #define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x0012DC])) |
---|
| 3315 | #define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x0012E0])) |
---|
| 3316 | |
---|
| 3317 | /* Bit definitions and macros for MCF_FEC_EIR */ |
---|
| 3318 | #define MCF_FEC_EIR_UN (0x00080000) |
---|
| 3319 | #define MCF_FEC_EIR_RL (0x00100000) |
---|
| 3320 | #define MCF_FEC_EIR_LC (0x00200000) |
---|
| 3321 | #define MCF_FEC_EIR_EBERR (0x00400000) |
---|
| 3322 | #define MCF_FEC_EIR_MII (0x00800000) |
---|
| 3323 | #define MCF_FEC_EIR_RXB (0x01000000) |
---|
| 3324 | #define MCF_FEC_EIR_RXF (0x02000000) |
---|
| 3325 | #define MCF_FEC_EIR_TXB (0x04000000) |
---|
| 3326 | #define MCF_FEC_EIR_TXF (0x08000000) |
---|
| 3327 | #define MCF_FEC_EIR_GRA (0x10000000) |
---|
| 3328 | #define MCF_FEC_EIR_BABT (0x20000000) |
---|
| 3329 | #define MCF_FEC_EIR_BABR (0x40000000) |
---|
| 3330 | #define MCF_FEC_EIR_HBERR (0x80000000) |
---|
| 3331 | #define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) |
---|
| 3332 | |
---|
| 3333 | /* Bit definitions and macros for MCF_FEC_EIMR */ |
---|
| 3334 | #define MCF_FEC_EIMR_UN (0x00080000) |
---|
| 3335 | #define MCF_FEC_EIMR_RL (0x00100000) |
---|
| 3336 | #define MCF_FEC_EIMR_LC (0x00200000) |
---|
| 3337 | #define MCF_FEC_EIMR_EBERR (0x00400000) |
---|
| 3338 | #define MCF_FEC_EIMR_MII (0x00800000) |
---|
| 3339 | #define MCF_FEC_EIMR_RXB (0x01000000) |
---|
| 3340 | #define MCF_FEC_EIMR_RXF (0x02000000) |
---|
| 3341 | #define MCF_FEC_EIMR_TXB (0x04000000) |
---|
| 3342 | #define MCF_FEC_EIMR_TXF (0x08000000) |
---|
| 3343 | #define MCF_FEC_EIMR_GRA (0x10000000) |
---|
| 3344 | #define MCF_FEC_EIMR_BABT (0x20000000) |
---|
| 3345 | #define MCF_FEC_EIMR_BABR (0x40000000) |
---|
| 3346 | #define MCF_FEC_EIMR_HBERR (0x80000000) |
---|
| 3347 | #define MCF_FEC_EIMR_MASK_ALL (0x00000000) |
---|
| 3348 | #define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) |
---|
| 3349 | |
---|
| 3350 | /* Bit definitions and macros for MCF_FEC_RDAR */ |
---|
| 3351 | #define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) |
---|
| 3352 | |
---|
| 3353 | /* Bit definitions and macros for MCF_FEC_TDAR */ |
---|
| 3354 | #define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) |
---|
| 3355 | |
---|
| 3356 | /* Bit definitions and macros for MCF_FEC_ECR */ |
---|
| 3357 | #define MCF_FEC_ECR_RESET (0x00000001) |
---|
| 3358 | #define MCF_FEC_ECR_ETHER_EN (0x00000002) |
---|
| 3359 | |
---|
| 3360 | /* Bit definitions and macros for MCF_FEC_MMFR */ |
---|
| 3361 | #define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) |
---|
| 3362 | #define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) |
---|
| 3363 | #define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) |
---|
| 3364 | #define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) |
---|
| 3365 | #define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) |
---|
| 3366 | #define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) |
---|
| 3367 | #define MCF_FEC_MMFR_ST_01 (0x40000000) |
---|
| 3368 | #define MCF_FEC_MMFR_OP_READ (0x20000000) |
---|
| 3369 | #define MCF_FEC_MMFR_OP_WRITE (0x10000000) |
---|
| 3370 | #define MCF_FEC_MMFR_TA_10 (0x00020000) |
---|
| 3371 | |
---|
| 3372 | /* Bit definitions and macros for MCF_FEC_MSCR */ |
---|
| 3373 | #define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) |
---|
| 3374 | #define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) |
---|
| 3375 | |
---|
| 3376 | /* Bit definitions and macros for MCF_FEC_MIBC */ |
---|
| 3377 | #define MCF_FEC_MIBC_MIB_IDLE (0x40000000) |
---|
| 3378 | #define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) |
---|
| 3379 | |
---|
| 3380 | /* Bit definitions and macros for MCF_FEC_RCR */ |
---|
| 3381 | #define MCF_FEC_RCR_LOOP (0x00000001) |
---|
| 3382 | #define MCF_FEC_RCR_DRT (0x00000002) |
---|
| 3383 | #define MCF_FEC_RCR_MII_MODE (0x00000004) |
---|
| 3384 | #define MCF_FEC_RCR_PROM (0x00000008) |
---|
| 3385 | #define MCF_FEC_RCR_BC_REJ (0x00000010) |
---|
| 3386 | #define MCF_FEC_RCR_FCE (0x00000020) |
---|
| 3387 | #define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) |
---|
| 3388 | |
---|
| 3389 | /* Bit definitions and macros for MCF_FEC_TCR */ |
---|
| 3390 | #define MCF_FEC_TCR_GTS (0x00000001) |
---|
| 3391 | #define MCF_FEC_TCR_HBC (0x00000002) |
---|
| 3392 | #define MCF_FEC_TCR_FDEN (0x00000004) |
---|
| 3393 | #define MCF_FEC_TCR_TFC_PAUSE (0x00000008) |
---|
| 3394 | #define MCF_FEC_TCR_RFC_PAUSE (0x00000010) |
---|
| 3395 | |
---|
| 3396 | /* Bit definitions and macros for MCF_FEC_PALR */ |
---|
| 3397 | #define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3398 | |
---|
| 3399 | /* Bit definitions and macros for MCF_FEC_PAUR */ |
---|
| 3400 | #define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) |
---|
| 3401 | #define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) |
---|
| 3402 | |
---|
| 3403 | /* Bit definitions and macros for MCF_FEC_OPD */ |
---|
| 3404 | #define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) |
---|
| 3405 | #define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) |
---|
| 3406 | |
---|
| 3407 | /* Bit definitions and macros for MCF_FEC_IAUR */ |
---|
| 3408 | #define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3409 | |
---|
| 3410 | /* Bit definitions and macros for MCF_FEC_IALR */ |
---|
| 3411 | #define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3412 | |
---|
| 3413 | /* Bit definitions and macros for MCF_FEC_GAUR */ |
---|
| 3414 | #define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3415 | |
---|
| 3416 | /* Bit definitions and macros for MCF_FEC_GALR */ |
---|
| 3417 | #define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3418 | |
---|
| 3419 | /* Bit definitions and macros for MCF_FEC_TFWR */ |
---|
| 3420 | #define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) |
---|
| 3421 | |
---|
| 3422 | /* Bit definitions and macros for MCF_FEC_FRBR */ |
---|
| 3423 | #define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) |
---|
| 3424 | |
---|
| 3425 | /* Bit definitions and macros for MCF_FEC_FRSR */ |
---|
| 3426 | #define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) |
---|
| 3427 | |
---|
| 3428 | /* Bit definitions and macros for MCF_FEC_ERDSR */ |
---|
| 3429 | #define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) |
---|
| 3430 | |
---|
| 3431 | /* Bit definitions and macros for MCF_FEC_ETDSR */ |
---|
| 3432 | #define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) |
---|
| 3433 | |
---|
| 3434 | /* Bit definitions and macros for MCF_FEC_EMRBR */ |
---|
| 3435 | #define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) |
---|
| 3436 | |
---|
| 3437 | /* buffer descriptor fields */ |
---|
| 3438 | /* Tx BD fields */ |
---|
| 3439 | #define MCF_FEC_TXBD_R (1 << 15) |
---|
| 3440 | #define MCF_FEC_TXBD_W (1 << 13) |
---|
| 3441 | #define MCF_FEC_TXBD_L (1 << 11) |
---|
| 3442 | #define MCF_FEC_TXBD_TC (1 << 10) |
---|
| 3443 | |
---|
| 3444 | /* Rx BD fields */ |
---|
| 3445 | #define MCF_FEC_RXBD_E (1 << 15) |
---|
| 3446 | #define MCF_FEC_RXBD_RO1 (1 << 14) |
---|
| 3447 | #define MCF_FEC_RXBD_W (1 << 13) |
---|
| 3448 | #define MCF_FEC_RXBD_L (1 << 11) |
---|
| 3449 | #define MCF_FEC_RXBD_LG (1 << 5) |
---|
| 3450 | #define MCF_FEC_RXBD_NO (1 << 4) |
---|
| 3451 | #define MCF_FEC_RXBD_CR (1 << 2) |
---|
| 3452 | #define MCF_FEC_RXBD_OV (1 << 1) |
---|
| 3453 | #define MCF_FEC_RXBD_TR (1 << 0) |
---|
| 3454 | |
---|
| 3455 | /********************************************************************* |
---|
| 3456 | * |
---|
| 3457 | * Random Number Generator (RNG) |
---|
| 3458 | * |
---|
| 3459 | *********************************************************************/ |
---|
| 3460 | |
---|
| 3461 | /* Register read/write macros */ |
---|
| 3462 | #define MCF_RNG_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000])) |
---|
| 3463 | #define MCF_RNG_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004])) |
---|
| 3464 | #define MCF_RNG_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008])) |
---|
| 3465 | #define MCF_RNG_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C])) |
---|
| 3466 | |
---|
| 3467 | /* Bit definitions and macros for MCF_RNG_RNGCR */ |
---|
| 3468 | #define MCF_RNG_RNGCR_GO (0x00000001) |
---|
| 3469 | #define MCF_RNG_RNGCR_HA (0x00000002) |
---|
| 3470 | #define MCF_RNG_RNGCR_IM (0x00000004) |
---|
| 3471 | #define MCF_RNG_RNGCR_CI (0x00000008) |
---|
| 3472 | |
---|
| 3473 | /* Bit definitions and macros for MCF_RNG_RNGSR */ |
---|
| 3474 | #define MCF_RNG_RNGSR_SV (0x00000001) |
---|
| 3475 | #define MCF_RNG_RNGSR_LRS (0x00000002) |
---|
| 3476 | #define MCF_RNG_RNGSR_FUF (0x00000004) |
---|
| 3477 | #define MCF_RNG_RNGSR_EI (0x00000008) |
---|
| 3478 | #define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) |
---|
| 3479 | #define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) |
---|
| 3480 | |
---|
| 3481 | /* Bit definitions and macros for MCF_RNG_RNGER */ |
---|
| 3482 | #define MCF_RNG_RNGER_ENTROPY(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3483 | |
---|
| 3484 | /* Bit definitions and macros for MCF_RNG_RNGOUT */ |
---|
| 3485 | #define MCF_RNG_RNGOUT_OUTPUT(x) (((x)&0xFFFFFFFF)<<0) |
---|
| 3486 | |
---|
| 3487 | /********************************************************************* |
---|
| 3488 | * |
---|
| 3489 | * Real-time Clock (RTC) |
---|
| 3490 | * |
---|
| 3491 | *********************************************************************/ |
---|
| 3492 | /* Register read/write macros */ |
---|
| 3493 | #define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x180000])) |
---|
| 3494 | #define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x180004])) |
---|
| 3495 | #define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x180008])) |
---|
| 3496 | #define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x18000C])) |
---|
| 3497 | #define MCF_RTC_CR (*(vuint32*)(&__IPSBAR[0x180010])) |
---|
| 3498 | #define MCF_RTC_ISR (*(vuint32*)(&__IPSBAR[0x180014])) |
---|
| 3499 | #define MCF_RTC_IER (*(vuint32*)(&__IPSBAR[0x180018])) |
---|
| 3500 | #define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x18001C])) |
---|
| 3501 | #define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x180020])) |
---|
| 3502 | #define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x180024])) |
---|
| 3503 | #define MCF_RTC_OSC_CNT_U (*(vuint32*)(&__IPSBAR[0x180034])) |
---|
| 3504 | #define MCF_RTC_OSC_CNT_L (*(vuint32*)(&__IPSBAR[0x180038])) |
---|
| 3505 | |
---|
| 3506 | /* Bit definitions and macros for MCF_RTC_HOURMIN */ |
---|
| 3507 | #define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x0000003F)<<0) |
---|
| 3508 | #define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x0000001F)<<8) |
---|
| 3509 | |
---|
| 3510 | /* Bit definitions and macros for MCF_RTC_SECONDS */ |
---|
| 3511 | #define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x0000003F)<<0) |
---|
| 3512 | |
---|
| 3513 | /* Bit definitions and macros for MCF_RTC_ALRM_HM */ |
---|
| 3514 | #define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x0000003F)<<0) |
---|
| 3515 | #define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x0000001F)<<8) |
---|
| 3516 | |
---|
| 3517 | /* Bit definitions and macros for MCF_RTC_ALRM_SEC */ |
---|
| 3518 | #define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x0000003F)<<0) |
---|
| 3519 | |
---|
| 3520 | /* Bit definitions and macros for MCF_RTC_CR */ |
---|
| 3521 | #define MCF_RTC_CR_SWR (0x00000001) |
---|
| 3522 | #define MCF_RTC_CR_EN (0x00000080) |
---|
| 3523 | |
---|
| 3524 | /* Bit definitions and macros for MCF_RTC_ISR */ |
---|
| 3525 | #define MCF_RTC_ISR_SW (0x00000001) |
---|
| 3526 | #define MCF_RTC_ISR_MIN (0x00000002) |
---|
| 3527 | #define MCF_RTC_ISR_ALM (0x00000004) |
---|
| 3528 | #define MCF_RTC_ISR_DAY (0x00000008) |
---|
| 3529 | #define MCF_RTC_ISR_1HZ (0x00000010) |
---|
| 3530 | #define MCF_RTC_ISR_HR (0x00000020) |
---|
| 3531 | |
---|
| 3532 | /* Bit definitions and macros for MCF_RTC_IER */ |
---|
| 3533 | #define MCF_RTC_IER_SW (0x00000001) |
---|
| 3534 | #define MCF_RTC_IER_MIN (0x00000002) |
---|
| 3535 | #define MCF_RTC_IER_ALM (0x00000004) |
---|
| 3536 | #define MCF_RTC_IER_DAY (0x00000008) |
---|
| 3537 | #define MCF_RTC_IER_1HZ (0x00000010) |
---|
| 3538 | #define MCF_RTC_IER_HR (0x00000020) |
---|
| 3539 | |
---|
| 3540 | /* Bit definitions and macros for MCF_RTC_STPWCH */ |
---|
| 3541 | #define MCF_RTC_STPWCH_CNT(x) (((x)&0x0000003F)<<0) |
---|
| 3542 | |
---|
| 3543 | /* Bit definitions and macros for MCF_RTC_DAYS */ |
---|
| 3544 | #define MCF_RTC_DAYS_DAYS(x) (((x)&0x0000FFFF)<<0) |
---|
| 3545 | |
---|
| 3546 | /* Bit definitions and macros for MCF_RTC_ALRM_DAY */ |
---|
| 3547 | #define MCF_RTC_ALRM_DAY_DAYS(x) (((x)&0x0000FFFF)<<0) |
---|
| 3548 | |
---|
| 3549 | #define MCF_RTC_RTCGOCNT(x) (((x)&0x0000FFFF)<<0) |
---|
| 3550 | /********************************************************************/ |
---|
| 3551 | |
---|
| 3552 | #endif /* __MCF5225x_H__ */ |
---|