source: rtems/bsps/m68k/genmcf548x/start/init548x.c @ 947c6645

Last change on this file since 947c6645 was 947c6645, checked in by Christian Mauderer <christian.mauderer@…>, on 03/07/22 at 13:06:23

bsps/m68k: Restore license file

Quite some files in the bsps/m68k/genmcf548x mention a
Freescale_license.txt file. The file has been accidentally removed
during the source reorganization in 2018. This commit restores it and
moves it to the right location for licenses.

Update #4625.
  • Property mode set to 100644
File size: 8.3 KB
Line 
1/*
2 * RTEMS generic mcf548x BSP
3 *
4 * The file contains the c part of MCF548x init code
5 *
6 * Parts of the code has been derived from the "dBUG source code"
7 * package Freescale is providing for M548X EVBs. The usage of
8 * the modified or unmodified code and it's integration into the
9 * generic mcf548x BSP has been done according to the Freescale
10 * license terms.
11 *
12 * The Freescale license terms can be reviewed in the file
13 *
14 *    LICENSE.Freescale
15 *
16 * The generic mcf548x BSP has been developed on the basic
17 * structures and modules of the av5282 BSP.
18 */
19
20/*
21 * Copyright (c) 2008 embedded brains GmbH. All rights reserved.
22 *
23 * The license and distribution terms for this file may be
24 * found in the file LICENSE in this distribution or at
25 * http://www.rtems.org/license/LICENSE.
26 */
27
28#include <bsp.h>
29
30#include <string.h>
31
32#include <bsp/linker-symbols.h>
33
34#if defined(HAS_LOW_LEVEL_INIT)
35#define SYSTEM_PERIOD                   10      /* system bus period in ns */
36
37/* SDRAM Timing Parameters */
38#define SDRAM_TWR                       2               /* in clocks */
39#define SDRAM_CASL                      2.5     /* in clocks */
40#define SDRAM_TRCD                      20              /* in ns */
41#define SDRAM_TRP                       20              /* in ns */
42#define SDRAM_TRFC                      75              /* in ns */
43#define SDRAM_TREFI                     7800    /* in ns */
44#endif /* defined(HAS_LOW_LEVEL_INIT) */
45
46extern uint8_t _DataRom[];
47extern uint8_t _DataRam[];
48extern uint8_t _DataEnd[];
49extern uint8_t _BssStart[];
50extern uint8_t _BssEnd[];
51extern uint8_t _BootFlashBase[];
52extern uint8_t _CodeFlashBase[];
53extern uint8_t RamBase[];
54
55void gpio_init(void);
56void fbcs_init(void);
57void sdramc_init(void);
58void mcf548x_init(void);
59
60
61void mcf548x_init(void)
62{
63    size_t i;
64
65#if defined(HAS_LOW_LEVEL_INIT)
66    /* set XLB arbiter timeouts */
67    MCF548X_XLB_ADRTO = 0x00000100;
68    MCF548X_XLB_DATTO = 0x00000100;
69    MCF548X_XLB_BUSTO = 0x00000100;
70#endif
71
72    gpio_init();
73#if defined(HAS_LOW_LEVEL_INIT)
74    fbcs_init();
75    sdramc_init();
76#endif /* defined(HAS_LOW_LEVEL_INIT) */
77
78    /* Copy the vector table to RAM if necessary */
79    if (bsp_vector0_size == bsp_vector1_size) {
80      memcpy(bsp_vector1_begin, bsp_vector0_begin, (size_t) bsp_vector1_size);
81      m68k_set_vbr((uint32_t)bsp_vector1_begin);
82    }
83
84    /* Move initialized data from ROM to RAM. */
85    if (bsp_section_data_begin != bsp_section_data_load_begin) {
86      memcpy(
87        bsp_section_data_begin,
88        bsp_section_data_load_begin,
89        (size_t) bsp_section_data_size
90      );
91    }
92
93    /* Zero uninitialized data */
94    memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
95
96    for (i = 8; i < RTEMS_ARRAY_SIZE(mcf548x_intc_icr_init_values); ++i) {
97      volatile uint8_t *icr = &MCF548X_INTC_ICR0;
98
99      icr[i] = mcf548x_intc_icr_init_values[i];
100    }
101}
102/********************************************************************/
103#if defined(HAS_LOW_LEVEL_INIT)
104void
105fbcs_init (void)
106{
107#ifdef M5484FIREENGINE
108
109volatile uint32_t cscr, clk_ratio, fb_period, ws;
110
111/* boot flash already valid ? */
112if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V))
113  {
114
115    /*
116     * Boot Flash
117     */
118    MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase));
119
120    cscr = (0
121            | MCF548X_FBCS_CSCR_ASET(1)
122            | MCF548X_FBCS_CSCR_WRAH(0)
123            | MCF548X_FBCS_CSCR_RDAH(0)
124            | MCF548X_FBCS_CSCR_AA
125            | MCF548X_FBCS_CSCR_PS_16);
126
127    /*
128     * Determine the necessary wait states based on the defined system
129     * period (XLB clock period) and the CLKIN to XLB ratio.
130     * The boot flash has a max access time of 110ns.
131     */
132    clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7;
133    fb_period = SYSTEM_PERIOD * clk_ratio;
134    ws = 110 / fb_period;
135
136    MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws);
137    MCF548X_FBCS_CSMR0 = (0
138                          | MCF548X_FBCS_CSMR_BAM_2M
139                          | MCF548X_FBCS_CSMR_V);
140
141  }
142
143/* code flash already valid ? */
144if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))
145  {
146
147    /*
148     * Code Flash
149     */
150    MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase));
151
152    /*
153     * Determine the necessary wait states based on the defined system
154     * period (XLB clock period) and the CLKIN to XLB ratio.
155     * The user/code flash has a max access time of 120ns.
156     */
157    ws = 120 / fb_period;
158    MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws);
159    MCF548X_FBCS_CSMR1 = (0
160                          | MCF548X_FBCS_CSMR_BAM_16M
161                          | MCF548X_FBCS_CSMR_V);
162    }
163
164#endif
165}
166#endif /* defined(HAS_LOW_LEVEL_INIT) */
167
168/********************************************************************/
169#if defined(HAS_LOW_LEVEL_INIT)
170void
171sdramc_init (void)
172{
173
174        /*
175         * Check to see if the SDRAM has already been initialized
176         * by a run control tool
177         */
178        if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF))
179        {
180                /*
181         * Basic configuration and initialization
182         */
183                MCF548X_SDRAMC_SDRAMDS = (0
184                        | MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
185                        | MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
186                        | MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
187                        | MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
188                        | MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
189            );
190        MCF548X_SDRAMC_CS0CFG = (0
191            | MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(RamBase))
192            | MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE)
193            );
194        MCF548X_SDRAMC_SDCFG1 = (0
195                        | MCF548X_SDRAMC_SDCFG1_SRD2RW(7)
196                        | MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
197                        | MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
198                        | MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))
199                        | MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))
200                        | MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))
201                        | MCF548X_SDRAMC_SDCFG1_WTLAT(3)
202            );
203                MCF548X_SDRAMC_SDCFG2 = (0
204                        | MCF548X_SDRAMC_SDCFG2_BRD2PRE(4)
205                        | MCF548X_SDRAMC_SDCFG2_BWT2RW(6)
206                        | MCF548X_SDRAMC_SDCFG2_BRD2WT(7)
207                        | MCF548X_SDRAMC_SDCFG2_BL(7)
208            );
209
210                /*
211         * Precharge and enable write to SDMR
212         */
213        MCF548X_SDRAMC_SDCR = (0
214                        | MCF548X_SDRAMC_SDCR_MODE_EN
215                        | MCF548X_SDRAMC_SDCR_CKE
216                        | MCF548X_SDRAMC_SDCR_DDR
217                        | MCF548X_SDRAMC_SDCR_MUX(1)
218                        | MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
219                        | MCF548X_SDRAMC_SDCR_IPALL
220            );
221
222                /*
223         * Write extended mode register
224         */
225                MCF548X_SDRAMC_SDMR = (0
226                        | MCF548X_SDRAMC_SDMR_BNKAD_LEMR
227                        | MCF548X_SDRAMC_SDMR_AD(0x0)
228                        | MCF548X_SDRAMC_SDMR_CMD
229            );
230
231                /*
232         * Write mode register and reset DLL
233         */
234                MCF548X_SDRAMC_SDMR = (0
235                        | MCF548X_SDRAMC_SDMR_BNKAD_LMR
236                        | MCF548X_SDRAMC_SDMR_AD(0x163)
237                        | MCF548X_SDRAMC_SDMR_CMD
238            );
239
240                /*
241         * Execute a PALL command
242         */
243                MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL;
244
245                /*
246         * Perform two REF cycles
247         */
248                MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
249                MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
250
251                /*
252         * Write mode register and clear reset DLL
253         */
254                MCF548X_SDRAMC_SDMR = (0
255                        | MCF548X_SDRAMC_SDMR_BNKAD_LMR
256                        | MCF548X_SDRAMC_SDMR_AD(0x063)
257                        | MCF548X_SDRAMC_SDMR_CMD
258            );
259
260                /*
261         * Enable auto refresh and lock SDMR
262         */
263                MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN;
264        MCF548X_SDRAMC_SDCR |= (0
265                        | MCF548X_SDRAMC_SDCR_REF
266                        | MCF548X_SDRAMC_SDCR_DQS_OE(0xF)
267            );
268    }
269
270}
271#endif /* defined(HAS_LOW_LEVEL_INIT) */
272
273/********************************************************************/
274void
275gpio_init(void)
276{
277
278#ifdef M5484FIREENGINE
279
280    /*
281     * Enable Ethernet signals so that, if a cable is plugged into
282     * the ports, the lines won't be floating and potentially cause
283     * erroneous transmissions
284     */
285    MCF548X_GPIO_PAR_FECI2CIRQ = (0
286
287        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
288        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
289        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII
290        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17
291
292        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
293        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
294        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII
295        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07
296        );
297
298#endif
299    /*
300     * make sure the "edge port" has all interrupts disabled
301     */
302    MCF548X_EPORT_EPIER = 0;
303}
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