source: rtems/bsps/m68k/gen68340/include/m68349.inc @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 13.2 KB
Line 
1/*----------------------------------------------------------------------------
2 * file name: M68349.INC                                P. CADIC CNET/DSM/TAM/CAT
3 *
4 * MC68349 BCC  Board Support Package
5 *
6 * date: 31/07/97
7 *
8 * Description: EQUATES FOR 68349 DEVICES
9 *
10 * Modifications:
11 *      - adapted for GNU CC by G.Montel 26/05/98
12 *----------------------------------------------------------------------------*/
13
14| -- SIM equates --                   
15
16.equ    BASE_REG, 0x3FF00
17.equ    BASE_SIM, 0xEFFFF000            | pour correction du bug 68349 sur IACK
18
19.equ    SIM_MCR, 0x000                  | module configuration register
20.equ    SIM_IDR, 0x002                  | processor identification register
21.equ    SIM_SYNCR, 0x004                | clock synthesizer control register
22.equ    SIM_AVR, 0x006                  | autovector register
23.equ    SIM_RSR, 0x007                  | reset status register
24
25| -- Port A
26.equ    SIM_PORTA, 0x011                | port A data
27.equ    SIM_DDRA, 0x013                 | port A direction data
28.equ    SIM_PPRA1, 0x015                | Port A pin assignement 1
29.equ    SIM_PPRA2, 0x017                | Port A pin assignement 2
30
31| -- Port B
32.equ    SIM_PORTB, 0x019                | port B data
33.equ    SIM_PORTB1, 0x01B               | port B data auxiliary
34.equ    SIM_DDRB, 0x01D                 | port B direction data
35.equ    SIM_PPRB, 0x01F                 | Port B pin assignement
36
37.equ    SIM_SWIV, 0x020    | SW interrupt vector
38.equ    SIM_SYPCR, 0x021    | System protection control register
39.equ    SIM_PICR, 0x022    | Periodic interrupt control register
40.equ    SIM_PITR, 0x024    | Periodic interrupt timing register
41.equ    SIM_SWSR, 0x027    | Sofware service
42
43| -- Chip select
44.equ    SIM_MASKH0, 0x040    | mask register CS0
45.equ    SIM_MASKL0, 0x042    | mask register CS0
46.equ    SIM_ADDRH0, 0x044    | base address CS0
47.equ    SIM_ADDRL0, 0x046    | base address CS0
48
49.equ    SIM_MASKH1, 0x048    | mask register CS1
50.equ    SIM_MASKL1, 0x04A    | mask register CS1
51.equ    SIM_ADDRH1, 0x04C    | base address CS1
52.equ    SIM_ADDRL1, 0x04E    | base address CS1
53
54.equ    SIM_MASKH2, 0x050    | mask register CS2
55.equ    SIM_MASKL2, 0x052    | mask register CS2
56.equ    SIM_ADDRH2, 0x054    | base address CS2
57.equ    SIM_ADDRL2, 0x056    | base address CS2
58
59.equ    SIM_MASKH3, 0x058    | mask register CS3
60.equ    SIM_MASKL3, 0x05A    | mask register CS3
61.equ    SIM_ADDRH3, 0x05C    | base address CS3
62.equ    SIM_ADDRL3, 0x05E    | base address CS3
63
64| -- TIMERS  equates --
65
66| __ TIMER 0
67
68.equ    TIM_MCR0, 0x600    | Module configuration register
69.equ    TIM_IR0, 0x604    | interrupt register
70.equ    TIM_CR0, 0x606    | controle register
71.equ    TIM_SR0, 0x608    | Status/prescaler register
72.equ    TIM_CNTR0, 0x60A    | counter register
73.equ    TIM_PREL10, 0x60C    | Preload register 1
74.equ    TIM_PREL20, 0x60E    | Preload register 2
75.equ    TIM_COM0, 0x610    | Compare register
76
77| __ TIMER 1
78
79.equ    TIM_MCR1, 0x640    | Module configuration register
80.equ    TIM_IR1, 0x644    | interrupt register
81.equ    TIM_CR1, 0x646    | controle register
82.equ    TIM_SR1, 0x648    | Status/prescaler register
83.equ    TIM_CNTR1, 0x64A    | counter register
84.equ    TIM_PREL11, 0x64C    | Preload register 1
85.equ    TIM_PREL21, 0x64E    | Preload register 2
86.equ    TIM_COM1, 0x650    | Compare register
87
88| -- U.A.R.T.  equates --
89
90.equ    UA_MCRH, 0x700    | module configuration register
91.equ    UA_MCRL, 0x701    | module configuration register
92.equ    UA_ILR, 0x704    | Interrupt level
93.equ    UA_IVR, 0x705    | Interrupt vector
94
95.equ    UA_MR1A, 0x710    | Mode register 1 A
96.equ    UA_MR2A, 0x720    | Mode register 2 A
97.equ    UA_CSRA, 0x711    | Clock_select regiter A
98.equ    UA_SRA, 0x711    | status register A
99.equ    UA_CRA, 0x712    | command register A
100.equ    UA_RBA, 0x713    | receive buffer A
101.equ    UA_TBA, 0x713    | transmit buffer A
102
103.equ    UA_IPCR, 0x714    | input port change register
104.equ    UA_ACR, 0x714    | auxiliary control register
105.equ    UA_ISR, 0x715    | interrupt status register
106.equ    UA_IER, 0x715    | interrupt enable register
107
108.equ    UA_MR1B, 0x718    | Mode register 1 B
109.equ    UA_MR2B, 0x721    | Mode register 2 B
110.equ    UA_CSRB, 0x719    | Clock_select regiter B
111.equ    UA_SRB, 0x719    | status register B
112.equ    UA_CRB, 0x71A    | command register A
113.equ    UA_RBB, 0x71B    | receive buffer A
114.equ    UA_TBB, 0x71B    | transmit buffer A
115
116.equ    UA_IP, 0x71D    | Input port register
117.equ    UA_OPCR, 0x71D    | output port control register
118.equ    UA_OPS, 0x71E    | output port bit set
119.equ    UA_OPR, 0x71F    | output port bit reset
120.equ    TX_A_EN, 0x01     | Tx A irq enable
121.equ    TX_B_EN, 0x10     | Tx B irq enable
122.equ    TX_A_DIS, 0xFE     | Tx A irq enable
123.equ    TX_B_DIS, 0xEF     | Tx B irq enable
124.equ    TX_AB_DIS, 0x22
125
126
127| -- DMA equates
128.equ    DMA_MCR0, 0x780    | module configuration register
129.equ    DMA_IR0, 0x784    | Interrupt register
130.equ    DMA_CCR0, 0x788    | Channel control register
131.equ    DMA_CSR0, 0x78A    | Channel status register
132.equ    DMA_FCR0, 0x78B    | Function code register
133.equ    DMA_SARH0, 0x78C    | Source adresse register
134.equ    DMA_SARL0, 0x78E    | Source adresse register
135.equ    DMA_DARH0, 0x790    | destination adresse register
136.equ    DMA_DARL0, 0x792    | destination adresse register
137.equ    DMA_BTCH0, 0x794    | byte transfer register
138.equ    DMA_BTCL0, 0x796    | byte transfer register
139
140.equ    DMA_MCR1, 0x7A0    | module configuration register
141.equ    DMA_IR1, 0x7A4    | Interrupt register
142.equ    DMA_CCR1, 0x7A8    | Channel control register
143.equ    DMA_CSR1, 0x7AA    | Channel status register
144.equ    DMA_FCR1, 0x7AB    | Function code register
145.equ    DMA_SARH1, 0x7AC    | Source adresse register
146.equ    DMA_SARL1, 0x7AE    | Source adresse register
147.equ    DMA_DARH1, 0x7B0    | destination adresse register
148.equ    DMA_DARL1, 0x7B2    | destination adresse register
149.equ    DMA_BTCH1, 0x7B4    | byte transfer register
150.equ    DMA_BTCL1, 0x7B6    | byte transfer register
151
152| -- cache equates
153.equ    CACHE_MCR, 0xFC0        | cache config reg. (long)
154
155| -- quad data memory module (QDMM) equates
156.equ    QDMM_MCR, 0xC00         | QDMM config reg (long)
157.equ    QDMM_QBAR0, 0xC10       | QDMM base 0 (long)
158.equ    QDMM_QBAR1, 0xC14       | QDMM base 1 (long)
159.equ    QDMM_QBAR2, 0xC18       | QDMM base 2 (long)
160.equ    QDMM_QBAR3, 0xC1C       | QDMM base 3 (long)
161
162
163
164|-----------------------------------------------------
165| AST68349 internal registers
166|-----------------------------------------------------
167.equ    EPLD_SPACE, 3                           | "reserved user" space
168.equ    CPU_SPACE, 7                            | "CPU" space
169
170||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
171| GLUE EPLD
172||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
173
174.equ    GLUE_EPLD, 0xB0000000
175
176|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
177| configuration of /CS0 :
178|
179|                 7   6   5   4   3   2   1   0
180|               +---+---+---+---+---+---+---+---+
181|               |ena|val|wid| ws|b31|b30|b29|b28|
182|               +---+---+---+---+---+---+---+---+
183|
184| b[31..28] : base address for decoding /CS[3..0]
185|  the decoding is as follow :
186|
187|  +----------+------------+------+
188|       | a[31..28] | a[27..26] | /CS  |
189|       +-----------+-----------+------+
190|       | b[31..28] |    00             | /CS0 |        each /CS decodes 64 Mbytes
191|       | b[31..28] |    01             | /CS1 |
192|       | b[31..28] |    10             | /CS2 |
193|       | b[31..28] |    11             | /CS3 |
194|       +-----------------------+------+
195|
196| after /RESET, /CS0 is validated for every cycle, until programmed
197|
198| ws : number of wait-states : 0 => 0 ws
199|                              1 => external /dsackx
200| wid : width of chip-select : 0 => 16 bits
201|                              1 => 32 bits
202| ena : enable chip-select   : 0 => disabled
203|                              1 => enabled
204|
205| val : automatic validation. set after reset
206| cleared when /CS0 is configured
207|
208.equ    REG_CS0, 0
209
210
211|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
212| configuration of /CS1 to /CS3:
213|
214|                 7   6   5   4   3   2   1   0
215|               +---+---+---+---+---+---+---+---+
216|               |ena| x |wid| ws| x | x | x | x |
217|               +---+---+---+---+---+---+---+---+
218|
219| ws : number of wait-states : 0 => 0 ws
220|                              1 => external /dsackx
221| wid : width of chip-select : 0 => 16 bits
222|                              1 => 32 bits
223| ena : enable chip-select   : 0 => disabled
224|                              1 => enabled
225.equ    REG_CS1, 1
226.equ    REG_CS2, 2
227.equ    REG_CS3, 3
228
229|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
230| I2C register
231|
232|                 7   6   5   4   3   2   1   0
233|               +---+---+---+---+---+---+---+----+
234|               | x | x | x | x | x | x |clk|data|
235|               +---+---+---+---+---+---+---+----+
236| bidirecionnal pin, open drain output.
237| set bit to 1 to read external state of pin
238|
239.equ    REG_I2C, 4
240
241|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
242| PDCS register
243|
244|                 7   6   5   4   3   2   1   0
245|               +---+---+---+---+---+---+---+---+
246|               |s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
247|               +---+---+---+---+---+---+---+---+
248| pd[5..1] : value read on the DRAM module
249| S12, S11 and S14 : "user reserved" configuration switch
250|
251.equ    REG_PDCS, 5
252
253|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
254| timer1 register
255|
256|                 7   6   5   4   3   2   1   0
257|               +---+---+---+---+---+---+---+---+
258|               |ena| x | x | x | x | x | d1| d0|
259|               +---+---+---+---+---+---+---+---+
260|
261| the timer clock is the 1000Hz clock of the ASTECC platform
262| the timer is reloaded on each write to the register, or if the input
263| TIN1 is set to 0.
264| on overflow, the open drain output TOUT1 is set to 0
265| the timer must be disabled to return TOUT1 to the inactive state
266|
267.equ    REG_TIMER1, 6
268
269|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
270| timer2 register
271|
272|                 7   6   5   4   3   2   1   0
273|               +---+---+---+---+---+---+---+---+
274|               |ena| x | x | x | x | x | d1| d0|
275|               +---+---+---+---+---+---+---+---+
276| the timer clock is the 1000Hz clock of the ASTECC platform
277| the timer is reloaded on each write to the register, or if the input
278| TIN2 is set to 0.
279| on overflow, the open drain output TOUT2 is set to 0
280| the timer must be disabled to return TOUT2 to the inactive state
281|
282.equ    REG_TIMER2, 7
283
284|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
285| baudrate generator register
286|
287|                 7   6   5   4   3   2   1   0
288|               +---+---+---+---+---+---+---+---+
289|               | x | x | x | x | x | d2| d1| d0|
290|               +---+---+---+---+---+---+---+---+
291|
292| d[2..0] : divider of a 3.6864 Mhz clock
293|
294| d[2..0]    :     0      1       2       3      4      5      6      7
295| divides by :     2      4       6       8     10     12     14     16
296| SCLK (Mhz) :  1.8432  0.9216  0.6144  0.4608   x    0.3072   x    0.2304
297| baudrate   :  115200   57600  38400    28800   x     19200   x     14400
298|
299.equ    REG_BAUDRATE, 8
300
301|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
302| IO register
303|
304|                 7   6   5   4   3   2   1   0
305|               +---+---+---+---+---+---+---+---+
306|               | x | x | x |io4|io3|io2|io1|io0|
307|               +---+---+---+---+---+---+---+---+
308|
309| io[4..0] : data written to port
310|
311| maximum current load is about 5 mA per pin
312|
313.equ    REG_IO, 9
314
315|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
316| IO port
317|
318|                 7   6   5   4   3   2   1   0
319|               +---+---+---+---+---+---+---+---+
320|               | x | x | x |io4|io3|io2|io1|io0|
321|               +---+---+---+---+---+---+---+---+
322|
323| io[4..0] : data read from port
324|
325.equ    REG_IO_PORT, 10
326
327|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
328| IO direction register
329|
330|                 7   6   5   4   3   2   1   0
331|               +---+---+---+---+---+---+---+---+
332|               | x | x | x | x | x |dr2|dr1|dr0|
333|               +---+---+---+---+---+---+---+---+
334|
335| dr0 : 0 => io port 0 is configured as input (default after /RESET)
336|       1 => io port 0 is configured as output
337|
338| dr1 : 0 => io port 1 is configured as input (default after /RESET)
339|       1 => io port 1 is configured as output
340|
341| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
342|       1 => io ports 2 to 4 are configured as output
343|
344.equ    REG_DIR_IO, 11
345
346
347
348
349||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
350| DRAM EPLD
351||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
352
353.equ    DRAM_EPLD, 0xA0000000
354
355|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
356| number of wait-state for DRAM
357|
358|                 7   6   5   4   3   2   1   0
359|               +---+---+---+---+---+---+---+---+
360|               | x | x | x | x | x | x |ws1|ws0|
361|               +---+---+---+---+---+---+---+---+
362|
363| ws[1..0]    : 0   1   2   3
364| wait states : 0   1   2   3
365|
366.equ    REG_WS, 0
367
368|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
369| configuration of refresh for DRAM
370|
371|                 7   6   5   4   3   2   1   0
372|               +---+---+---+---+---+---+---+---+
373|               |ena| x | x | x | x | x |rf1|rf0|
374|               +---+---+---+---+---+---+---+---+
375|
376|       rf[1..0] :  0   1    2    3
377|       refresh  : 5µs 10µs 15µs 20µs
378|
379| ena == 0 : refresh disabled
380| ena == 1 : refresh enabled
381|
382.equ    REG_REFRESH, 1
383
384|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
385| configuration of DRAM module size
386|
387|                 7   6   5   4   3   2   1   0
388|               +---+---+---+---+---+---+---+---+
389|               | x | x | x | x | x |sz2|sz1|sz0|
390|               +---+---+---+---+---+---+---+---+
391|
392|  sz[2..0]     : 0   1   2   3   4    5   6   7
393|  size (Mbytes): 4   8   16  32  64  128  0   0
394|
395.equ    REG_CONFIG, 2
396
397|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
398| bus width of /CS0 during reset                bw[1..0]  : 0   1   2       3
399|                                   bus width : 32  16  8   ext. /dsackx
400|
401| state of CS_SWITCH  : sel == 0 => CPU chip_selects  (/CS[3..0])
402|                     : sel == 1 => EPLD chip_selects (/CS[3..0])
403|
404|                 7   6   5   4   3   2   1   0
405|               +---+---+---+---+---+---+---+---+
406|               |bw1|bw0| x | x | x | x | x |sel|
407|               +---+---+---+---+---+---+---+---+
408|
409.equ    REG_BUSWIDTH, 3
410
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